JP2006216092A - Bidirectional shift register, optoelectronic device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a biderectional shift register which will not have shifting generated in shift timing, when switching a transfer direction, and which can surely be operated at low power consumption. <P>SOLUTION: A clock control circuit UBj is provided with a clock supply circuit 20 and a clock input circuit 30. A normal rotation clock signal CK is supplied to a NOR circuit 32 and to a NAND circuit 35, and output signals thereof are selected according to a transfer direction, to generate the clock signal of one system. Even if the output signals of the NOR circuit 32 and the NAND circuit 35 are switched according to the direction of transfer, the logical levels of the clock signal CLK and the normal rotation clock signal CK will match each other. Then, first to fourth clock signals CK1j to CK4j are generated, based on the clock signal CLK of a single system. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a bidirectional shift register, an electro-optical device, and an electronic apparatus that can transfer a pulse bidirectionally.

An electro-optical device that performs display by electro-optical change of an electro-optical material such as liquid crystal or organic EL (electroluminescence) is widely used as a display device such as an information processing device or a television. The electro-optical device includes an active
There is a matrix type. That is, in the active matrix type electro-optical device, the pixel electrode is formed corresponding to the intersection of the scanning line extending in the row direction and the data line extending in the column direction. In addition, a pixel switch such as a thin film transistor that is turned on and off in accordance with a scanning signal supplied to the scanning line is interposed between the pixel electrode and the data line at the intersection. On the other hand, a counter electrode is provided so as to face the pixel electrode through the electro-optic material.

In such a configuration, when an on-voltage scanning signal is applied to a scanning line, a pixel switch connected to the scanning line is turned on. When a data signal corresponding to the gradation (density) is supplied to the data line in this ON state, the data signal is applied to the pixel electrode via the pixel switch, and thus between the pixel electrode and the counter electrode. A voltage corresponding to the data signal is applied to the electro-optical material sandwiched between the two. As a result, the electro-optical material changes electro-optically, and as a result, the transmitted light amount, reflected light amount or light emission amount in the pixel (in either
The amount of light visually recognized on the observer side) corresponds to the voltage of the data signal applied to the pixel electrode. Therefore, a predetermined display can be performed by executing such control for each pixel.

Here, the scanning signal is output from the scanning line driving circuit. This scanning line driving circuit has a Y shift register in which a plurality of stages of circuit blocks are connected in multiple stages along the Y direction. The Y shift register shifts a start pulse supplied at the beginning of the vertical scanning period by using a Y clock signal which is a reference for horizontal scanning. On the other hand, the data signal is output from the data line driving circuit. This data line driving circuit receives image signals supplied in synchronization with vertical scanning and horizontal scanning.
A sampling signal is supplied to a sampling switch that samples each data line within a horizontal effective scanning period. Specifically, the data line driving circuit has an X shift register in which a plurality of stages of circuit blocks are connected in multiple stages along the X direction. The X shift register shifts the start pulse supplied at the beginning of the horizontal scanning period by using an X clock signal synchronized with the cycle in which the image signal is supplied.

By the way, the electro-optical device may be required to have a function of flipping a display image vertically and horizontally as necessary. For example, a projector that enlarges and projects an image is used by placing it on a desk or hanging it from the ceiling, so that it is necessary to invert the display image vertically and horizontally depending on the installation situation. Further, for example, in a rotary panel monitor of a video camera, it is necessary to vertically and horizontally invert the display image according to the rotation angle. For this reason, a type that can transfer the start pulse not only in one direction but also in any direction by a control signal is used for the X and Y shift registers.

Patent Document 1 discloses a shift register capable of bidirectional transfer. The shift register is formed by cascading a plurality of circuit blocks, and each circuit block includes a transfer circuit and a clock control circuit. Focusing on a certain circuit block, the shift register is operated according to an inverted clock signal obtained by inverting the normal clock signal when shifting to the right, and by inverting the normal clock signal when shifting to the left.

In addition, the first and second clock signals are supplied to the transfer circuit, but malfunction may occur if the periods in which these signals become significant overlap. Therefore, Patent Document 2 discloses a waveform shaping circuit shown in FIG. This waveform shaping circuit includes five inverters 711-7.
15 is composed. Inverters 714 and 715 form a latch circuit. Thereby, the overlap period is shortened.
JP 2002-313092 A JP 2003-228315 A

However, in the bi-directional shift register described in Patent Document 1, the signal serving as a transfer reference is switched according to the transfer direction, so that the left / right shift timing is shifted by a half cycle with respect to the first clock signal. End up. As a pixel arrangement of the electro-optical device, a delta arrangement in which pixels are arranged in a staggered pattern is known. The timing shift becomes a problem particularly in a color display device arranged in a delta arrangement. More specifically, as disclosed in JP-A-10-74062, there is a problem in that the RGB arrangement differs depending on the shift direction. In this publication, in order to solve this point, a clock selection circuit shown in FIG. 24 is disclosed. This clock selection circuit includes exclusive OR circuits 721 and 722, and outputs a normal clock signal CL and an inverted clock signal CL * to a plurality of circuit blocks according to a signal CHN indicating the transfer direction. However, since it is necessary to provide a clock selection circuit, the structure of the shift register becomes complicated. In addition, since the exclusive OR circuits 721 and 722 are connected to a long wiring with a stray capacitance, there is a disadvantage that a large driving capability is required. Further, in the waveform shaping circuit described in Patent Document 2, in order to align the phases of the normal clock signal CL and the inverted clock signal CL *, it is necessary to use inverters 712 to 715 having high driving capability, There is a problem that electric power increases.

The present invention has been made in view of such circumstances, and a bidirectional shift register that does not shift in shift timing even when the transfer direction is switched and operates reliably with low power consumption, and an electro-optical device using the same It is another object of the present invention to provide an electronic device.

In order to solve the above-described problem, a bidirectional shift register according to the present invention includes a plurality of transfer unit circuits that sequentially shift pulses based on a normal control clock signal and an inverted control clock signal, and the plurality of transfer units. A plurality of clock control circuits provided corresponding to each of the circuits and supplying a normal control clock signal and an inverted control clock signal to the transfer unit circuit,
The pulse can be transferred bidirectionally in accordance with a transfer direction control signal that indicates the transfer direction of the pulse, and each of the plurality of clock control circuits has a normal input clock signal and an inverted input obtained by inverting the normal input clock signal. A first enable signal generation circuit that detects that a clock signal is alternately supplied as a supply clock signal, satisfies a first condition, and generates a negative logic first enable signal that permits input of the supply clock signal A second enable signal generation circuit that detects that the second condition is satisfied and generates a positive logic second enable signal that permits input of the supply clock signal; and the supply clock signal and the first A NOR circuit to which an enable signal is input, and a NAN to which the supply clock signal and the second enable signal are input
Based on the D circuit and the transfer direction control signal, the output signal of the NOR circuit and the NAND
A selection circuit for selecting one of the output signals of the circuit and outputting it as a clock signal; the normal control clock signal whose logic level is the same as the clock signal; and the inverted control clock whose logic level is inverted from the clock signal A clock supply circuit that generates a signal and supplies the signal to the transfer unit circuit.

According to this bidirectional shift register, the normal control clock signal (for example, the first clock signal CK1 and the third clock signal CK3 in the embodiment) and the inverted control clock signal (for example, the second clock) supplied to the unit transfer circuit. The signal CK2 and the fourth clock signal CK4) are supplied from the clock control circuit. Regardless of the transfer direction, each clock control circuit is supplied with one of the normal input clock signal (for example, the normal clock signal CK in the embodiment) or the inverted input clock signal (for example, the inverted clock signal CKB in the embodiment). Captured as a signal. Here, the supply clock signal is supplied to the NOR circuit and the NAND circuit, and the output signals thereof are selected according to the transfer direction to generate one system of clock signals. The NOR circuit calculates the logical product of negative logic and outputs the operation result as positive logic, while the NAND circuit calculates the logical product of positive logic and outputs the operation result as negative logic. That is, according to the transfer direction, the NOR circuit and N
Even if the output signal of the AND circuit is switched, the logic levels of the clock signal and the supplied clock signal match. Then, a normal rotation control clock signal and an inversion control clock signal are generated based on one system of clock signals. Thereby, even if the transfer direction is switched, the phase relationship between the supplied clock signal, the normal rotation control clock signal, and the inverted control clock signal can be fixed.

Further, in order to supply the normal input clock signal and the inverted input clock signal to a plurality of clock control circuits, for example, two signal lines can be used to supply these signals to each clock control circuit. . In this case, since it is necessary to extend the signal line from the clock control circuit at the right end to the clock control circuit at the left end, a stray capacitance is attached thereto. If the normal input clock signal and the inverted input clock signal to be supplied to the signal line are switched depending on the transfer direction, it is necessary to separately provide a combinational logic circuit for switching, and a combinational logic circuit having a large driving capability is used. There is a need. However, according to the present invention, if attention is paid to a certain clock control circuit, even if the transfer direction is switched, the supply clock signal taken into the clock control circuit is either a normal input clock signal or an inverted input clock signal. On the other hand. Therefore, a combinational logic circuit having a large driving capability can be eliminated.

The above-described transfer unit circuit of the bidirectional shift register includes a first switch means provided between the first terminal and the first connection point, and a first switch means provided between the first connection point and the second terminal. 2 switch means, a third switch means provided between the second connection point and the first terminal, and a fourth switch means provided between the second connection point and the second terminal. The first switch means is a P-channel type first controlled on / off based on the inversion control clock signal.
A first transistor and an N-channel second transistor whose on / off is controlled based on the normal rotation control clock signal, and when at least one of the first transistor and the second transistor is turned on, the first transistor A logic level state of the second connection point is set according to a logic level state of the terminal, and the second switch means is an N-channel type whose on / off is controlled based on the normal rotation control clock signal. A third transistor and a fourth P-channel transistor whose on / off is controlled based on the inverted control clock signal, and when at least one of the third transistor and the fourth transistor is turned on, The logic level state of the second connection point is set according to the logic level state of two terminals, and the third switch means When the direction control signal is at one logic level, an output signal corresponding to the state of the second connection point is supplied to the first terminal, and the fourth switch means has the transfer direction control signal at the other logic level. The output signal corresponding to the state of the second connection point
It is preferable to supply the terminal.

According to the present invention, pulses can be transferred by controlling on / off of the first switch means and the second switch means. Here, when the transfer direction is one direction, the first switch means functions as a write switch for writing a pulse, and the second switch means functions as a hold switch for storing the logic level of the pulse. When the transfer direction is the other direction, the first switch means functions as a hold switch and the second switch means functions as a write switch. Here, the case where at least one of the first transistor and the second transistor is turned on includes a case where either one is turned on and a case where both are turned on. For example, the former specific configuration corresponds to a transfer gate, and the latter specific configuration corresponds to, for example, a clocked inverter.

The transfer unit circuit includes a first switch means provided between the first terminal and the first connection point, and a second switch means provided between the first connection point and the second terminal. , An inverting circuit provided between the first connection point and the second connection point, a first clocked inverter provided between the second connection point and the first terminal, and the second connection. A second clocked inverter provided between a point and the second terminal, wherein the first switch means and the second switch means are based on the forward control clock signal and the inverted control clock signal. ON / OFF is controlled, the first clocked inverter becomes active when the transfer direction control signal is at one logic level, and becomes inactive when the transfer direction control signal is at the other logic level, The second Click clocked inverter, the transfer direction control signal becomes active when the other logic level, and the transfer direction control signal becomes inactive when the one logic level, it is preferable.

Further, a first inversion control clock signal is supplied to the first transistor as the inversion control clock signal, a first normal control clock signal is supplied to the second transistor as the normal control clock signal, and the first transistor The third transistor is supplied with the second normal control clock signal as the normal control clock signal, the fourth transistor is supplied with the second reverse control clock signal as the reverse control clock signal, and the clock supply circuit The clock signal is supplied to one input terminal, and the first forward rotation control clock signal is output N
An AND circuit, a first inversion circuit that inverts the first normal control clock signal and outputs the first inversion control clock signal, the clock signal is supplied to one input terminal, and the other input terminal A NOR circuit that is supplied with the first inversion control clock signal and outputs the second normal rotation control clock signal; and inverts the second normal rotation clock control signal to generate the second inversion control clock signal; And a second inverting circuit that supplies the other input terminal of the NAND circuit.

According to the present invention, the clock supply circuit is configured by a flip-flop, and based on the clock signal, the first normal rotation control clock signal, the first inversion control clock signal, the second normal rotation control clock signal, and the second inversion control clock signal. Is generated. Here, when the clock signal falls, the on / off state is determined in the order of the first transistor → the second transistor → the third transistor → the fourth transistor, and when the clock signal rises, the third transistor → the first transistor
On / off is determined in the order of transistor → second transistor. First switch means and second switch means
The switch means toggles, and it is necessary to switch the on / off state during pulse transfer. That is, if the first switch means is in the on state and the second switch means is in the off state, it is necessary to turn off the first switch means and turn on the second switch means. By determining ON / OFF in the above-described order, the first switch means and the second switch at the time of state transition
The switch means is not turned on at the same time. Since the pulses are sequentially transferred between adjacent transfer unit circuits, the first switch means and the second switch means do not turn on at the same time. Therefore, when transferring a pulse from one transfer unit circuit to the next transfer unit circuit, Therefore, it is possible to prevent the pulse from passing through the next transfer unit circuit and being transferred to the next transfer unit circuit.

Here, the first enable signal generation circuit is active when a pulse input to the transfer unit circuit of the own stage or a pulse output from the transfer unit circuit of the own stage is active, or the transfer direction is one direction. In this case, at least one of the fact that the first switch means of the transfer unit circuit which is the next stage is in the OFF state is the first condition, and the second enable signal generation circuit is connected to the transfer unit circuit of the own stage. When the input shift pulse or the shift pulse output from the transfer unit circuit of the own stage is active, or when the transfer direction is the other direction, the second switch means of the transfer unit circuit which is the next stage is turned off. It is preferable that at least one of the states is the second condition. Power consumption can be reduced by providing that the pulse input to the transfer unit circuit of the own stage or the pulse output from the transfer unit circuit of the own stage is active. Moreover, by setting the next-stage switch means to be in an OFF state, it is possible to prevent a pulse from passing through and to reliably transfer the pulse.

Next, an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines. A scanning line driving circuit for driving the plurality of scanning lines; and a data line driving circuit for driving the plurality of data lines. The scanning line driving circuit includes the above-described bidirectional shift register and is adjacent to the scanning line driving circuit. Generating a plurality of scanning signals so as to become active during a period in which the shift signals output from the transfer unit circuit are simultaneously active, and supplying the plurality of scanning signals to the plurality of scanning lines, respectively. And According to the present invention, it is possible to select the scanning line from the upper end to the lower end and to select the scanning line from the lower end to the upper end by switching the order of activating the plurality of scanning signals.

Next, another electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines. A scanning line driving circuit for driving the plurality of scanning lines and a data line driving circuit for driving the plurality of data lines, the data line driving circuit including the bidirectional shift register described above,
A plurality of sampling signals obtained by generating a plurality of sampling signals so as to be active during a period in which each shift signal output from the adjacent transfer unit circuit is simultaneously active, and a plurality of sampling signals obtained by sampling the image signals according to each of the plurality of sampling signals The data signal is supplied to each of the plurality of data lines. According to the present invention, it is possible to select the data line from the right end to the left end and to select the data line from the left end to the right end by switching the order of supplying the data signals to the plurality of data lines.
Next, an electronic apparatus according to the present invention preferably includes the above-described electro-optical device. Such an electronic device may include, for example, a video camera or a projector that can display a normal image and a reverse image.

<1. Bidirectional shift register>
First, the bidirectional shift register 1 according to the present invention will be described. The bidirectional shift register 1 switches the transfer direction of the start pulse SP in accordance with the transfer direction control signal DIR that indicates the transfer direction. Specifically, when the transfer direction control signal DIR is at the H level, the start pulse SP is shifted in the right direction (from left to right), and when the transfer direction control signal DIR is at the L level, the left direction (
The start pulse SP is shifted from right to left.

FIG. 1 shows a block diagram of the bidirectional shift register 1. As shown in this figure, the bidirectional shift register 1 includes a data transfer unit 2 and a clock control unit 3. Data transfer unit 2 in this example
Includes n data transfer unit circuits Ua1, Ua2,..., Uaj (j is a natural number not less than 2 and less than n), Uan, transfer gates TG1 and TG2, and an inverter INV1.
The inverter INV1 inverts the logic level of the transfer direction control signal DIR to generate an inverted transfer direction control signal DIRB. When the transfer direction control signal DIR is at the H level, the transfer gate TG1 is turned on and the transfer gate TG2 is turned off. On the other hand, when the transfer direction control signal DIR is at the L level, the transfer gate TG1 is turned off and the transfer gate TG2 is turned on. That is, when the transfer direction control signal DIR indicates an H level shift instruction, the start pulse SP is supplied to the rightmost data transfer unit circuit Ua1, and the transfer direction control signal DIR indicates an H level shift instruction. In this case, the start pulse SP is supplied to the leftmost data transfer unit circuit Uan.

FIG. 2 shows a circuit diagram of the j-th data transfer unit circuit Uaj. The other data transfer unit circuits are similarly configured. As shown in the figure, the data transfer unit circuit Uaj includes clocked inverters 10 and 11, a NOR circuit 12, P-channel transistors P1 and P2, and N-channel transistors N1 and N2. When the transfer direction is the right direction, the transistors P1 and N1 constitute a write switch SWaj, and the write switch SWaj is provided between the first terminal S1 and the first connection point S3. The transistors P2 and N2 constitute a hold switch SWbj, and the hold switch SWbj is provided between the first connection point S3 and the second terminal S2. The NOR circuit 12 provided between the first connection point S3 and the second connection point S4 functions as an inverting circuit when the reset signal REST is inactive. Further, a clocked inverter 10 is provided between the second connection point S4 and the first terminal S1, and a clocked inverter 11 is provided between the second connection point S4 and the second terminal S2.

The transistor P1 is supplied with the first clock signal CK1j, the transistor N1 is supplied with the second clock signal CK2j, the transistor N2 is supplied with the third clock signal CK3j, and the transistor P2 is supplied with the fourth clock signal CK4j. First to fourth clock signals CK1j to
CK4j is supplied from a clock control circuit Ubj provided corresponding to the data transfer unit circuit Uaj, and an input signal INj and an output signal OUTj of the data transfer unit circuit Uaj are supplied to the clock control circuit Ubj.

The shift signal Qj is taken out from the NOR circuit 12. The reset signal REST is supplied to one input terminal of the NOR circuit 12, and the connection point of the write switches SWaj and SWbj is connected to the other input terminal. The reset signal REST becomes active at the H level. When the H level reset signal REST is supplied, the logical level of the shift signal Qj is forcibly set to the L level. When the power is turned on, the logic levels of the shift signals Q1 to Qn of the data transfer unit circuits Ua1 to Uan are varied. In such a case, the reset signal REST is used to align the logic levels of the output signals Q1 to Qn to the L level.

The clocked inverter 10 operates as an inverter when the inverted transfer direction control signal DIRB is at the H level, while the output terminal is in a high impedance state when the inverted transfer direction control signal DIRB is at the L level. The clocked inverter 11 operates as an inverter when the transfer direction control signal DIR is at the H level, while the output terminal is in a high impedance state when the transfer direction control signal DIR is at the H level.

If the reset signal REST is inactive (L level) and the transfer direction control signal DIR is H level, the transfer direction is rightward, and the equivalent circuit of the data transfer unit circuits Uaj and Uaj + 1 is shown in FIG. ). In this case, the clocked inverter 10 becomes inactive, and the NOR circuit 12 functions as an inverter. The reset signal RES
If T is inactive (L level) and the transfer direction control signal DIR is L level,
The transfer direction is leftward, and the equivalent circuit of the data transfer unit circuits Uaj and Uaj + 1 is shown in FIG.
It will be shown in

Next, the clock control unit 3 shown in FIG. 1 will be described. The clock control unit 3 includes an inverter INV2 that inverts the normal clock signal CK and outputs an inverted clock signal CKB, and a plurality of clock control circuits Ub1, Ub2,..., Ubj,. Each of the clock control circuits Ub1 to Ubn is provided corresponding to each of the plurality of data transfer unit circuits Ua1 to Uan, and includes a clock supply circuit 20 and a clock input circuit 30. The odd-numbered clock control circuits Ub1, Ub3, Ub5,... Are supplied with the normal rotation clock signal CK,
The inverted clock signal CKB is supplied to the clock control circuits Ub2, Ub4, Ub6,. In this example, “j” is an odd number.

FIG. 4 shows a block diagram of the j-th stage clock control circuit Ubj. The clock input circuit 30
A first enable signal generation circuit 31, a NOR circuit 32, a transfer gate 33, a second enable signal generation circuit 34, a NAND circuit 35, and a transfer gate 36 are provided. The transfer gate 33 is turned on when the transfer direction control signal DIR is H level, that is, when the transfer direction is right direction, and when the transfer direction control signal DIR is L level, that is, when the transfer direction is left direction. Will be off. On the other hand, the transfer gate 36 is turned on when the inverted transfer direction control signal DIRB is H level, that is, when the transfer direction is leftward, and when the inverted transfer direction control signal DIRB is L level, that is, the transfer direction is changed. Turns off when in the right direction. Therefore, when the transfer direction is the right direction, the output signal of the NOR circuit 32 is supplied to the clock supply circuit 20 as the clock signal CLK, whereas when the transfer direction is the left direction, the output signal of the NAND circuit 35 is The clock signal CLK is supplied to the clock supply circuit 20. The transfer gates 33 and 36 function as a selection unit that selects the output signal of the NOR circuit 32 and the output signal of the NAND circuit 36 according to the transfer direction control signal DIR and outputs the selected signal as the clock signal CLK.

The first enable signal EN1 that is active at the L level is supplied to one input terminal of the NOR circuit 32, and the normal clock signal CK is supplied to the other input terminal. The first enable signal EN1 is a signal that permits input of the normal rotation clock signal CK. The first enable signal generation circuit 31 includes NAND circuits 311 and 313 and an inverter 312 as shown in FIG. First, the output signal of the NAND circuit 311 becomes active (H level) when either one of the input signal INj and the output signal OUTj of the data transfer unit circuit Uaj of its own stage becomes active (L level). The output signal of the NAND circuit 311 is supplied to one input terminal of the NAND circuit 313, and the second clock signal CK is supplied to the other input terminal.
2j + 1 is supplied. The second clock signal CK2j + 1 is a signal that instructs the data transfer unit circuit Uaj + 1 of the next stage to write the input signal INj + 1 when the transfer direction is the right direction, and becomes active at the H level. Therefore, the first enable signal generation circuit 31 is the next stage when either one of the input signal INj and the output signal OUTj of the data transfer unit circuit Uaj of its own stage is active and the transfer direction is the right direction. The data transfer unit circuit Uaj + 1 functions as means for detecting that writing has become impossible.

The second enable signal generation circuit 34 includes NAND circuits 341 and 342 and an inverter 343 as shown in FIG. First, the output signal of the NAND circuit 341 becomes active (H level) when one of the input signal INj and the output signal OUTj of the data transfer unit circuit Uaj of its own stage becomes active (L level). The output signal of the NAND circuit 341 is supplied to one input terminal of the NAND circuit 342, and the fourth input terminal is supplied to the other input terminal.
A clock signal CK4j-1 is supplied. The fourth clock signal CK4j-1 is a signal that instructs the data transfer unit circuit Uaj-1 at the next stage to write the input signal INj-1 when the transfer direction is the left direction, and becomes active at the L level. Therefore, the second enable signal generation circuit 34
When either one of the input signal INj and the output signal OUTj of the data transfer unit circuit Uaj of the own stage is active and the transfer direction is the left direction, the data transfer unit circuit U of the next stage
It functions as a means for detecting that aj-1 has become unwritable.

By the first enable signal circuit 31 and the second enable signal generation circuit 34 described above,
When the input signal INj and the output signal OUTj of the data transfer unit circuit Uaj at its own stage are inactive, the capture of the normal clock signal CK is stopped. At this time, the logic level of the clock signal CLK output from the clock input circuit 30 is fixed, and the clock supply circuit 20
And the logic level of each node of the data transfer unit circuit Uaj is fixed. That is, among the plurality of data transfer unit circuits Ua1 to Uan and the plurality of clock control circuits Ub1 to Ubn, only the circuit that receives a pulse from the previous stage and transfers the pulse to the subsequent stage operates, and the other circuits stop operating. . As a result, power consumption is greatly reduced. Further, the first enable signal circuit 31 and the second enable signal generation circuit 34 detect that the data transfer unit circuit in the next stage has become unwritable and permit the input of the normal clock signal CK. It is possible to prevent malfunction due to penetration of the.

Next, the NOR circuit 32 shown in FIG. 4 functions as a logic circuit that calculates a logical product of negative logic and outputs a calculation result as positive logic. Therefore, if the first enable signal EN1 is active, the normal clock signal CK is captured, the logic level is inverted, and the transfer gate 33 is inverted.
To supply. The NAND circuit 35 functions as a logic circuit that calculates a logical product of positive logic and outputs the operation result as negative logic. Therefore, if the second enable signal EN2 is active, the normal clock signal CK is taken in, the logic level is inverted, and the transfer gate 3
6 is supplied. As described above, the transfer gates 33 and 36 select the output signals of the NOR circuit 32 and the NAND circuit 36 and output the clock signal CLK. Therefore, the transfer gates 33 and 36 are generated based on the normal clock signal CK regardless of the transfer direction. This is important when the bidirectional shift register 1 is used as a drive circuit for an image display device. That is, since the type of the clock signal input to the clock control circuit Ubj is fixed regardless of the transfer direction, the timing relationship between the shift signals Q1 to Qn and the normal rotation clock signal CK is fixed. As a result, even if the pixel arrangement is a delta arrangement, there is no problem and image inversion can be easily performed.

By the way, the first enable signal generation circuit 31 and the second enable signal generation circuit 3 described above.
4 includes NAND circuits 311 and 341 for calculating a negative logical OR of the input signal INj and the output signal OUTj as shown in FIG. That is, since the functions of the NAND circuits 311 and 341 are the same, they may be combined. Therefore, the clock input circuit 30 may be configured as shown in FIG. The clock input circuit 30 shown in FIG. 6 includes a 3-input NOR circuit 32 ′ instead of the 2-input NOR circuit 32, and includes a 3-input NAND circuit 35 ′ instead of the 2-input NAND circuit 35. An inverter 38 is provided to supply a negative logic signal to the NOR circuit 32 ′. By configuring the clock input circuit 30 in this way, the configuration can be simplified and the power consumption can be reduced.

Next, the clock supply circuit 20 shown in FIG. 4 will be described. The clock supply circuit 20
A NAND circuit 21, inverters 22 and 23, and a NOR circuit 24 are provided. As shown in FIG. 7, the inverters 22 and 23 are configured by connecting a P-channel transistor Tr1 and an N-channel transistor Tr2 in series between a high-potential-side power supply Vdd and a low-potential-side power supply Vss. . As shown in FIG. 8A, the NAND circuit 21 includes P-channel transistors Tr3 and Tr4 connected in parallel between the high-potential-side power supply Vdd and the node Z1, and the node Z1 and the low-potential-side power supply. N-channel transistors Tr5 and Tr6 connected in series with Vss. Further, the NOR circuit 24 includes a high potential side power supply V
P-channel transistors Tr7 and Tr connected in series between dd and node Z2
8 and N-channel transistors Tr9 and Tr10 connected in parallel between the node Z2 and the low-potential-side power supply Vss.

FIG. 9 shows input / output characteristics of the NAND circuit 21, inverters 22 and 23, and NOR circuit 24. In the figure, Vinv is the threshold potential of the inverters 22 and 23, and Vnand is N
The threshold potential of the AND circuit 21 and Vnor indicate the threshold potential of the NOR circuit 24, respectively. Threshold potential Vn
and is higher than the threshold potential Vinv. This is because, as shown in FIG. 8A, N-channel transistors Tr4 and Tr5 are connected in series between the node Z1 and the low-potential-side power supply Vss. The threshold potential Vnor is lower than the threshold potential Vinv. This is because, as shown in FIG. 8B, P-channel transistors Tr7 and Tr8 are connected in series between the node Z2 and the high-potential-side power supply Vdd.

Next, the operation of the clock supply circuit 20 will be described. FIG. 10 shows a timing chart when the logic level of the clock signal CLK changes from the H level to the L level. In addition,
It is assumed that the threshold potentials of the P-channel transistors P1 and P2 shown in FIG. 2 are Vp, and the threshold potentials of the N-channel transistors N1 and N2 are Vn. First, in the initial state, the level of the clock signal CLK is H level. At this time, the first clock signal CK1j
Is L level, the transistor P1 is on, the second clock signal CK2j is H level, the transistor N1 is on, the third clock signal CK3j is L level, the transistor N2 is off, and the fourth clock signal CK4j is H level. P2 is in an off state.

At time ta0, the clock signal CLK starts to fall, and at time ta1, the threshold potential V
When reaching nand, the first clock signal CK1j output from the NAND circuit 21 starts to rise. At time ta2, the level of the first clock signal CK1j is the threshold potential Vi.
When nv is reached, rising of the second clock signal CK2j output from the inverter 22 starts. At this time, the level of the first clock signal CK1j does not reach the threshold potential Vp, and the level of the first clock signal CK1j becomes the threshold potential Vp at time ta3. Then, the transistor P1 is turned off.

When the time ta4 is reached, the level of the second clock signal CK2j reaches the threshold potential Vnor, and NO
The rise of the third clock signal CK3j output from the R circuit 24 starts. here,
Time T during which the level of the second clock signal CK2j changes from the threshold potential Vnor to the threshold potential Vn
When comparing a1 and the time Ta2 until the level of the third clock signal CK3j reaches the threshold potential Vn from the L level, the time Ta1 is shorter than the time Ta2. This is because the threshold potential Vnor of the NOR circuit 24 is low as shown in FIG. In an actual circuit, NO
The R circuit 24 has a propagation delay time, but Ta1 <Ta2. For this reason, the transistor N1 is turned off at the time ta5, and the transistor N2 is turned on at the time ta6.

Thereafter, at time ta7, the level of the third clock signal CK3j reaches the threshold potential Vinv, and the falling of the fourth clock signal CK4j output from the inverter 23 starts. Then, at time ta8, the level of the fourth clock signal CK4 reaches the threshold potential Vp.
As a result, the transistor P2 is turned on. Accordingly, the signal is determined in the order of transistor P1, transistor N1, transistor N2, and transistor P2. Here, since the transistors P1 and N1 constitute a write switch and the transistors P2 and N2 constitute a hold switch, the hold switch changes from the off state to the on state after the write switch changes from the on state to the off state. .

FIG. 11 shows a timing chart when the logic level of the clock signal CLK changes from the L level to the H level. First, in the initial state, the level of the clock signal CLK is L level. At this time, the third clock signal CK3j is H level and the transistor N2 is in the on state, the fourth clock signal CK4j is L level and the transistor P2 is in the on state, the first clock signal CK1j is H level and the transistor P1 is in the off state, The clock signal CK2j is L
At the level, the transistor P1 is off.

At time tb0, the clock signal CLK starts to rise, and at time tb1, the threshold potential V
When reaching nor, the third clock signal CK3j output from the NOR circuit 24 starts to fall. When the level of the third clock signal CK3j reaches the threshold potential Vinv at time tb2, the rising of the fourth clock signal CK4j output from the inverter 23 starts. At this time, the level of the third clock signal CK3j does not reach the threshold potential Vn, and the level of the third clock signal CK3j becomes the threshold potential Vn at time tb3. Then, the transistor N2 is turned off.

At time tb4, the level of the fourth clock signal CK4j reaches the threshold potential Vnand, and N
The first clock signal CK1j output from the AND circuit 21 starts to fall. Here, a time Tb1 when the level of the fourth clock signal CK4j changes from the threshold potential Vnand to the threshold potential Vp and a time Tb2 when the level of the first clock signal CK1j reaches the threshold potential Vp from the H level are compared. Tb1 is shorter than time Tb2. This is because the threshold potential Vnand of the NAND circuit 21 is high as shown in FIG. In an actual circuit, the NAND circuit 21 has a propagation delay time, but Tb1 <Tb2. Therefore, the transistor P2 is turned off at time tb5, and the transistor P1 is turned on at time tb6.

Thereafter, at time tb7, the level of the first clock signal CK1j reaches the threshold potential Vinv, and the rising of the second clock signal CK2j output from the inverter 22 starts. Then, at time tb8, the level of the second clock signal CK2j reaches the threshold potential Vn. As a result, the transistor N1 is turned on. Accordingly, the signal is determined in the order of the transistor N2, the transistor P2, the transistor P1, and the transistor N1. Here, the transistors P1 and N1 constitute a write switch SWaj, and the transistors P2 and N2
Constitutes the hold switch SWbj, so that the hold switch SWaj changes from the off state to the on state after the write switch SWbj changes from the on state to the off state.

Next, the transfer operation of the jth data transfer unit circuit Uaj driven by the first to fourth clock signals CK1j to CK4j and the j + 1th data transfer unit circuit Uaj + 1 adjacent thereto will be described. explain. However, the transfer direction of the start pulse SP is the right direction. Further, as shown in FIG. 12, it is assumed that the input signal INj enters the data transfer unit circuit Uaj and the shift operation is performed based on the forward clock signal CK and the inverted clock signal CKB. Further, the falling period of the normal clock signal CK is T1, the period when the normal clock signal is L level is T2, and the rising time of the normal clock signal CK is T3. Further, in the initial state, it is assumed that the input signal INj is at L level and the normal clock signal CK is at H level.

FIG. 13 shows an equivalent circuit of the data transfer unit circuit Uaj and the (j + 1) th data transfer unit circuit Uaj + 1. In this figure, since the transfer direction is the right direction, the transfer gate 33 is turned on and the transfer gate 36 is turned off in the clock input circuit 30 shown in FIG. In this case, when the first enable signal EN1 becomes active, the normal clock signal CK is taken in by the NOR circuit 32 in the data transfer unit circuit Uaj, and a signal obtained by inverting the normal clock signal CK is used as the clock signal CLK. 20 is supplied. On the other hand, in the data transfer unit circuit Uaj + 1, the inverted clock signal CKB is taken in by the NOR circuit 32, and a signal obtained by inverting the inverted clock signal CKB is supplied to the clock supply circuit 20 as the clock signal CLK.

In the initial state, as shown in FIG. 13A, the write switches SWaj and SWaj + 1 are turned off, and the hold switches SWbj and SWbj + 1 are turned on.
Next, in the period T1, the data transfer unit circuit Uaj is controlled according to the rising waveform of the clock signal CLK, while the data transfer unit circuit Uaj + 1 is controlled by the clock signal CLK.
Control is performed according to the falling waveform. At this time, since the input signal INj + 1 and the output signal OUTj + 1 of the data transfer unit circuit Uaj + 1 are inactive (H level), the state of the write switch SWaj + 1 and the hold switch SWbj + 1 changes. Absent. On the other hand, in the data transfer unit circuit Uaj, the input signal INj is active (L level), and
Since the next-stage write switch SWaj + 1 is in the off state, the first enable signal EN1 becomes active. Therefore, the clock signal CLK rises from the L level to the H level. As described with reference to FIG. 11, when the clock signal CLK rises, the transistor N2 changes from the on state to the off state, and then the transistor P2 changes from the on state to the off state. Accordingly, as shown in FIG. 13B, the hold switch SWbj is turned off. Next, the transistor P1 changes from the off state to the on state, and then the transistor N1 changes from the off state to the on state. At this time, the write switch SWaj is turned on as shown in FIG. Then, the input signal INj is output as the output signal OUTj through the NOR circuit 12 and the inverter 11.

Next, in the period T2, since the level of the clock signal CLK does not change, the state of the data transfer unit circuit Uaj and the data transfer unit circuit Uaj + 1 is maintained (see FIG. 13D).
Next, in the period T3, the output signal OUTj of the data transfer unit circuit Uaj is active (
L level), and the input signal INj + 1 of the data transfer unit circuit Uaj + 1 is also activated.
For this reason, the data transfer unit circuit Uaj is controlled according to the falling waveform of the clock signal CLK, while the data transfer unit circuit Uaj + 1 is controlled according to the rising waveform of the clock signal CLK.

First, in the data transfer unit circuit Uaj, since the output signal OUTj is active (L level) and the write switch SWaj + 1 in the next stage is in an off state, the first enable signal EN1 becomes active. For this reason, the clock signal CLK falls from the H level to the L level. As described with reference to FIG. 10, when the clock signal CLK falls, the transistor P1 changes from the on state to the off state, and then the transistor N1 changes from the on state to the off state. Therefore, as shown in FIG. 13E, the hold switch SWbj
Is turned off. Next, transistor N2 changes from an off state to an on state, and then
The transistor P2 changes from the off state to the on state. At this time, the hold switch SW2 is turned on as shown in FIG. Then, a latch circuit is configured by the NOR circuit 12 and the inverter 11, and the L level is stored.

Next, since the output signal OUTj is active (L level) and the next-stage write switch SWaj + 2 (not shown) is in the OFF state, the data transfer unit circuit Uaj + 1 is in the first state.
The enable signal EN1 becomes active. Therefore, the clock signal CLK rises from the L level to the H level. At the rising edge of the clock signal CLK, the transistor N2 changes from the on state to the off state, and then the transistor P2 changes from the on state to the off state. Accordingly, as shown in FIG. 13E, the hold switch SWbj + 1 is turned off. Next, the transistor P1 changes from the off state to the on state, and the transistor N1
1 changes from the off state to the on state. At this time, the write switch SWaj + 1 is turned on as shown in FIG. Then, the input signal INj + 1 is output as the output signal OUTj + 1 via the NOR circuit 12 and the inverter 11.

Thereafter, these operations are repeated, and data transfer unit circuits Uaj + 2, Uaj + 3,.
The transfer pulses are sequentially transferred to an. It is important to detect that the next-stage write switch is in the OFF state and to change the write switch or hold switch in the ON state of the next stage to the OFF state in order to prevent the transfer pulse from penetrating. It is. The write switch and the hold switch operate with toggle, but according to the above-described operation, there is a period in which both switches are turned off at the same time during the state transition (for example, FIGS. 13B and 13E).
). In other words, both switches do not turn on simultaneously during the transition of the switch state. If there is a period in which the write switch and the hold switch are simultaneously turned on, the write switches SWaj and SWaj + 1 and the hold switches SWbj and SWbj + 1 are turned on in FIG. The transfer pulse to be transferred from Uaj to the data transfer unit circuit Uaj + 1 is transferred to the data transfer unit circuit Uaj + 2. According to the present embodiment, since the period in which both switches are simultaneously turned off during the switch state transition is provided, the transfer pulse can be prevented from penetrating and the transfer can be executed reliably.

FIG. 14 shows a timing chart of the overall operation of the bidirectional shift register 1. As shown in this figure, when the start pulse SP that is active at the L level is input to the bidirectional shift register 1, the shift signals Q1 to Qn are sequentially output in synchronization with the forward clock signal CK and the inverted clock signal CKB. Is done. If the transfer direction is right, start pulse SP
Is supplied to the leftmost data transfer unit circuit Ua1, so that the shift signal is Q1 → Q2 →.
, → Qn in this order. Since each of the shift signals Q1 to Qn is an output signal of the NOR circuit 12, it becomes active at the H level. In this case, the shift signal at a certain stage and the shift signal at the next stage overlap for a period of ½ cycle of the normal clock signal CK. When the transfer direction is the left direction, the start pulse SP is supplied to the data transfer unit circuit Ua1 at the right end.
The shift signal becomes active in the order of Qn → Qn−1 →,... → Q1.

Here, the phase relationship (phase difference) between the shift signals Q1 to Qn and the forward clock signal CK or the inverted clock signal CKB is constant regardless of whether the transfer direction is left or right. For example,
As shown in FIG. 14, the rising edge Eu of the shift signal Q2 is synchronized with the rising edge of the normal clock signal CK regardless of the transfer direction. Therefore, the phase relationship does not shift by a half cycle of the normal clock signal CK or the inverted clock signal CKB according to the transfer direction.

<2. Electro-optical device>
Next, an electro-optical device using the above-described bidirectional shift register 1 as a drive circuit will be described.
FIG. 15 is a block diagram showing an electrical configuration of the electro-optical device 500 according to the present invention. The electro-optical device 500 uses liquid crystal as an electro-optical material. The electro-optical device 500 includes a liquid crystal panel AA as a main part. The liquid crystal panel AA is bonded to an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element and a counter substrate with the electrode formation surfaces facing each other and maintaining a certain gap. However, liquid crystal is sandwiched between the gaps.

The electro-optical device 500 includes a liquid crystal panel AA, a timing generation circuit 300, and an image processing circuit 400. The liquid crystal panel AA includes an image display area A, a scanning line driving circuit 100, a data line driving circuit 200, a sampling circuit 240, and an image signal supply line L on the element substrate. The input image data D supplied to the electro-optical device 500 has, for example, a 3-bit parallel format. The timing generation circuit 300 generates a Y clock signal YCK, an X clock signal XCK, a Y transfer start pulse DY, an X transfer start pulse DX, and a transfer direction control signal DIR in synchronization with the input image data D to drive a scanning line. This is supplied to the circuit 100 and the data line driving circuit 200. The timing generation circuit 300 generates various timing signals for controlling the image processing circuit 400 and outputs them. Y clock signal YCK
And the X clock signal XCK correspond to the normal rotation clock signal CK described above, and the Y transfer start pulse DY and the X transfer start pulse DX correspond to the start pulse SP described above.

Here, the Y clock signal YCK specifies a period for selecting the scanning line 2, and the X clock signal XCK specifies a period for selecting the data line 3. The Y transfer start pulse DY is a pulse for instructing the start of selection of the scanning line 2, while the X transfer start pulse DX is a pulse for instructing the start of selection of the data line 3. Further, the transfer direction control signal DIR is a signal for instructing the selection order of the scanning lines 2 and the data lines 3. When the logic level is H level, the transfer direction control signal DIR instructs to select each scanning line 2 sequentially from top to bottom and to select each data line 3 from left to right. In the following description, the display mode in this case is referred to as normal image display. On the other hand, when the logical level of the transfer direction control signal DIR is L level, the transfer direction control signal D
The IR instructs to select each scanning line 2 sequentially from the bottom to the top and select each data line 3 from the right to the left. In the following description, the display mode in this case is referred to as reverse image display. In this example, the common transfer direction control signal DIR is supplied to the scanning line driving circuit 100 and the data line driving circuit 200. However, in the timing generation circuit 300, the scanning line selection signal and the data line are Of course, the selection signals may be individually generated and supplied to the scanning line driving circuit 100 and the data line driving circuit 200.

Next, the image processing circuit 400 subjects the input image data D to gamma correction and the like in consideration of the light transmission characteristics of the liquid crystal panel, and then D / A converts the image data of each RGB color to obtain the image signal VID.
Is supplied to the liquid crystal panel AA.
Next, in the image display area A, as shown in FIG. 15, m (m is a natural number of 2 or more) scanning lines 2 are formed in parallel along the X direction, while n (N is a natural number of 2 or more)
Two data lines 3 are formed in parallel along the Y direction. In the vicinity of the intersection of the scanning line 2 and the data line 3, the gate of the TFT 50 is connected to the scanning line 2,
The source of the TFT 50 is connected to the data line 3 and the drain of the TFT 50 is connected to the pixel electrode 6. Each pixel has a pixel electrode 6 and a counter electrode (on the counter substrate).
And a liquid crystal sandwiched between these electrodes. As a result, the pixels are arranged in a matrix corresponding to each intersection of the scanning line 2 and the data line 3.

Further, each scanning line 2 to which the gate of the TFT 50 is connected has scanning signals Y1, Y2,.
m is applied in a pulse-sequential line-sequential manner. Therefore, when a scanning signal is supplied to a certain scanning line 2, the TFT 50 connected to the scanning line is turned on, so that the image signals X1, X2,..., Xn supplied from the data line 3 at a predetermined timing are After being written in order to the corresponding pixels, they are held for a predetermined period.

Since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, the amount of light passing through the liquid crystal is limited as the applied voltage increases in the normally white mode, whereas the amount of light that passes through the liquid crystal is reduced as the applied voltage increases in the normally black mode. In the entire 500, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display becomes possible. In order to prevent the stored image signal from leaking, the storage capacitor 51
It is added in parallel with a liquid crystal capacitor formed between the pixel electrode 6 and the counter electrode. For example, since the voltage of the pixel electrode 6 is held by the storage capacitor 51 for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, and as a result, a high contrast ratio is realized. Become.

Next, the data line driving circuit 200 generates sampling signals SR1 to SRn that are sequentially activated in synchronization with the X clock signal XCK. Further, the data line driving circuit 200 can control the order in which the sampling signals SR1 to SRn are activated by the transfer direction control signal DIR. Specifically, when the transfer direction control signal DIR is at the H level, the sampling signal becomes active in the order of SR1 → SR2 →... SRn, and when the transfer direction control signal DIR is at the L level, the sampling signal is SRn → SRn−. 1 → SR1
It becomes active in the order.

The sampling circuit 240 includes n switches SW1 to SWn. Each switch SW
1 to SWn are constituted by TFTs. When the sampling signals SR1 to SRn supplied to the gate are sequentially activated, the switches SW1 to SWn are sequentially turned on. Then, the image signal VID supplied via the image signal supply line L is sampled and sequentially supplied to each data line 3. Therefore, if the sampling signal becomes active in the order of SR1 → SR2 →... SRn, the data line 3 is sequentially selected from the left to the right, while if the sampling signal becomes active in the order of SRn → SRn−1 →. The data line 3 is selected sequentially from right to left. Of course, the sampling circuit 240 may be included in the data line driving circuit 200.

Next, FIG. 16 is a block diagram showing a detailed configuration of the data line driving circuit 200. As shown in the figure, the data line driving circuit 200 includes a bidirectional shift register 1 and n NAND circuits 21.
0 and an inverter 220. However, the bidirectional shift register 1 is composed of n + 1 stages. The NAND circuit 210 calculates the negation of the logical product of adjacent shift signals, and outputs the inverter 2
20 calculates the negative again and outputs scanning signals Y1, Y2,..., Yn.
Next, FIG. 17 is a block diagram showing a detailed configuration of the scanning line driving circuit 100. As shown in the figure, the scanning line driving circuit 100 includes a bidirectional shift register 1, m NAND circuits 110, and an inverter 120. However, the bidirectional shift register 1 is composed of m + 1 stages.
The NAND circuit 110 calculates the negation of the logical product of adjacent shift signals, and the inverter 120
Calculates a negative negation and outputs sampling signals SR1, SR2,..., SRm.

Next, the display operation of the electro-optical device 500 described above will be described. First, a normal image display operation when the vertical scanning direction is the downward direction and the horizontal scanning direction is the right direction will be described. In this case, since the transfer direction control signal DIR becomes H level, the transfer gate TG1 shown in FIG. 1 is turned on, and the transfer gate TG2 is turned off. As a result, the Y transfer start pulse DY that defines the beginning of the vertical scanning period is supplied to the upper end of the one-stage data transfer unit circuit from the top. Therefore, as shown in FIG. 18, the scanning signal Y1,
Y2,..., Ym are output in order.

Specifically, in FIG. 17, the shift signals Q1, Q2,..., Qm + 1 output from the first, second, third,. D
A signal obtained by capturing Y at the falling edge of the Y clock signal YCK is sequentially shifted by half a cycle. Further, the NAND circuit 110 and the inverter 120 corresponding to each row are used to shift the shift signals output from adjacent stages. Overlapping portions are taken out and output as scanning signals Y1, Y2, Y3,.

Here, when the scanning signal Y1 becomes H level, the T connected to the scanning line 2 in the first row is T.
All FT50s are turned on. On the other hand, during the period in which the scanning signal Y1 is at the H level, the image signal VID corresponding to each pixel is sequentially transmitted through the image signal supply line L1 in synchronization with the supply of the sampling signals SR1, SR2,. Supplied. Here, when the sampling signal SR1 becomes H level, the sampling switch SW1 in the first column is turned on, so that the image signal VID is sampled on the data line 3 in the first column. The image signal VID sampled on the data line 3 in the first column is applied to the pixel electrode 6 in the first row and the first column via the TFT 50 which is turned on, and is written in the liquid crystal capacitance.

Next, when the sampling signal SR2 becomes H level, the sampling switch S in the second column
Since W2 is turned on, the image signal VID is sampled on the data line 3 in the second column and written to the liquid crystal capacitor in the first row and the second column via the TFT 50 which is turned on. Similarly, the image signal VID is sampled and written to the liquid crystal capacity of 1 row and n columns. Thus, the writing of the liquid crystal capacitance from the first column to the nth column in the first row is completed.
Thereafter, when the scanning signals Y2, Y3,..., Ym sequentially become H level, the second row, the third row,.
In the m-th row, writing of the liquid crystal capacitance from the first column to the n-th column is executed in the same manner as in the first row. Thus, a normal image is formed in which the vertical scanning direction is the downward direction and the horizontal scanning direction is the right direction.

Next, a reverse image display operation when the vertical scanning direction is the upward direction and the horizontal scanning direction is the left direction will be described. In this case, since the transfer direction control signal DIR is at the L level, the transfer gate TG1 shown in FIG. 1 is turned off and the transfer gate TG2 is turned on. As a result, the Y transfer start pulse DY is supplied from the top to the lower end of the m + 1 stage data transfer unit circuit. Therefore, as shown in FIG. 19, the scanning signals Ym, Ym−1,
Ym-2,..., Y1 are output in order. Here, when the scanning signal Ym becomes the H level, all the TFTs 50 whose gates are connected to the m-th scanning line 2 are turned on. On the other hand, during the period when the scanning signal Ym is at the H level, the image signal VID is the sampling signals SRn, SRn.
-1,..., SR1 are sequentially supplied via the image signal supply line L in synchronization with the supply of SR1. Here, when the sampling signal SRn becomes H level, the sampling switch SWn in the n-th column is turned on, so that the image signal VID corresponding to the pixel in the m-th row and the n-th column is sampled on the data line 3 in the n-th column. Then, the image signal VID sampled on the data line 3 in the n-th column is applied to the pixel electrode 6 in the m-th row and the n-th column via the TFT 50 that is turned on,
It is written in the liquid crystal capacitor.

Next, when the sampling signal SRn-1 becomes H level, the sampling switch SWn-1 in the (n-1) th column is turned on, so that the image signal VID is sampled on the data line 3 in the (n-1) th column. Then, the data is written into the liquid crystal capacitor of m rows (n−1) columns through the TFT 50 which is turned on. Similarly, the image signal VID is sampled and written to the liquid crystal capacity of m rows and 1 column. Thus, the writing of the liquid crystal capacitance from the nth column to the first column in the mth row is completed. Thereafter, the scanning signals Ym-1, Ym-2,.
When the level is reached, the (m-1) th row, the (m-1) th row,..., The liquid crystal capacitance writing from the nth column to the first column is written in the same manner as the mth row. As a result, a reverse image of one frame is formed.

As described above, according to the above-described electro-optical device 500, normal image display and reverse image display are possible. Note that the above-described electro-optical device 500 is a liquid crystal display device using liquid crystal as an electro-optical material, and this liquid crystal display device can be applied to any of a transmissive type, a reflective type, and a transflective type. Also,
The present invention can also be applied to a passive matrix system that uses only an active matrix system. Furthermore, the electro-optical device can be applied to various devices such as an organic EL device, a fluorescent display tube, a plasma display panel, and a digital mirror device.

<3. Electronic equipment>
Next, some electronic apparatuses using the electro-optical device according to the above-described embodiment will be described.
FIG. 20 shows a configuration of a mobile personal computer to which the electro-optical device 500 is applied. The personal computer 1000 includes an electro-optical device 500 as a display unit.
And a main body 1010. The main body 1010 is provided with a power switch 1001 and a keyboard 1002. In this case, the liquid crystal panel AA of the electro-optical device 500 is particularly
There is no need to perform reverse image display. However, the electro-optical device 500 can be used in combination with other types of devices that require reverse image display. That is, the electro-optical device 500 capable of normal image display and reverse image display has improved versatility, and can reduce the cost of a device in which it is incorporated.

FIG. 21 shows a configuration of a projector using the electro-optical device 500. As shown in this figure, a projector 2000 is provided with a lamp unit 2002 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2002 is
Light valves 100R and 100G corresponding to each primary color are separated into three primary colors R (red), G (green), and B (blue) by three mirrors 2006 and two dichroic mirrors 2008 arranged inside. And 100B, respectively. Here, the light valve 100
R, 100G, and 100B are basically the same as the electro-optical device 500 according to the above-described embodiment, that is, the transmissive liquid crystal display device. That is, the light valves 100R, 100G, 1
00B functions as an optical modulator that generates RGB primary color images.
Further, since the light path of B light is longer than that of other R and G lights, in order to prevent loss thereof, light is guided through a relay lens system 2021 including an incident lens 2022, a relay lens 2023, and an exit lens 2024. It is burned. The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2012 from three directions. In the dichroic prism 2012, R and B light is refracted at 90 degrees, while G light goes straight. As a result, a color image obtained by combining the primary color images is projected onto the screen 2020 via the projection lens 2014. Here, when the projector 2000 mounted on the desk is used with its bottom surface facing the ceiling surface, it is necessary to invert the top / bottom / left / right of the modulation image by the light valve as compared to when using it on the desk. However, in the present embodiment, as described above, when the vertical scanning direction by the scanning line driving circuit 100 is set as the upward direction and the horizontal scanning direction by the data line driving circuit 500 is set as the left direction, a reverse image is formed.

FIG. 22 shows a configuration of a video camera using the electro-optical device 500. As shown in this figure, the main body 3010 of the video camera 3000 is provided with an optical system 3012 in addition to the electro-optical device 500 used as the monitor 510. Here, the electro-optical device 500 is rotatably attached to a hinge 3016 about a shaft 3024, and the hinge 3016 is configured to open and close with respect to the main body 3010 about the shaft 3022. Yes.
For this reason, the electro-optical device 500 needs to have a relationship in which the upper, lower, left, and right sides of the display image are reversed between the mode illustrated in the figure and the mode used by the photographer in the viewfinder. Here, in this embodiment, as described above, the vertical scanning direction by the scanning line driving circuit 100,
If the horizontal scanning directions of the data line driving circuit 200 are opposite to each other, the display image can be reversed vertically and horizontally. In addition, as an electronic device, FIGS.
The present invention is not limited to the example described with reference to the above, and can be applied to all devices that need to flip the image vertically and horizontally according to various situations.

1 is a block diagram showing a configuration of a bidirectional shift register 1 according to the present invention. 3 is a circuit diagram showing a configuration of a data transfer circuit Uaj used in the bidirectional shift register 1. FIG. (A) is an equivalent circuit diagram of the data transfer unit circuits Uaj and Uaj + 1 when the transfer direction control signal DIR is at the H level, and (B) is a data transfer unit when the transfer direction control signal DIR is at the L level. It is an equivalent circuit diagram of the circuits Uaj and Uaj + 1. 3 is a circuit diagram showing a configuration of a clock control circuit Ubj used in the bidirectional shift register 1. FIG. (A) is a circuit diagram of the first enable signal generation circuit 31 used for the clock control circuit Ubj, and (B) is a circuit diagram of the second enable signal generation circuit 34 used for the clock control circuit Ubj. 3 is a circuit diagram showing a configuration example of a clock input circuit 30. FIG. It is a circuit diagram of an inverter. (A) is a circuit diagram of a NAND circuit, and (B) is a circuit diagram of a NOR circuit. It is a graph which shows the threshold potential of an inverter, a NAND circuit, and a NOR circuit. 6 is a timing chart of first to fourth clock signals when the logic level of the clock signal CLK transits from an H level to an L level. 6 is a timing chart of first to fourth clock signals when the logic level of the clock signal CLK changes from L level to H level. 6 is a timing chart for explaining a transfer operation of data transfer unit circuits Uaj and Uaj + 1. It is an equivalent circuit diagram of the data transfer unit circuits Uaj and Uaj + 1 during the transfer operation. 3 is a timing chart showing the overall operation of the bidirectional shift register 1. 1 is a block diagram showing a configuration of an electro-optical device 500 according to the present invention. 2 is a circuit diagram of a data line driving circuit 200 used in the same device. FIG. 2 is a circuit diagram of a scanning line driving circuit 100 used in the apparatus. FIG. It is a timing chart for demonstrating operation | movement of the apparatus in normal image display. It is a timing chart for demonstrating operation | movement of the apparatus in a reverse image display. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the same apparatus is applied. It is a block diagram of the projector which is an example of the electronic device to which the apparatus is applied. It is a block diagram of the video camera which is an example of the electronic device to which the same apparatus is applied. It is a circuit diagram of the conventional waveform shaping circuit. It is a circuit diagram which shows the structural example of the switching circuit of a normal rotation clock signal and an inversion clock signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Bidirectional shift register, 2 ... Scan line, 3 ... Data line, CK1j ... 1st clock signal (forward rotation control clock signal, 1st forward rotation control clock signal), CK2j ... 2nd clock signal (
Inversion control clock signal, first inversion control clock signal), CK3j... Third clock signal (normal rotation control clock signal, second normal rotation control clock signal), CK4j... Fourth clock signal (inversion control clock signal, second inversion) Control clock signal), Ua1 to Uan ... data transfer unit circuit (transfer unit circuit), Ub1 to Ubn ... clock control circuit, DIR ... transfer direction control signal, C
K: forward rotation clock signal (forward rotation input clock signal), CKB: inverted clock signal (inverted input clock signal), EN1: first enable signal, EN2: second enable signal, 31: first enable signal generation circuit, 34 2nd enable signal generating circuit 20 Clock supply circuit (clock supply circuit) SWaj Write switch (first switch means) SWbj Hold switch (second switch means) S1 First terminal S2 Second Terminal, S3... First connection point, S4... Second connection point, 10, 11... Clocked inverter (first and second clocked inverters), P1, N1, N2, P2. ),
DESCRIPTION OF SYMBOLS 100 ... Scanning line drive circuit, 200 ... Data line drive circuit, 500 ... Electro-optical apparatus.

Claims (7)

A plurality of transfer unit circuits for sequentially shifting pulses based on a normal rotation control clock signal and an inversion control clock signal, and a normal rotation control clock signal and an inversion control clock provided corresponding to each of the plurality of transfer unit circuits. In a bidirectional shift register comprising a plurality of clock control circuits for supplying a signal to the transfer unit circuit and capable of transferring the pulse bidirectionally according to a transfer direction control signal that indicates a transfer direction of the pulse,
In each of the plurality of clock control circuits, a normal input clock signal and an inverted input clock signal obtained by inverting the normal input clock signal are alternately supplied as a supply clock signal,
A first enable signal generation circuit that detects that a first condition is satisfied and generates a first enable signal of negative logic that permits input of the supply clock signal;
A second enable signal generation circuit that detects that a second condition is satisfied and generates a positive logic second enable signal that permits input of the supply clock signal;
A NOR circuit to which the supply clock signal and the first enable signal are input;
A NAND circuit to which the supply clock signal and the second enable signal are input;
A selection circuit that selects one of the output signal of the NOR circuit and the output signal of the NAND circuit based on the transfer direction control signal and outputs it as a clock signal;
A clock supply circuit that generates the normal control clock signal whose logic level matches the clock signal and the inverted control clock signal whose logic level is inverted from the clock signal and supplies the clock signal to the transfer unit circuit;
A bidirectional shift register characterized by the above. The transfer unit circuit includes first switch means provided between a first terminal and a first connection point;
Second switch means provided between the first connection point and the second terminal; third switch means provided between the second connection point and the first terminal; and the second connection point; A fourth switch means provided between the second terminal and the second terminal;
The first switch means includes a P-channel first transistor whose on / off is controlled based on the inverted control clock signal and an N-channel type whose on / off is controlled based on the normal control clock signal. A second transistor, the first transistor and the second transistor
When at least one of the transistors is turned on, the logic level of the second connection point is set according to the logic level of the first terminal,
The second switch means includes an N-channel third transistor whose on / off is controlled based on the normal control clock signal and a P-channel type whose on / off is controlled based on the inverted control clock signal. A fourth transistor, the third transistor and the fourth transistor
When at least one of the transistors is turned on, the logic level of the second connection point is set according to the logic level of the second terminal;
The third switch means is configured such that when the transfer direction control signal is at one logic level, the second switch means
Supplying an output signal corresponding to the state of the connection point to the first terminal;
The fourth switch means includes the second switch means when the transfer direction control signal is at the other logic level.
The bidirectional shift register according to claim 1, wherein an output signal corresponding to a state of a connection point is supplied to the second terminal. The first transistor is supplied with a first inversion control clock signal as the inversion control clock signal, the second transistor is supplied with a first normal control clock signal as the normal control clock signal, and the third transistor The second normal control clock signal is supplied as the normal control clock signal, the second transistor is supplied with the second inverted control clock signal as the inverted control clock signal,
The clock supply circuit includes:
A NAND circuit for supplying the clock signal to one input terminal and outputting the first normal rotation control clock signal;
A first inverting circuit for inverting the first normal control clock signal and outputting the first inverted control clock signal;
A NOR circuit for supplying the clock signal to one input terminal, supplying the first inversion control clock signal to the other input terminal, and outputting the second normal control clock signal;
Inverting the second normal clock control signal to generate the second inverted control clock signal;
A second inverting circuit for supplying to the other input terminal of the NAND circuit,
The bidirectional shift register according to claim 2. The first enable signal generation circuit is activated when a pulse input to the transfer unit circuit of the own stage or a pulse output from the transfer unit circuit of the own stage is active, or when the transfer direction is one direction. The first condition is at least one of the first switch means of the transfer unit circuit being a stage being in an OFF state,
The second enable signal generation circuit is active when a shift pulse input to the transfer unit circuit of the own stage or a shift pulse output from the transfer unit circuit of the own stage is active, or the transfer direction is the other direction. The second condition is that at least one of the second switch means of the transfer unit circuit in the next stage is in an OFF state,
The bidirectional shift register according to any one of claims 1 to 3, wherein the bidirectional shift register is provided. An electro-optical device comprising a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines,
A scanning line driving circuit for driving the plurality of scanning lines;
A data line driving circuit for driving the plurality of data lines,
The scanning line driving circuit includes:
A bidirectional shift register according to any one of claims 1 to 4, comprising:
Generating a plurality of scanning signals so as to be active during a period in which the shift signals output from the adjacent transfer unit circuits are simultaneously active, and supplying the plurality of scanning signals to the plurality of scanning lines, respectively.
An electro-optical device. An electro-optical device comprising a plurality of scanning lines, a plurality of data lines, and an electro-optical element provided corresponding to the intersection of the scanning lines and the data lines,
A scanning line driving circuit for driving the plurality of scanning lines;
A data line driving circuit for driving the plurality of data lines,
The data line driving circuit includes:
5. A sampling shift signal comprising the bidirectional shift register according to claim 1, wherein the plurality of sampling signals are activated during a period in which the shift signals output from the adjacent transfer unit circuits are simultaneously activated. And supplying a plurality of data signals obtained by sampling an image signal according to each of the plurality of sampling signals to the plurality of data lines, respectively.
An electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 6.

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