JP2006215575A - Liquid crystal display device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which can realize a large screen, high definition, high resolution and multi-level gradation. <P>SOLUTION: The liquid crystal display device wherein image display is performed by line-sequentially driving a plurality of pixels having thin film transistors has a source electrode and a drain electrode provided at an upper part of each thin film transistor, an organic resin film provided at an upper part of the source and drain electrodes, a pixel electrode provided at an upper part of the organic resin film, a counter electrode provided opposite to the pixel electrode and a liquid crystal layer provided between the pixel electrode and the counter electrode. Before analog gradation voltage is written in the plurality of pixels, voltage higher than the analog gradation voltage is applied to the liquid crystal layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device. In particular, the present invention relates to a liquid crystal display device that performs gradation display using both voltage gradation and time gradation.

  Recently, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT) has been rapidly developed. The reason is that the demand for active matrix liquid crystal display devices has increased.

  In an active matrix liquid crystal display device, pixel TFTs are arranged in dozens to millions of pixel regions arranged in a matrix, and the charge that enters and exits the pixel electrode connected to each pixel TFT is switched by the pixel TFT. It is controlled by function.

  In recent years, there has been a demand for multi-gradation display capable of full color display as well as higher definition and higher resolution of images.

  Among active matrix liquid crystal display devices, digital drive type active matrix liquid crystal display devices capable of high-speed driving have been attracting attention as display devices have higher definition and higher resolution.

  A digital drive type active matrix liquid crystal display device requires a D / A conversion circuit (DAC) for converting digital video data input from the outside into analog data (gradation voltage). There are various types of D / A conversion circuits.

The multi-gradation display capability of a digital drive type active matrix liquid crystal display device is the capability of this D / A conversion circuit, that is, how many bits of digital video data can be converted into analog data by the D / A conversion circuit. Depends on. For example, in general, a liquid crystal display device having a D / A conversion circuit for processing 2-bit digital video data can perform 2 ² = 4 gradation display, and if 8 bits, 2 ⁸ = 256. Gradation display can be performed, and 2 ⁿ gradation display can be performed with n bits.

  However, in order to increase the capability of the D / A conversion circuit, the circuit configuration of the D / A conversion circuit becomes complicated and the layout area increases. Recently, a liquid crystal display device in which a D / A conversion circuit is formed of polysilicon TFTs on the same substrate as an active matrix circuit has been reported. However, in this case, when the circuit configuration of the D / A conversion circuit becomes complicated, the yield of the D / A conversion circuit decreases, and the yield of the liquid crystal display device also decreases. Further, when the layout area of the D / A conversion circuit is increased, it is difficult to realize a small liquid crystal display device.

  In addition, as the active matrix liquid crystal display device has a larger screen, higher definition, and higher resolution, the time for writing image data to one pixel has been shortened, and the TN mode (twist using twisted nematic liquid crystal), which has been commonly used, has been shortened. In the nematic mode), the response speed of liquid crystal molecules has become a problem.

  As described above, realization of an active matrix liquid crystal display device capable of realizing a large screen, high definition, high resolution, and multi-gradation is desired.

  Accordingly, the present invention has been made in view of the above-described problems, and provides a liquid crystal display device capable of realizing a large screen, high definition, high resolution, and multiple gradations.

  First, refer to FIG. FIG. 1 is a schematic configuration diagram of a liquid crystal display device of the present invention. Reference numeral 101 denotes a liquid crystal panel having a digital driver. The liquid crystal panel 101 includes an active matrix substrate 101-1 and a counter substrate 101-2. On the active matrix substrate 101-1, an active matrix circuit 101-1-4 in which source drivers 101-1-1, gate drivers 101-1-2 and 101-1-3, and a plurality of pixel TFTs are arranged in a matrix. have. The source driver 101-1-1, gate driver 101-1-2, and 101-1-3 drive the active matrix circuit 101-1-4. Further, the counter substrate 101-2 has a counter electrode 101-2-1. A terminal COM indicates a terminal that supplies a signal to the counter electrode.

  Reference numeral 102 denotes a digital video data time gradation processing circuit. The digital video data time gradation processing circuit 102 converts n-bit digital video data out of m-bit digital video data input from the outside into digital video data for n-bit voltage gradation. Of the m-bit digital video data, (mn) bit gradation information is expressed by time gradation.

  The n-bit digital video data converted by the digital video data time gradation processing circuit 102 is input to the liquid crystal panel 101. The n-bit digital video data input to the liquid crystal panel 101 is input to the source driver 101-1-1, converted into analog gradation data by a D / A conversion circuit in the source driver, and supplied to each source signal line. , Supplied to the pixel TFT.

  A counter electrode drive circuit 103 supplies a counter electrode control signal for controlling the potential of the counter electrode to the counter electrode 101-2-1 of the liquid crystal panel 101.

  In the present specification, a liquid crystal display device and a liquid crystal panel are selectively used. In this specification, one having at least an active matrix circuit is referred to as a liquid crystal panel.

  Here, FIG. 2 and FIG. 3 which explain the schematic block diagram of the liquid crystal panel of the liquid crystal display device of this invention are referred. 2 and 3 show an active matrix substrate 101-1, a counter substrate, and a liquid crystal 101-3 constituting the liquid crystal panel 101. FIG. The liquid crystal panel used in the present invention has a so-called π cell structure, and uses a display mode called an OCB (Optically Compensated Bend) mode. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to a bend alignment as shown in FIG. 2 when a voltage is applied. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to the substrates and light is transmitted.

  As shown in FIG. 2, the liquid crystal display device of the present invention includes a liquid crystal panel in which liquid crystals are bend-oriented, a biaxial retardation plate 111, and a pair of polarizing plates whose transmission axes are perpendicular to each other. In the display in the OCB mode, the viewing angle dependency of retardation is compensated three-dimensionally by a biaxial retardation plate.

  As described above, when no voltage is applied to the liquid crystal, the splay alignment shown in FIG. 3 is performed.

  According to the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be achieved.

  Next, another example of the liquid crystal display device of the present invention is shown in FIG. Reference numeral 301 denotes a liquid crystal panel having an analog driver. The liquid crystal display device 301 includes an active matrix substrate 301-1 and a counter substrate 301-2. An active matrix circuit 301-1-4 includes a source driver 301-1-1, gate drivers 301-1-2 and 301-1-3, and a plurality of pixel TFTs arranged in a matrix on the active matrix substrate 301-1. have. The source driver 301-1-1, the gate driver 301-1-2, and 301-1-3 drive the active matrix circuit 301-1-4. Further, the counter substrate 301-2 includes a counter electrode 301-2-1. A terminal COM indicates a terminal that supplies a signal to the counter electrode.

  An A / D conversion circuit 302 converts analog video data supplied from the outside into m-bit digital video data. Reference numeral 303 denotes a digital video data time gradation processing circuit. The digital video data time gradation processing circuit 303 converts n-bit digital video data of input m-bit digital video data into digital video data for n-bit voltage gradation. Of the input m-bit digital video data, (mn) -bit gradation information is expressed by time gradation. The n-bit digital video data converted by the digital video data time gradation processing circuit 303 is input to the D / A conversion circuit 304 and converted into analog video data. The analog video data converted by the D / A conversion circuit 304 is input to the liquid crystal display device 301. The analog video data input to the liquid crystal display device 301 is input to the source driver, sampled by a sampling circuit in the source driver, supplied to each source signal line, and supplied to the pixel TFT.

  A counter electrode driving circuit 305 supplies a counter electrode control signal for controlling the potential of the counter electrode to the counter electrode 301-2-1 of the liquid crystal panel 301.

  The operation of the liquid crystal display device of the present invention will be described in detail in the following embodiments.

  The configuration of the present invention will be described below.

  According to the liquid crystal display device of the present invention, an active matrix circuit having a plurality of pixel TFTs arranged in a matrix, an active matrix substrate having a source driver and a gate driver for driving the active matrix circuit, a counter substrate having a counter electrode, In the liquid crystal display device, the display is performed in the OCB mode, and among the m-bit digital video data input from the outside, n bits are used as voltage gradation information and (mn) bits are used as time scales. By using (m and n are positive numbers greater than or equal to 2 and m> n) as tone information, a liquid crystal display device is provided that performs voltage gradation and time gradation simultaneously.

  Further, according to the liquid crystal display device of the present invention, an active matrix circuit having a plurality of pixel TFTs arranged in a matrix, an active matrix substrate having a source driver and a gate driver for driving the active matrix circuit, and a counter electrode having a counter electrode A liquid crystal display device having a substrate, wherein the display is performed in an OCB mode, and n bits of m-bit digital video data inputted from the outside are used as voltage gradation information and (mn) bits are used. By using time gradation information (m and n are both positive numbers of 2 or more and m> n), the voltage gradation and the time gradation are performed before, after, or before and after, respectively. A liquid crystal display device is provided.

In addition, according to the liquid crystal display device of the present invention, the active matrix circuit having a plurality of pixel TFTs arranged in a matrix, the active matrix substrate having the source driver and gate driver for driving the active matrix circuit, and the counter electrode A counter substrate, a circuit for converting m-bit digital video data inputted from the outside into n-bit digital video data and supplying the n-bit digital video data to the source driver (m and n are both positive numbers of 2 or more) , M> n), wherein voltage gradation and time gradation are simultaneously performed to display one frame of video by 2 ^mn subframes, and the 2 ^mn At the start of display of each subframe, a voltage is applied to make the liquid crystal molecules bend. The liquid crystal display device which is characterized in that there is provided.

Further, according to the liquid crystal display device of the present invention, an active matrix circuit having a plurality of pixel TFTs arranged in a matrix, an active matrix substrate having a source driver and a gate driver for driving the active matrix circuit, and a counter electrode having a counter electrode A circuit for converting m-bit digital video data inputted from the outside into n-bit digital video data and supplying the n-bit digital video data to the source driver (m and n are both positive numbers of 2 or more, m> n), wherein the voltage gradation and the time gradation are respectively performed before, after, or before and after the liquid crystal molecules at the start of the display of the 2 ^mn subframes. A liquid crystal display device characterized by applying a voltage for changing the orientation of the liquid crystal to bend orientation is provided.

Further, according to the liquid crystal display device of the present invention, an active matrix circuit having a plurality of pixel TFTs arranged in a matrix, an active matrix substrate having a source driver and a gate driver for driving the active matrix circuit, and a counter electrode having a counter electrode A circuit for converting m-bit digital video data inputted from the outside into n-bit digital video data and supplying the n-bit digital video data to the source driver (m and n are both positive numbers of 2 or more, m> n), wherein a voltage gradation and a time gradation are simultaneously performed to display one frame image by 2 ^mn subframes, and the 2 ^mn Bend the orientation of the liquid crystal molecules at the start of the display of the frame composed of The liquid crystal display device is provided, which comprises applying a voltage to the counter.

Further, according to the liquid crystal display device of the present invention, an active matrix circuit having a plurality of pixel TFTs arranged in a matrix, an active matrix substrate having a source driver and a gate driver for driving the active matrix circuit, and a counter electrode having a counter electrode A circuit for converting m-bit digital video data inputted from the outside into n-bit digital video data and supplying the n-bit digital video data to the source driver (m and n are both positive numbers of 2 or more, m> n), wherein a voltage gradation and a time gradation are respectively performed before, after, or in ^succession, and a frame display constituted by the 2 ^mn subframes is displayed. A liquid crystal characterized by applying a voltage for changing the alignment of liquid crystal molecules to bend alignment at the start of Display device is provided.

  The m may be 10 and the n may be 2.

  The m may be 12, and the n may be 4.

  According to the liquid crystal display device of the present invention, a small active matrix liquid crystal display device capable of realizing a large screen, high definition, high resolution, and multiple gradations is realized.

  The liquid crystal display device of the present invention will be described in detail below with reference to embodiments. However, the liquid crystal display device of the present invention is not limited to the following embodiments.

(Embodiment 1)
FIG. 4 shows a schematic configuration diagram of the liquid crystal display device of the present embodiment. In this embodiment, for the sake of simplicity, a liquid crystal display device to which 4-bit digital video data is supplied from the outside is taken as an example.

  FIG. 4 shows a schematic configuration diagram of the liquid crystal display device of the present invention. Reference numeral 401 denotes a liquid crystal panel having a digital driver. The liquid crystal panel 401 includes an active matrix substrate 401-1 and a counter substrate 401-2. An active matrix circuit 401-1-4 in which source drivers 401-1-1, gate drivers 401-1-2 and 401-1-3, and a plurality of pixel TFTs are arranged in a matrix on the active matrix substrate 401-1. have. The source driver 401-1-1, the gate drivers 401-1-2, and 401-1-3 drive the active matrix circuit 401-1-4. The counter substrate 401-2 has a counter electrode 401-2-1. A terminal COM indicates a terminal that supplies a signal to the counter electrode.

  Note that the liquid crystal panel of the present embodiment uses the OCB mode as described above as the display mode.

  Reference numeral 402 denotes a digital video data time gradation processing circuit. The digital video data time gradation processing circuit 402 converts 2-bit digital video data out of 4-bit digital video data input from the outside into 2-bit digital video data for voltage gradation. Of the 4-bit digital video data, the remaining 2-bit gradation information is expressed by time gradation.

  The 2-bit digital video data converted by the digital video data time gradation processing circuit 402 is input to the liquid crystal panel 401. The 2-bit digital video data input to the liquid crystal panel 401 is input to the source driver, converted to analog gradation data by a D / A conversion circuit (not shown) in the source driver, and supplied to each source signal line. The

  A counter electrode driving circuit 403 supplies a counter electrode control signal for controlling the potential of the counter electrode to the counter electrode 401-2-1 of the liquid crystal panel 401.

  Here, a circuit circuit configuration of the liquid crystal panel 401 of the liquid crystal display device of the present embodiment, particularly, an active matrix circuit 401-1-4 will be described with reference to FIG. 5.

  In the present embodiment, the active matrix circuit 401-1-4 has (x × y) pixels. For convenience of explanation, each pixel is given a reference sign such as P1,1, P2,1,..., Py, x. Each pixel has a pixel TFT 501 and a storage capacitor 502. Further, liquid crystal is sandwiched between the active matrix substrate and the counter substrate. A liquid crystal 502 schematically shows a liquid crystal corresponding to each pixel.

  The digital driver liquid crystal panel of the present embodiment performs so-called line-sequential driving in which pixels for one line (for example, P1,1, P1,2,..., P1, x) are simultaneously driven. In other words, the analog gradation voltage is simultaneously written in the pixels for one line. The time required to write the analog gradation voltage to all the pixels (P1,1 to Py, x) will be referred to as one frame period (Tf). In the present embodiment, a period obtained by dividing one frame period (Tf) into four is referred to as a subframe period (Tsf). Further, the time required to write the analog gradation voltage to pixels for one line (for example, P1,1, P1,2,..., P1, x) is referred to as one subframe line period (Tsfl). To do.

  The counter electrode control signal from the counter electrode control circuit is supplied to the counter electrode 401-2-1. A counter electrode control signal is supplied to a terminal COM to which the counter electrode is electrically connected.

  Next, gradation display of the liquid crystal display device of the present embodiment will be described. The digital video data supplied from the outside to the liquid crystal display device of this embodiment is 4 bits and has 16 gradation information. Reference is now made to FIG. FIG. 6 shows display gradation levels of the liquid crystal display device of the present embodiment. The voltage level VL is the lowest voltage level input to the D / A conversion circuit, and the voltage level VH is the highest voltage level input to the D / A conversion circuit.

  In this embodiment, in order to realize a voltage level of 2 bits, that is, 4 gradations, the voltage level VH and the voltage level VL are divided into almost equal voltage levels, and the step of the voltage level is expressed as α. did. Note that α = (VH−VL) / 4. Therefore, the voltage gradation level output from the D / A converter circuit of this embodiment is VL when the address of the digital video data is (00), and VL + α when the address of the digital video data is (01). When the address of the digital video data is (10), it becomes VL + 2α, and when the address of the digital video data is (11), it becomes VL + 3α.

  As described above, there are four voltage gradation levels that can be output by the D / A conversion circuit of the present embodiment: VL, (VL + α), (VL + 2α), and (VL + 3α). Therefore, in the present invention, the number of display gradation levels of the liquid crystal display device can be increased by combining time gradation display.

  In the present embodiment, by using information of 2 bits of 4-bit digital video data for time gradation display, a display gradation corresponding to a voltage gradation level obtained by dividing the voltage level step α into approximately four equal parts. Level can be realized. That is, the liquid crystal display device of the present embodiment has VL, VL + α / 4, VL + 2α / 4, VL + 3α / 4, VL + α, VL + 5α / 4, VL + 6α / 4, VL + 7α / 4, VL + 2α, VL + 9α / 4, VL + 10α / 4, VL + 11α. A display gradation level corresponding to a voltage gradation level of / 4, VL + 3α can be realized.

  Here, correspondences between externally input 4-bit digital video data addresses, digital video data addresses after time gradation processing and voltage gradation levels corresponding thereto, and display gradation levels combining time gradations are as follows. Table 1 shows.

  As shown in Table 1, in this embodiment, the same gradation voltage level (VL + 3α) is output when the addresses of 4-bit digital video data are (1100) to (1111).

Note that the gradation voltage levels shown in Table 1 may be voltages actually applied to the liquid crystal. That is, the gradation voltage level shown in Table 1 may be a voltage level that takes _VCOM applied to a counter electrode described later into consideration.

  The liquid crystal display device of the present invention performs display by dividing one frame period Tf into four subframe periods (1st Tsf, 2nd Tsf, 3rd Tsf, and 4th Tsf). Furthermore, since the liquid crystal display device according to the present embodiment performs line sequential driving, gradation voltage is written in each pixel during one subframe line period (Tsfl) in one frame period. Therefore, after the time grayscale processing, the subframe line periods (1st Tsfl, 2nd Tsfl, 3rd Tsfl, and 4th Tsfl) corresponding to the subframe periods (1st Tsf, 2nd Tsf, 3rd Tsf, and 4th Tsf) An address of 2-bit digital video data is input to the D / A conversion circuit, and a gradation voltage is output from the D / A conversion circuit. Four subframes are displayed at high speed by the grayscale voltage written in the four subframe line periods (1st Tsfl, 2nd Tsfl, 3rd Tsfl, and 4th Tsfl). As a result, the display grayscale of one frame is The sum of the gradation voltage levels in each subframe line period is a time average. In this way, voltage gradation and time gradation are performed simultaneously.

In the liquid crystal display device of this embodiment, an initialization period (Ti) is provided in each subframe period before the subframe line period starts. In this initialization period (Ti), a certain voltage Vi (pixel electrode initialization voltage) is applied to all the pixels, and a voltage V _COMi (counter electrode initialization voltage) applied to the counter electrode is applied to the splay alignment. The liquid crystal is shifted to bend alignment.

Therefore, in the liquid crystal display device according to the present embodiment, even when a D / A conversion circuit that handles 2-bit digital video data is used, it is possible to display a gradation level of 2 ⁴ −3 = 13 gradations.

  Note that the address (or gradation voltage level) of digital video data written in each subframe line period (1st Tsfl, 2nd Tsfl, 3rd Tsfl, and 4th) can also be set by combinations other than those in Table 1. For example, in Table 1, when the digital video data address is (0010), the gradation voltage of (VL + α) is written in the third subframe line period (3rd Tsfl) and the fourth subframe line period (4th Tsfl). However, the present invention is not limited to this combination in order to realize the present invention. That is, when the digital video data address is (0010), the gradation of (VL + α) in a total of two subframe periods among the four subframe periods from the first subframe line period to the fourth subframe line period. It is sufficient that the voltage is written, and it is possible to freely set in which sub-frame period the gradation voltage of (VL + α) is written.

  Reference is now made to FIGS. 7 and 8 show driving timing charts of the liquid crystal display device of the present embodiment. 7 and 8 illustrate the pixel P1,1, pixel P2,1, pixel P3,1 and pixel Py, 1 as an example. For convenience of illustration, the description is made with reference to FIGS. 7 and 8.

As described above, one frame period (Tf) includes a first subframe period (1st Tsf), a second subframe period (2nd Tsf), a third subframe period (3rd Tsf), and a fourth subframe period ( 4th Tsf). At the beginning of each sub-frame period, there is an initialization period (Ti). During this initialization period (Ti), the pixel electrode initialization voltage (Vi) is applied to all pixels. In the initialization period (Ti), the counter electrode initialization voltage (V _COMi ) is applied to the counter electrode (COM).

Therefore, in the present embodiment, during the initialization period (Ti), a voltage of (Vi + V _COMi ) is applied to the liquid crystal sandwiched between the pixel electrode and the counter electrode, and the liquid crystal molecules that have been splay aligned. Is bend-oriented, and a high-speed response is possible by applying an analog gradation voltage having image information thereafter.

In the first subframe period, after the initialization period (Ti) has elapsed, in the pixel P1,1, digital video data is converted into an analog gradation voltage by the D / A converter circuit in the first subframe line period (1st Tsfl). Written. Note that V _COM is applied to the counter electrode after the initialization period (Ti) has elapsed. V _COM can be adjusted by checking the flicker of the display screen. V _COM may be 0V.

It is desirable that Vi, V _COMi , and V _COM are set to optimum values according to the liquid crystal used, display conditions, and the like.

  After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the first subframe period ends.

Then, after the elapse of the first subframe period, the second subframe period starts. Also in the second subframe period (2nd Tsf), the counter electrode initialization voltage (V _COMi ) is supplied to the counter electrode (COM) in the initialization period (Ti). Also in the second sub-frame period, after the initialization period (Ti) has elapsed, the digital video data is converted into analog signals by the D / A converter circuit in the second sub-frame line period (2nd Tsfl) after the initialization period (Ti) has elapsed. Converted to a regulated voltage and written. After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written. Note that V _COM is applied to the counter electrode after the initialization period (Ti) has elapsed.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the second subframe period ends.

  The same operation is performed in the third subframe period (3rd Tsf) and the fourth subframe period (4th Tsf).

  In this way, the period from the first subframe period to the fourth subframe period ends.

  After the end of the first frame period, the second frame period begins (FIG. 8). In the present embodiment, frame inversion is performed in which the direction of the electric field applied to the liquid crystal is reversed every frame period. Therefore, in the second frame period, the pixel electrode initialization voltage (Vi) and the gradation voltage supplied to the pixel electrode are applied with voltages having a polarity opposite to that of the first frame period when the counter electrode is used as a reference potential. Will be.

  Reference is now made to FIG. FIG. 9 is an example showing the relationship between the gradation voltage level written in the pixel electrode of a certain pixel (for example, pixel P1,1) every subframe period and the gradation display level in the frame period.

  First, focus on the first frame period. First, in the initialization period (Ti), the initialization voltage (Vi) is applied to the pixel electrode, and the liquid crystal in the splay alignment shifts to the bend alignment. After the initialization period (Ti), the gradation voltage of (VL + α) is written in the first subframe line period (1st Tsfl), and the gradation voltage (VL + α) is written in the first subframe period (1st Tsf). The gradation display corresponding to is performed. A gradation voltage of (VL + 2α) is written in the second subframe line period (2nd Tsfl), and gradation display corresponding to the gradation voltage (VL + α) is performed in the second subframe period (2nd Tsf). . The gradation voltage of (VL + 2α) is written in the third subframe line period (3rd Tsfl), and gradation display corresponding to the gradation voltage (VL + 2α) is performed in the third subframe period (3rd Tsf). Is called. The gradation voltage of (VL + 2α) is written in the fourth subframe line period (1st Tsfl), and the gradation display corresponding to the gradation voltage (VL + 2α) is performed in the fourth subframe period (4th Tsf). Is called. Therefore, the gradation display level of the first frame is gradation display corresponding to the gradation voltage level of (VL + 7α / 4).

Next, attention is focused on the second frame period. First, in the initialization period (Ti), the initialization voltage (Vi) is applied to the pixel electrode, and the liquid crystal in the splay alignment shifts to the bend alignment. After the initialization period (Ti), the gradation voltage of (VL + 2α) is written in the first subframe line period (1st Tsfl), and the gradation voltage (VL + 2α) is written in the first subframe period (1st Tsf). The gradation display corresponding to is performed. A gradation voltage of (VL + 2α) is written in the second subframe line period (2nd Tsfl), and gradation display corresponding to the gradation voltage (VL + 2α) is performed in the second subframe period (2nd Tsf). . The gradation voltage of (VL + 3α) is written in the third subframe line period (3rd Tsfl), and the gradation display corresponding to the gradation voltage (VL + 3α) is performed in the third subframe period (3rd Tsf). Is called.
The gradation voltage of (VL + 3α) is written in the fourth subframe line period (1st Tsfl), and the gradation display corresponding to the gradation voltage (VL + 3α) is performed in the fourth subframe period (4th Tsf). Is called. Therefore, the gradation display level of the first frame is a gradation display corresponding to the gradation voltage level of (VL + 10α / 4).

  In this embodiment, in order to realize a voltage level of four gradations, the voltage level VH and the voltage level VL are divided into substantially equal voltage levels, and the step of the voltage level is α. Even when the voltage level VH and the voltage level VL are arbitrarily set without being divided into equal voltage levels, the effect of the present invention is obtained.

  In this embodiment, the gradation voltage level can be realized by inputting the voltage level VH and the voltage level VL to the D / A conversion circuit of the liquid crystal panel. A voltage level can also be realized.

  In the present embodiment, the gradation voltage level written in each subframe line period is set as shown in Table 1, but as described above, it is not limited to Table 1.

  In this embodiment, 2-bit digital video data out of 4-bit digital video data input from the outside is converted into digital video data for 2-bit voltage gradation, and 4-bit digital video data is converted. Among them, 2-bit gradation information is expressed by time gradation. Here, in general, m-bit digital video data is converted from external n-bit digital video data into digital video data for a gray-scale voltage by a time gray-scale processing circuit. Consider a case where information is expressed by time gradation. Note that m and n are both integers of 2 or more, and m> n.

In this case, the relationship between the frame period (Tf) and the subframe period (Tsf) is Tf = 2 ^mn · Tsf, and (2 ^m − (2 ^mn −1)) gradation display can be performed.

  In the present embodiment, the case where m = 4 and n = 2 has been described as an example, but it is needless to say that the present invention is not limited to these cases. m = 12 and n = 4 may be sufficient. Moreover, m = 8 and n = 2 may be sufficient. Moreover, m = 8 and n = 6 may be sufficient. Moreover, m = 10 and n = 2 may be sufficient, and the other case may be sufficient.

  Further, the voltage gradation and the time gradation may be performed before, after, or after each other.

(Embodiment 2)
In the present embodiment, a case where frame inversion driving is performed for each subframe in the configuration of the liquid crystal display device of the present invention in Embodiment 1 will be described.

  Please refer to FIG. FIG. 10 shows a drive timing chart of the liquid crystal display device of the present embodiment. FIG. 10 shows a pixel P1,1, pixel P2,1, pixel P3,1 and pixel Py, 1 as an example.

Also in the present embodiment, as described above, one frame period (Tf) includes a first subframe period (1st Tsf), a second subframe period (2nd Tsf), a third subframe period (3rd Tsf), and It is constituted by a fourth subframe period (4th Tsf). At the beginning of each sub-frame period, there is an initialization period (Ti). During this initialization period (Ti), the pixel electrode initialization voltage (Vi) is applied to all pixels. In the initialization period (Ti), the counter electrode initialization voltage (V _COMi ) is applied to the counter electrode (COM).

Therefore, also in the present embodiment, during the initialization period (Ti), a voltage of (Vi + V _COMi ) is applied to the liquid crystal sandwiched between the pixel electrode and the counter electrode, and the liquid crystal molecules that have been splay aligned. Is bend-oriented, and a high-speed response is possible by applying an analog gradation voltage having image information thereafter.

In the first subframe period, after the initialization period (Ti) has elapsed, in the pixel P1,1, digital video data is converted into an analog gradation voltage by the D / A converter circuit in the first subframe line period (1st Tsfl). The analog gradation voltage is written. Note that analog gradation voltages corresponding to the respective pixels are simultaneously written in the pixels P1,1 to P1, x. Note that V _COM is applied to the counter electrode after the initialization period (Ti) has elapsed. V _COM can be adjusted by checking the flicker of the display screen. In this embodiment, V _COM may be 0V.

  After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the first subframe period ends.

Then, after the elapse of the first subframe period, the second subframe period starts. Also in the second subframe period (2nd Tsf), the counter electrode initialization voltage (V _COMi ) is supplied to the counter electrode (COM) in the initialization period (Ti). In the present embodiment, the direction of the electric field applied to the liquid crystal is reversed every subframe period. Also in the second subframe period, after the initialization period (Ti) has elapsed, the digital video data is transferred to the pixels P1,1 to P1, x in the first subframe line period (1st Tsfl) by the D / A conversion circuit. Converted to a regulated voltage and written. After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written. Note that V _COM is applied to the counter electrode after the initialization period (Ti) has elapsed.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the second subframe period ends.

  The same operation is performed in the third subframe period (3rd Tsf) and the fourth subframe period (4th Tsf).

  In this way, the period from the first subframe period to the fourth subframe period ends.

  After the end of the first frame period, the second frame period begins (not shown).

  As described above, in the present embodiment, since display is performed by the subframe inversion method in which the direction of the electric field applied to the liquid crystal is reversed every subframe period, display with less flicker is possible.

(Embodiment 3)
In the present embodiment, in the configuration of the liquid crystal display device of the present invention in the first embodiment, an initialization period is provided only in the first subframe period, an initialization voltage (Vi and V _COM ) is applied, and frame inversion driving is performed. The case where it performs is demonstrated.

  Please refer to FIG. FIG. 11 shows a drive timing chart of the liquid crystal display device of the present embodiment. In FIG. 11, the pixel P1,1, pixel P2,1, pixel P3,1 and pixel Py, 1 are shown as an example.

  Also in the present embodiment, as described above, one frame period (Tf) includes a first subframe period (1st Tsf), a second subframe period (2nd Tsf), a third subframe period (3rd Tsf), and It is constituted by a fourth subframe period (4th Tsf). The first embodiment is different from the first embodiment in that there is an initialization period (Ti) only at the beginning of the first subframe period, and in this initialization period (Ti), the pixel electrode initialization voltage (Vi) is applied to all pixels. Is applied.

In the initialization period (Ti), the counter electrode initialization voltage (V _COMi ) is applied to the counter electrode (COM).

Therefore, also in the present embodiment, during the initialization period (Ti), a voltage of (Vi + V _COMi ) is applied to the liquid crystal sandwiched between the pixel electrode and the counter electrode, and the liquid crystal molecules that have been splay aligned. Is bend-oriented, and a high-speed response is possible by applying an analog gradation voltage having image information thereafter.

In the first subframe period, after the initialization period (Ti) has elapsed, in the pixel P1,1, digital video data is converted into an analog gradation voltage by the D / A converter circuit in the first subframe line period (1st Tsfl). The analog gradation voltage is written. Note that analog gradation voltages corresponding to the respective pixels are simultaneously written in the pixels P1,1 to P1, x. Note that V _COM is applied to the counter electrode after the initialization period (Ti) has elapsed. V _COM can be adjusted by checking the flicker of the display screen. In this embodiment, V _COM may be 0V.

  After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the first subframe period ends.

Then, after the elapse of the first subframe period, the second subframe period starts. In the second subframe period (2nd Tsf), the initialization period (Ti) is not provided. Therefore, the initialization voltages (Vi and V _COM ) are not applied to the pixels at the start of the second subframe period. In the pixels P1,1 to P1, x, digital video data is converted into analog gradation voltages by the D / A conversion circuit and written in the first subframe line period (1st Tsfl). After the digital video data is converted into the analog gradation voltage by the D / A conversion circuit and written in the pixels P1,1 to P1, x, the pixels P2,1 to P2, x are used in the next subframe line period. The digital video data is converted into an analog gradation voltage by a D / A conversion circuit and written.

  In this way, analog gradation voltages having image information are sequentially written in all pixels. Therefore, the second subframe period ends.

  In the third subframe period (3rd Tsf) and the fourth subframe period (4th Tsf), the same operation as in the second subframe period (2nd Tsf) is performed.

  In this way, the period from the first subframe period to the fourth subframe period ends.

  After the end of the first frame period, the second frame period begins (not shown).

(Embodiment 4)
In this embodiment, a liquid crystal display device to which 10-bit digital video data is input will be described. Please refer to FIG. FIG. 12 shows a schematic configuration diagram of the liquid crystal display device of this embodiment. The liquid crystal display device 1001 includes an active matrix substrate 1001-1 and a counter substrate 1001-2. An active matrix circuit 1001-1-4 in which source drivers 1001-1-1 and 1001-1-2, a gate driver 1001-1-3, and a plurality of pixel TFTs are arranged in a matrix on an active matrix substrate 1001-1. , A digital video data time gradation processing circuit 1001-1-5, and a counter electrode driving circuit 1001-1-6. Further, the counter substrate 1001-2 includes a counter electrode 1001-2-1. A terminal COM indicates a terminal that supplies a signal to the counter electrode.

  In the present embodiment, as shown in FIG. 12, the digital video data time gradation processing circuit and the counter electrode driving circuit are integrally formed on the active matrix substrate to form a liquid crystal display device.

  The digital video data time gradation processing circuit 1001-1-5 converts 8-bit digital video data out of 10-bit digital video data input from the outside into digital video data for 8-bit voltage gradation. . Of 10-bit digital video data, 2-bit gradation information is represented by time gradation.

  The 8-bit digital video data converted by the digital video data time gradation processing circuit 1001-5 is input to the source drivers 1001-1-1 and 1001-1-2, and the D / A conversion circuit (see FIG. (Not shown) is converted into an analog gradation voltage and supplied to each source signal line.

  Reference is now made to FIG. FIG. 13 shows the circuit configuration of the liquid crystal display device of this embodiment in more detail. The source driver 1001-1-1 includes a shift register circuit 1001-1-1-1, a latch circuit 1 (1001-1-1-2), a latch circuit 2 (1001-1-1-3), and a D / A conversion. Circuit (1001-1-1-1-4). In addition, a buffer circuit and a level shifter circuit (both not shown) are included. For convenience of explanation, the D / A conversion circuit 1001-1-1-4 includes a level shifter circuit.

  The source driver 1001-1-2 has the same configuration as the source driver 1001-1-1. The source driver 1001-1-1 supplies an image signal (grayscale voltage) to the odd-numbered source signal line, and the source driver 1001-1-2 supplies the image signal to the even-numbered source signal line. It is like that.

  In the active matrix type liquid crystal display device of this embodiment, two source drivers 1001-1-1 and 1001-1-2 are provided so as to sandwich the upper and lower sides of the active matrix circuit for the sake of circuit layout. If possible in the circuit layout, only one source driver may be provided.

  Reference numeral 1001-1-3 denotes a gate driver, which includes a shift register circuit, a buffer circuit, a level shifter circuit, and the like (all not shown).

  The active matrix circuit 1001-1-4 has 1920 × 1080 (horizontal × vertical) pixels. The configuration of each pixel is the same as that described in the first embodiment.

  The liquid crystal display device of this embodiment includes a D / A conversion circuit 1001-1-1-4 that handles 8-bit digital video data. In addition, information of 2 bits among 10-bit digital video data supplied from the outside is used for time gradation. Note that the time gradation can be considered as in the first embodiment.

Therefore, the liquid crystal display device of this embodiment can perform 2 ⁸ −3 = 253 gradation display.

  In addition, as a method for driving the liquid crystal display device according to the present embodiment, any of the above-described first to third embodiments can be used.

(Embodiment 5)
In this embodiment, an example of a method for manufacturing a liquid crystal display device of the present invention will be described. Here, a method for simultaneously manufacturing TFTs of an active matrix circuit and a driver circuit provided in the periphery thereof will be described.

  [Step of Forming Island-shaped Semiconductor Layer and Gate Insulating Film: FIG. 14A] In FIG. 14A, it is preferable to use an alkali-free glass substrate or a quartz substrate as the substrate 7001. In addition, a substrate in which an insulating film is formed on the surface of a silicon substrate or a metal substrate may be used.

  A base film 7002 made of a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film was formed to a thickness of 100 to 400 nm by a plasma CVD method or a sputtering method on the surface of the substrate 7001 on which the TFT was formed. For example, the base film 7002 may be formed to have a two-layer structure in which the silicon nitride film 7002 has a thickness of 25 to 100 nm, here 50 nm, and the silicon oxide film 7003 has a thickness of 50 to 300 nm, here 150 nm. The base film 7002 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used.

  Next, an amorphous silicon film having a thickness of 20 to 100 nm was formed on the base film 7002 by a known film formation method. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atom% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film. Here, since the base film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent surface contamination by preventing exposure to the air atmosphere and to reduce variation in characteristics of the manufactured TFT.

  A known laser crystallization technique or thermal crystallization technique may be used for the step of forming the crystalline silicon film from the amorphous silicon film. Alternatively, a crystalline silicon film may be formed by a thermal crystallization method using a catalyst element that promotes crystallization of silicon. In addition, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly deposited. Further, a crystalline silicon film may be formed using a known technique of SOI (Silicon On Insulators) in which single crystal silicon is bonded onto a substrate.

Unnecessary portions of the crystalline silicon film thus formed were removed by etching to form island-like semiconductor layers 7004 to 7006. In order to control the threshold voltage, boron (B) is added in advance to the region where the n-channel TFT of the crystalline silicon film is formed in order to control the threshold voltage of about 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ^−3. You can keep it.

Next, a gate insulating film 7007 containing silicon oxide or silicon nitride as a main component was formed so as to cover the island-shaped semiconductor layers 7004 to 7006. The gate insulating film 7007 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, a silicon nitride oxide film made of N ₂ O and SiH ₄ as a raw material is formed by plasma CVD to a thickness of 75 nm, and then thermally oxidized at 800 to 1000 ° C. in an oxygen atmosphere or a mixed atmosphere of oxygen and hydrochloric acid. A gate insulating film may be used. (Fig. 14 (A))

[Formation of n ⁻ Region: FIG. 14B] Resist is formed over the entire surface of the island-shaped semiconductor layers 7004 and 7006 and the wiring formation region and part of the island-shaped semiconductor layer 7005 (including the region to be a channel formation region). Masks 7008 to 7011 are formed, and an impurity element imparting n-type conductivity is added to form a low concentration impurity region 7012. This low-concentration impurity region 7012 is an LDD region (hereinafter referred to as Lov region in this specification) that overlaps with a gate electrode through a gate insulating film later on an n-channel TFT of a CMOS circuit. .) Is an impurity region. Note that the concentration of the impurity element imparting n-type contained in the low-concentration impurity region formed here is represented by (n ⁻ ). Therefore, in this specification, the low-concentration impurity region 7012 can be referred to as an n ⁻ region.

Here, phosphorus was added by an ion doping method in which phosphine (PH ₃ ) was plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the underlying semiconductor layer through the gate insulating film 7007. The concentration of phosphorus to be added is preferably in the range of 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , and here it is set to 1 × 10 ¹⁸ atoms / cm ³ .

  Thereafter, the resist masks 7008 to 7011 are removed, and a heat treatment is performed in a nitrogen atmosphere at 400 to 900 ° C., preferably 550 to 800 ° C. for 1 to 12 hours, to activate the phosphorus added in this step. It was.

  [Formation of Conductive Film for Gate Electrode and Wiring: FIG. 14C] Element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W) for the first conductive film 7013 Alternatively, a conductive material containing either of them as a main component was formed to a thickness of 10 to 100 nm. As the first conductive film 7013, for example, tantalum nitride (TaN) or tungsten nitride (WN) is preferably used. Further, a second conductive film 7014 is formed over the first conductive film 7013 with an element selected from Ta, Ti, Mo, and W, or a conductive material whose main component is 100 to 400 nm in thickness. did. For example, Ta may be formed to a thickness of 200 nm. Although not illustrated, it is effective to form a silicon film with a thickness of about 2 to 20 nm below the first conductive film 7013 to prevent oxidation of the conductive films 7013 and 7014 (particularly the conductive film 7014). It is.

[Formation of p-ch gate electrode and wiring electrode and formation of p ⁺ region: FIG. 15A] A resist mask 7015 to 7018 is formed, and a first conductive film and a second conductive film (hereinafter referred to as a laminated film) The gate electrode 7019 and gate wirings 7020 and 7021 of the p-channel TFT are formed. Note that the conductive films 7022 and 7023 were left over the region to be the n-channel TFT so as to cover the entire surface.

Then, a process of adding an impurity element imparting p-type conductivity to part of the semiconductor layer 7004 where the p-channel TFT is formed is performed by leaving the resist masks 7015 to 7018 as they are. Here, boron is used as an impurity element, and diborane (B ₂ H ₆ ) is used for ion doping (of course, ion implantation may be used). Here, boron was added at a concentration of 5 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . Note that the concentration of the impurity element imparting p-type contained in the impurity region formed here is represented by (p ⁺⁺ ). Therefore, in this specification, the impurity regions 7024 and 7025 can be referred to as p ⁺⁺ regions.

  Note that in this step, the gate insulating film 7007 is removed by etching using the resist masks 7015 to 7018 to expose part of the island-shaped semiconductor layer 7004, and then an impurity element imparting p-type is added. May be performed. In that case, since the acceleration voltage may be low, the damage to the island-shaped semiconductor film is small and the throughput is improved.

[Formation of n-ch Gate Electrode: FIG. 15B] Next, after removing the resist masks 7015 to 7018, resist masks 7026 to 7029 were formed, and gate electrodes 7030 and 7031 of n-channel TFTs were formed. . At this time, the gate electrode 7030 was formed so as to overlap the n ⁻ region 7012 with a gate insulating film interposed therebetween.

[Formation of n ⁺ Region: FIG. 15C] Next, the resist masks 7026 to 7029 were removed, and resist masks 7032 to 7034 were formed. Then, a step of forming an impurity region functioning as a source region or a drain region in the n-channel TFT was performed. The resist mask 7034 was formed so as to cover the gate electrode 7031 of the n-channel TFT. This is because an LDD region is formed in an n-channel TFT of the active matrix circuit so as not to overlap with the gate electrode in a later process.

Then, impurity regions 7035 to 7039 were formed by adding an impurity element imparting n-type conductivity. Also here, ion doping using phosphine (PH ₃ ) (of course, ion implantation may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Note that the concentration of the impurity element imparting n-type contained in the impurity regions 7037 to 7039 formed here is represented by (n ⁺ ). Therefore, in this specification, the impurity regions 7037 to 7039 can be referred to as n ⁺ regions. In addition, since the impurity regions 7035 and 7036 have already been formed with n ⁻ regions, strictly speaking, they contain phosphorus at a slightly higher concentration than the impurity regions 7037 to 7039.

  Note that in this step, the gate insulating film 7007 is etched using the resist masks 7032 to 7034 and the gate electrode 7030 as masks to expose part of the island-shaped semiconductor films 7005 and 7006, and then an impurity element imparting n-type conductivity is added. You may perform the process to add. In that case, since the acceleration voltage may be low, the damage to the island-shaped semiconductor film is small and the throughput is improved.

[N ^- region formed in: FIG. 16 (A)] Next, a resist mask 7032 to 7034 is removed, an impurity element imparting n-type to the island-like semiconductor layer 7006 to be an n-channel TFT of the active matrix circuit The step of adding was performed. Impurity regions 7040 to 7043 formed in this way are doped with phosphorus at a concentration (specifically, 5 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ ) that is equal to or less than that of the n ⁻ region. did. Note that the concentration of the impurity element imparting n-type contained in the impurity regions 7040 to 7043 formed here is represented by (n ⁻ ). Therefore, in this specification, the impurity regions 7040 to 7043 can be referred to as n ⁻ regions. In this step, phosphorus is added to all impurity regions except for the impurity region 7067 hidden by the gate electrode at an n ⁻ concentration. However, since the concentration is very low, it can be ignored.

  [Thermal Activation Step: FIG. 16B] Next, a protective insulating film 7044 to be a part of the first interlayer insulating film later was formed. The protective insulating film 7044 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 100 to 400 nm.

  Thereafter, a heat treatment process was performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment was performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 400 to 550 ° C., here 450 ° C. for 2 hours.

  Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  [Formation of Interlayer Insulating Film, Source / Drain Electrode, Light-shielding Film, Pixel Electrode, Retention Capacitor: FIG. 16C] After the activation process is finished, a thickness of 0.5 to 1.5 μm is formed on the protective insulating film 7044 An interlayer insulating film 7045 was formed. A laminated film composed of the protective insulating film 7044 and the interlayer insulating film 7045 was used as a first interlayer insulating film.

  Thereafter, contact holes reaching the source region or the drain region of each TFT were formed, and source electrodes 7046 to 7048 and drain electrodes 7049 and 7050 were formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.

  Next, the passivation film 7051 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm). Thereafter, when the hydrogenation treatment was performed in this state, a favorable result was obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 7051 at a position where a contact hole for connecting the pixel electrode and the drain electrode is formed later.

  Thereafter, a second interlayer insulating film 7052 made of an organic resin was formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above, organic SiO compounds, and the like can also be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.

  Next, a light-shielding film 7053 was formed over the second interlayer insulating film 7052 in a region to be an active matrix circuit. The light-shielding film 7053 is a film having an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or any one of them as a main component and formed to a thickness of 100 to 300 nm. Then, an oxide film 7054 having a thickness of 30 to 150 nm (preferably 50 to 75 nm) was formed on the surface of the light shielding film 7054 by an anodic oxidation method or a plasma oxidation method. Here, an aluminum film or a film containing aluminum as a main component is used as the light-shielding film 7053, and an aluminum oxide film (alumina film) is used as the oxide film 7054.

  Although the insulating film is provided only on the surface of the light shielding film here, the insulating film may be formed by a vapor phase method such as a plasma CVD method, a thermal CVD method, or a sputtering method. In that case also, the film thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Alternatively, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a DLC (Diamond like carbon) film, or an organic resin film may be used. Further, a laminated film combining these may be used.

  Next, a contact hole reaching the drain electrode 7050 was formed in the second interlayer insulating film 7052 to form a pixel electrode 7055. Note that the pixel electrodes 7056 and 7057 are pixel electrodes of different adjacent pixels. For the pixel electrodes 7055 to 7057, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering.

  At this time, a storage capacitor is formed by a region 7058 in which the pixel electrode 7055 and the light-shielding film 7053 overlap with each other with the oxide film 7054 interposed therebetween.

  Thus, an active matrix substrate having a CMOS circuit serving as a driver circuit and an active matrix circuit on the same substrate was completed. Note that an n-channel TFT 7081 and a p-channel TFT 7082 were formed in the CMOS circuit serving as a driver circuit, and a pixel TFT 7083 formed of an n-channel TFT was formed in the active matrix circuit.

In the p-channel TFT 7081 of the CMOS circuit, a channel formation region 7061, a source region 7062, and a drain region 7063 are formed as p ⁺ regions, respectively. The n-channel TFT 7082 includes a channel formation region 7064, a source region 7065, a drain region 7066, and an LDD region (hereinafter referred to as a Lov region) overlapping with a gate electrode through a gate insulating film. 7067 was formed. At this time, the source region 7065 and the drain region 7066 were each formed by an (n ⁻ + n ⁺ ) region, and the Lov region 7067 was formed by an n ⁻ region.

In the pixel TFT 7083, channel formation regions 7068 and 7069, a source region 7070, a drain region 7071, and an LDD region that does not overlap with the gate electrode through the gate insulating film (hereinafter referred to as an Loff region. Note that “off” means offset. 7072 to 7075 and n ⁺ regions 7076 in contact with the Loff regions 7073 and 7074 were formed. At this time, the source region 7070 and the drain region 7071 were each formed of an n ⁺ region, and the Loff regions 7072 to 7075 were formed of an n ⁻ region.

  According to the manufacturing method of this embodiment, the structure of the TFT that forms each circuit is optimized according to the circuit specifications required by the active matrix circuit and the driver circuit, and the operation performance and reliability of the semiconductor device can be improved. . Specifically, n-channel TFTs have a low LDD region arrangement according to circuit specifications and use different Lov regions or Loff regions. A TFT structure with an emphasis on off-current operation was realized.

  For example, the n-channel TFT 7082 is suitable for a logic circuit such as a shift register circuit, a frequency divider circuit, a signal dividing circuit, a level shifter circuit, or a buffer circuit that places importance on high-speed operation. The n-channel TFT 7083 is suitable for an active matrix circuit and a sampling circuit (sample hold circuit) that place importance on low off-current operation.

  The length (width) of the Lov region may be 0.5 to 3.0 μm, typically 1.0 to 1.5 μm with respect to the channel length of 3 to 7 μm. The length (width) of the Loff regions 7072 to 7075 provided in the pixel TFT 7083 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.

  An active matrix substrate is completed through the above steps.

  Next, a process for manufacturing a liquid crystal display device based on the active matrix substrate manufactured by the above process will be described.

  An alignment film (not shown) is formed on the active matrix substrate in the state of FIG. In this embodiment, polyimide is used for the alignment film. Next, a counter substrate is prepared. The counter substrate includes a glass substrate, a counter electrode made of a transparent conductive film, and an alignment film (both not shown).

  In this embodiment, a polyimide film is used as the alignment film. In addition, the rubbing process was performed after alignment film formation. In this embodiment, polyimide having a relatively large pretilt angle is used for the alignment film.

  Next, the active matrix substrate and the counter substrate that have undergone the above-described steps are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling step. Thereafter, liquid crystal is injected between both the substrates and completely sealed with a sealant (both not shown). In this embodiment, nematic liquid crystal is used as the liquid crystal.

  Thus, a liquid crystal display device is completed.

  Note that the amorphous silicon film may be crystallized by laser light (typically excimer laser light) instead of the crystallization method of the amorphous silicon film described in this embodiment.

  Further, instead of using the polycrystalline silicon film, another process may be performed using an SOI structure (SOI substrate) such as smart cut, SIMOX, or ELTRAN.

(Embodiment 6)
In this embodiment mode, another method for manufacturing the liquid crystal display device of the present invention will be described. Here, a method for simultaneously manufacturing TFTs of an active matrix circuit and a driver circuit provided in the periphery thereof will be described.

  [Step of Forming Island-shaped Semiconductor Layer and Gate Insulating Film: FIG. 17A] In FIG. 17A, it is preferable to use an alkali-free glass substrate or a quartz substrate as the substrate 6001. In addition, a substrate in which an insulating film is formed on the surface of a silicon substrate or a metal substrate may be used.

  A base film 6002 made of a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film was formed to a thickness of 100 to 400 nm by a plasma CVD method or a sputtering method on the surface of the substrate 6001 on which the TFT was formed. For example, the base film 6002 is preferably formed to have a two-layer structure in which the silicon nitride film 6002 has a thickness of 25 to 100 nm, here 50 nm, and the silicon oxide film 6003 has a thickness of 50 to 300 nm, here 150 nm. The base film 6002 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used.

  Next, an amorphous silicon film having a thickness of 20 to 100 nm was formed on the base film 6002 by a known film formation method. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atom% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film. Here, since the base film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent surface contamination by preventing exposure to the air atmosphere and to reduce variation in characteristics of the manufactured TFT.

  A known laser crystallization technique or thermal crystallization technique may be used for the step of forming the crystalline silicon film from the amorphous silicon film. Alternatively, a crystalline silicon film may be formed by a thermal crystallization method using a catalyst element that promotes crystallization of silicon. In addition, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly deposited. Further, a crystalline silicon film may be formed using a known technique of SOI (Silicon On Insulators) in which single crystal silicon is bonded onto a substrate.

Unnecessary portions of the crystalline silicon film thus formed were removed by etching to form island-like semiconductor layers 6004 to 6006. In order to control the threshold voltage, boron (B) is added in advance to the region where the n-channel TFT of the crystalline silicon film is formed in order to control the threshold voltage of about 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ^−3. You can keep it.

Next, a gate insulating film 6007 containing silicon oxide or silicon nitride as a main component was formed so as to cover the island-shaped semiconductor layers 6004 to 6006. The gate insulating film 6007 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, a silicon nitride oxide film made of N ₂ O and SiH ₄ as a raw material is formed by plasma CVD to a thickness of 75 nm, and then thermally oxidized at 800 to 1000 ° C. in an oxygen atmosphere or a mixed atmosphere of oxygen and hydrochloric acid. A gate insulating film may be used. (Fig. 17 (A))

[Formation of n ⁻ Region: FIG. 17B] Resist is formed on the entire surface of the island-shaped semiconductor layers 6004 and 6006 and the wiring formation region and part of the island-shaped semiconductor layer 6005 (including the region to be a channel formation region). Masks 6008 to 6011 are formed, and an impurity element imparting n-type conductivity is added to form low-concentration impurity regions 6012 and 6013. The low-concentration impurity regions 6012 and 6013 are LDD regions (hereinafter referred to as Lov regions in this specification) that overlap with the n-channel TFT of the CMOS circuit via the gate insulating film. This is an impurity region for forming (.). Note that the concentration of the impurity element imparting n-type contained in the low-concentration impurity region formed here is represented by (n ⁻ ). Therefore, in this specification, the low-concentration impurity regions 6012 and 6013 can be referred to as n ⁻ regions.

Here, phosphorus was added by an ion doping method in which phosphine (PH ₃ ) was plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the underlying semiconductor layer through the gate insulating film 6007. The concentration of phosphorus to be added is preferably in the range of 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , and here it is set to 1 × 10 ¹⁸ atoms / cm ³ .

  Thereafter, the resist masks 6008 to 6011 are removed, and a heat treatment is performed at 400 to 900 ° C., preferably 550 to 800 ° C. for 1 to 12 hours in a nitrogen atmosphere, and a step of activating phosphorus added in this step is performed. It was.

  [Formation of Conductive Film for Gate Electrode and Wiring: FIG. 17C] Element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W) for the first conductive film 6014 Alternatively, a conductive material containing either of them as a main component was formed to a thickness of 10 to 100 nm. As the first conductive film 6014, for example, tantalum nitride (TaN) or tungsten nitride (WN) is preferably used. Further, a second conductive film 6015 is formed over the first conductive film 6014 with a thickness of 100 to 400 nm using a conductive material mainly containing any element selected from Ta, Ti, Mo, and W. did. For example, Ta may be formed to a thickness of 200 nm. Although not shown, it is effective to form a silicon film with a thickness of about 2 to 20 nm below the first conductive film 6014 in order to prevent oxidation of the conductive films 6014 and 6015 (particularly the conductive film 6015). It is.

[Formation of p-ch gate electrode and wiring electrode and formation of p ⁺ region: FIG. 18A] Resist masks 6016 to 6019 are formed, and a first conductive film and a second conductive film (hereinafter referred to as a laminated film) The gate electrode 6020 and the gate wirings 6021 and 6022 of the p-channel TFT are formed. Note that the conductive films 6023 and 6024 were left over the region to be the n-channel TFT so as to cover the entire surface.

Then, a process of adding an impurity element imparting p-type conductivity to part of the semiconductor layer 6004 in which the p-channel TFT is formed is performed by leaving the resist masks 6016 to 6019 as they are. Here, boron is used as an impurity element, and diborane (B ₂ H ₆ ) is used for ion doping (of course, ion implantation may be used). Here, boron was added at a concentration of 5 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . Note that the concentration of the impurity element imparting p-type contained in the impurity region formed here is represented by (p ⁺⁺ ). Accordingly, in this specification, the impurity regions 6025 and 6026 can be referred to as p ⁺⁺ regions.

  Note that in this step, the gate insulating film 6007 is removed by etching using the resist masks 6016 to 6019 to expose part of the island-shaped semiconductor layer 6004, and then an impurity element imparting p-type is added. May be performed. In that case, since the acceleration voltage may be low, the damage to the island-shaped semiconductor film is small and the throughput is improved.

[Formation of n-ch Gate Electrode: FIG. 18B] Next, after removing the resist masks 6016 to 6019, resist masks 6027 to 6030 are formed, and gate electrodes 6031 and 6032 of n-channel TFTs are formed. . At this time, the gate electrode 6031 was formed so as to overlap with the n ⁻ regions 6012 and 6013 through the gate insulating film.

[Formation of n ⁺ Region: FIG. 18C] Next, the resist masks 6027 to 6030 were removed, and resist masks 6033 to 6035 were formed. Then, a step of forming an impurity region functioning as a source region or a drain region in the n-channel TFT was performed. The resist mask 6035 was formed so as to cover the gate electrode 6032 of the n-channel TFT. This is because an LDD region is formed in an n-channel TFT of the active matrix circuit so as not to overlap with the gate electrode in a later process.

Then, impurity regions 6036 to 6040 were formed by adding an impurity element imparting n-type conductivity. Here again, ion doping using phosphine (PH ₃ ) (of course, ion implantation may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Note that the concentration of the impurity element imparting n-type contained in the impurity regions 6038 to 6040 formed here is represented by (n ⁺ ). Therefore, in this specification, the impurity regions 6038 to 6040 can be referred to as n ⁺ regions. Further, since the n ⁻ region has already been formed in the impurity regions 6036 and 6037, strictly speaking, the impurity regions 6036 and 6037 contain phosphorus at a slightly higher concentration than the impurity regions 6038 to 6040.

  Note that in this step, the gate insulating film 6007 is etched using the resist masks 6033 to 6035 and the gate electrode 6031 as a mask to expose part of the island-shaped semiconductor films 6005 and 6006, and then an impurity element imparting n-type conductivity is used. You may perform the process to add. In that case, since the acceleration voltage may be low, the damage to the island-shaped semiconductor film is small and the throughput is improved.

[N ^- region formed in: FIG. 19 (A)] Next, a resist mask 6033 to 6035 is removed, an impurity element imparting n-type to the island-like semiconductor layer 6006 to be an n-channel TFT of the active matrix circuit The step of adding was performed. Impurity regions 6041 to 6044 thus formed are doped with phosphorus at a concentration (specifically, 5 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ ) of the same level as or lower than that of the n ⁻ region. did. Note that the concentration of the impurity element imparting n-type contained in the impurity regions 6041 to 6044 formed here is represented by (n ⁻ ). Therefore, in this specification, the impurity regions 6041 to 6044 can be referred to as n ⁻ regions. In this step, phosphorus is added to all impurity regions except for the impurity region 6068 hidden by the gate electrode at an n ⁻ concentration. However, since the concentration is very low, it can be ignored.

  [Thermal Activation Process: FIG. 19B] Next, a protective insulating film 6045 to be a part of the first interlayer insulating film later was formed. The protective insulating film 6045 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 100 to 400 nm.

  Thereafter, a heat treatment process was performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment was performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 400 to 550 ° C., here 450 ° C. for 2 hours.

  Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  [Formation of Interlayer Insulating Film, Source / Drain Electrode, Light-shielding Film, Pixel Electrode, Retention Capacitor: FIG. 19C] After the activation process is finished, a thickness of 0.5 to 1.5 μm is formed on the protective insulating film 6045. An interlayer insulating film 6046 was formed. A laminated film composed of the protective insulating film 6045 and the interlayer insulating film 6046 was used as a first interlayer insulating film.

  Thereafter, contact holes reaching the source region or the drain region of each TFT were formed, and source electrodes 6047 to 6049 and drain electrodes 6050 and 6051 were formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.

  Next, the passivation film 6052 was formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm). Thereafter, when the hydrogenation treatment was performed in this state, a favorable result was obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 6052 at a position where a contact hole for connecting the pixel electrode and the drain electrode later is formed.

  Thereafter, a second interlayer insulating film 6053 made of an organic resin was formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above, organic SiO compounds, and the like can also be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.

  Next, a light-shielding film 6054 was formed over the second interlayer insulating film 6053 in a region to be an active matrix circuit. The light-shielding film 6054 is a film having an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or any one of them as a main component and formed to a thickness of 100 to 300 nm. Then, an oxide film 6055 having a thickness of 30 to 150 nm (preferably 50 to 75 nm) was formed on the surface of the light shielding film 6055 by an anodic oxidation method or a plasma oxidation method. Here, an aluminum film or a film containing aluminum as a main component is used as the light-shielding film 6055, and an aluminum oxide film (alumina film) is used as the oxide film 6055.

  Although the insulating film is provided only on the surface of the light shielding film here, the insulating film may be formed by a vapor phase method such as a plasma CVD method, a thermal CVD method, or a sputtering method. In that case also, the film thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Alternatively, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a DLC (Diamond like carbon) film, or an organic resin film may be used. Further, a laminated film combining these may be used.

  Next, a contact hole reaching the drain electrode 6051 was formed in the second interlayer insulating film 6055, and a pixel electrode 6056 was formed. Note that the pixel electrodes 6057 and 6058 are pixel electrodes of different adjacent pixels. For the pixel electrodes 6056 to 6058, a transparent conductive film is used when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is used. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering.

  At this time, a region 6059 in which the pixel electrode 6056 and the light-shielding film 6054 overlap with each other through the oxide film 6055 forms a storage capacitor.

  Thus, an active matrix substrate having a CMOS circuit serving as a driver circuit and an active matrix circuit on the same substrate was completed. Note that an n-channel TFT 6081 and a p-channel TFT 6082 were formed in the CMOS circuit serving as a driver circuit, and a pixel TFT 6083 formed of an n-channel TFT was formed in the active matrix circuit.

In the p-channel TFT 6081 of the CMOS circuit, a channel formation region 6062, a source region 6063, and a drain region 6064 are formed as p ⁺ regions, respectively. The n-channel TFT 6082 includes a channel formation region 6065, a source region 6066, a drain region 6067, and an LDD region (hereinafter referred to as an Lov region) overlapping with a gate electrode through a gate insulating film. 6068) was formed. At this time, the source region 6066 and the drain region 6067 are each formed of an (n ⁻ + n ⁺ ) region, and the Lov region 6068 is formed of an n ⁻ region.

The pixel TFT 6084 includes channel formation regions 6069 and 6070, a source region 6071, a drain region 6072, and an LDD region that does not overlap with the gate electrode through the gate insulating film (hereinafter referred to as an Loff region. Note that “off” means offset. The n ⁺ region 6077 in contact with 6073 to 6076 and the Loff regions 6074 and 6075 was formed. At this time, the source region 6071 and the drain region 6072 were each formed of an n ⁺ region, and the Loff regions 6073 to 6076 were formed of an n ⁻ region.

  According to the manufacturing method of this embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the active matrix circuit and the driver circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel TFTs have a low LDD region arrangement according to circuit specifications and use different Lov regions or Loff regions. A TFT structure emphasizing off-current operation is realized.

  For example, in the case of an active matrix liquid crystal display device, the n-channel TFT 6082 is suitable for logic circuits such as a shift register circuit, a frequency divider circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit that place importance on high-speed operation. The n-channel TFT 6083 is suitable for an active matrix circuit and a sampling circuit (sample hold circuit) that place importance on low off-current operation.

  The length (width) of the Lov region may be 0.5 to 3.0 μm, typically 1.0 to 1.5 μm with respect to the channel length of 3 to 7 μm. The length (width) of the Loff regions 6073 to 6076 provided in the pixel TFT 6083 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.

  A liquid crystal display device is manufactured based on the active matrix substrate manufactured through the above steps. See Embodiment 5 for an example of a manufacturing process.

(Embodiment 7)
FIG. 20 is an example of another configuration of the active matrix substrate of the liquid crystal display device of the present invention. 8001 is a p-channel TFT, 8002 is an n-channel TFT, 8003 is an n-channel TFT, and 8004 is an n-channel TFT. Reference numerals 8001, 8002, and 8003 constitute a circuit portion of the driver, and reference numeral 8004 constitutes an active matrix circuit portion.

Reference numerals 8005 to 8013 denote pixel TFT semiconductor layers constituting the active matrix circuit. 8005, 8009 and 8013 are n ⁺ regions, 8006, 8008, 8010 and 8012 are n ⁻ regions, and 8007 and 8011 are channel forming regions. Reference numeral 8014 denotes an insulating film cap layer, which is provided to form an offset portion in the channel formation region.

  For the present embodiment, Japanese Patent Application No. 11-67809, which is a patent application of the present applicant, can be referred to.

(Embodiment 8)
The above-described liquid crystal display device of the present invention can be used in a three-plate projector as shown in FIG.

  In FIG. 21, 2401 is a white light source, 2402 to 2405 are dichroic mirrors, 2406 and 2407 are total reflection mirrors, 2408 to 2410 are liquid crystal display devices of the present invention, and 2411 is a projection lens.

(Embodiment 9)
Further, the above-described liquid crystal display device of the present invention can also be used for a three-plate projector as shown in FIG.

  In FIG. 23, 2501 is a white light source, 2502 and 2503 are dichroic mirrors, 2504 to 2506 are total reflection mirrors, 2507 to 2509 are liquid crystal display devices of the present invention, 2510 is a dichroic prism, and 2511 is a projection lens.

(Embodiment 10)
Further, the above-described liquid crystal display device of the present invention can also be used for a single-plate projector as shown in FIG.

  In FIG. 23, reference numeral 2601 denotes a white light source composed of a lamp and a reflector. Reference numerals 2602, 2603, and 2604 are dichroic mirrors that selectively reflect light in the blue, red, and green wavelength regions, respectively. Reference numeral 2605 denotes a microlens array, which is composed of a plurality of microlenses. Reference numeral 2606 denotes a liquid crystal display device of the present invention. Reference numeral 2607 denotes a field lens, 2608 denotes a projection lens, and 2609 denotes a screen.

(Embodiment 11)
The projectors of the eighth to tenth embodiments include a rear projector and a front projector depending on the projection method.

  FIG. 24A shows a front projector, which includes a main body 10001, a liquid crystal display device 10002 of the present invention, a light source 10003, an optical system 10004, and a screen 10005. FIG. 24A shows a front projector that incorporates one liquid crystal display device. By incorporating three liquid crystal display devices (corresponding to R, G, and B light, respectively), A front projector having a higher resolution and higher definition can be realized.

  FIG. 24B shows a rear type projector, 10006 a main body, 10007 a liquid crystal display device, 10008 a light source, 10009 a reflector, and 10010 a screen. FIG. 24B shows a rear projector in which three active matrix semiconductor display devices are incorporated (corresponding to R, G, and B lights, respectively).

Embodiment 12
In this embodiment, an example in which the liquid crystal display device of the present invention is used for a goggle type display is shown.

  Refer to FIG. Reference numeral 2801 denotes a goggle type display main body. 2802-R and 2802-L are liquid crystal display devices of the present invention, 2803-R and 2803-L are LED backlights, and 2804-R and 2804-L are optical elements.

(Embodiment 13)
In the present embodiment, field sequential driving is performed by using an LED for the backlight of the liquid crystal display device of the present invention.

  The timing chart of the field sequential driving method shown in FIG. 26 includes image signal writing start signal (Vsync signal), red (R), green (G) and blue (B) LED lighting timing signals (R, G and B) and a video signal (VIDEO). Tf is a frame period. TR, TG, and TB are LED lighting periods of red (R), green (G), and blue (B), respectively.

  An image signal, for example, R1, supplied to the liquid crystal display device is a signal obtained by compressing original video data corresponding to red input from the outside to 1/3 in the time axis direction. An image signal, for example G1, supplied to the liquid crystal panel is a signal obtained by compressing original video data corresponding to green input from the outside to 1/3 in the time axis direction. An image signal supplied to the liquid crystal panel, for example, B1, is a signal obtained by compressing original video data corresponding to blue input from the outside to 1/3 in the time axis direction.

  In the field sequential driving method, the R, G, and B LEDs are sequentially lit in the LED lighting period TR period, TG period, and TB period, respectively. During the lighting period (TR) of the red LED, a video signal (R1) corresponding to red is supplied to the liquid crystal panel, and one red image is written on the liquid crystal panel. Further, during the green LED lighting period (TG), video data (G1) corresponding to green is supplied to the liquid crystal panel, and one green image is written on the liquid crystal panel. Also, during the lighting period (TB) of the blue LED, video data (B1) corresponding to blue is supplied to the liquid crystal display device, and one screen image of blue is written on the liquid crystal display device. One frame is formed by writing these three images.

(Embodiment 14)
In this embodiment, an example in which the liquid crystal display device of the present invention is used in a notebook personal computer is shown in FIG.

  Reference numeral 3001 denotes a notebook personal computer main body, and 3002 denotes a liquid crystal display device of the present invention. Moreover, LED is used for the backlight. In addition, you may use a cathode tube for a backlight conventionally.

(Embodiment 15)
The liquid crystal display device of the present invention has various other uses. In this embodiment, a semiconductor device incorporating the liquid crystal display device of the present invention will be described.

  Examples of such a semiconductor device include a video camera, a still camera, a car navigation system, a personal computer, and a portable information terminal (such as a mobile computer and a mobile phone). An example of them is shown in FIG.

  FIG. 28A shows a cellular phone, which includes a main body 11001, an audio output portion 11002, an audio input portion 11003, the liquid crystal display device 11004 of the present invention, an operation switch 11005, and an antenna 11006.

  FIG. 28B shows a video camera, which includes a main body 12001, a liquid crystal display device 12002 of the present invention, an audio input portion 12003, operation switches 12004, a battery 12005, and an image receiving portion 12006.

  FIG. 28C shows a mobile computer which includes a main body 13001, a camera portion 13002, an image receiving portion 13003, an operation switch 13004, and the liquid crystal display device 13017 of the present invention.

  FIG. 28D illustrates a portable book (electronic book) which includes a main body 14001, liquid crystal display devices 14002 and 14003 of the present invention, a storage medium 14004, operation switches 14005, and an antenna 14006.

  FIG. 29A illustrates a personal computer, which includes a main body 15001, an image input portion 15002, a display portion 15003, a keyboard 15004, and the like. The present invention can be applied to the image input unit 15002, the display unit 15003, and other signal control circuits.

  FIG. 29B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 16001, a display portion 16002, a speaker portion 16003, a recording medium 16004, an operation switch 16005, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 16002 and other signal control circuits.

  FIG. 29C illustrates a digital camera, which includes a main body 17001, a display portion 17002, an eyepiece portion 17003, an operation switch 17004, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 17002 and other signal control circuits.

  FIG. 29D illustrates a display which includes a main body 18001, a support base 18002, a display portion 18003, and the like. The present invention can be applied to the display portion 18003. FIG. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

It is a schematic block diagram of the liquid crystal display device of this invention. It is a schematic block diagram of the liquid crystal panel of this invention. It is a schematic block diagram of the liquid crystal panel of this invention. It is a schematic block diagram of the liquid crystal display device of this invention. 1 is a circuit configuration diagram of an active matrix circuit, a source driver, and a gate driver of an embodiment of a liquid crystal display device of the present invention. It is a figure which shows the gradation display level of one embodiment of the liquid crystal display device of this invention. It is a figure which shows the drive timing chart of embodiment with the liquid crystal display device of this invention. It is a figure which shows the drive timing chart of embodiment with the liquid crystal display device of this invention. It is a figure which shows the drive timing chart of embodiment with the liquid crystal display device of this invention. It is a figure which shows the drive timing chart of embodiment with the liquid crystal display device of this invention. It is a figure which shows the drive timing chart of embodiment with the liquid crystal display device of this invention. 1 is a schematic configuration diagram of an embodiment of a liquid crystal display device of the present invention. 1 is a circuit configuration diagram of an active matrix circuit, a source driver, and a gate driver of an embodiment of a liquid crystal display device of the present invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is a figure which shows the example of a manufacturing process of the liquid crystal display device of this invention. It is sectional drawing of the liquid crystal display device of this invention. 1 is a schematic configuration diagram of a three-plate projector using a liquid crystal display device of the present invention. 1 is a schematic configuration diagram of a three-plate projector using a liquid crystal display device of the present invention. 1 is a schematic configuration diagram of a single-plate projector using a liquid crystal display device of the present invention. It is a schematic block diagram of a front projector and a rear projector using the liquid crystal display device of the present invention. It is a schematic block diagram of a goggle type display using the liquid crystal display device of the present invention. It is a timing chart of field sequential drive. 1 is a schematic configuration diagram of a notebook personal computer using a liquid crystal display device of the present invention. It is an example of the electronic device using the liquid crystal display device of this invention. It is an example of the electronic device using the liquid crystal display device of this invention. It is a schematic block diagram of the liquid crystal display device of this invention.

Explanation of symbols

101 liquid crystal panel 101-1 active matrix substrate 101-1-1 source driver 101-1-2 gate driver 101-1-3 gate driver 101-1-4 active matrix circuit 101-2 counter substrate 101-2-1 counter electrode 102 digital video data time gradation processing circuit 103 counter electrode control circuit

Claims (7)

A liquid crystal display device that performs image display by line-sequentially driving a plurality of pixels having thin film transistors,
A source electrode and a drain electrode provided above the thin film transistor;
An organic resin film provided above the source and drain electrodes;
A pixel electrode provided above the organic resin film;
A counter electrode provided facing the pixel electrode;
A liquid crystal layer provided between the pixel electrode and the counter electrode;
Have
A voltage higher than the analog gradation voltage is applied to the liquid crystal layer before writing the analog gradation voltage to the plurality of pixels. A liquid crystal display device that performs image display by line-sequentially driving a plurality of pixels having thin film transistors,
A source electrode and a drain electrode made of a laminated film containing aluminum provided above the thin film transistor;
An organic resin film provided above the source and drain electrodes;
A pixel electrode provided above the organic resin film;
A counter electrode provided facing the pixel electrode;
A liquid crystal layer provided between the pixel electrode and the counter electrode;
Have
A voltage higher than the analog gradation voltage is applied to the liquid crystal layer before writing the analog gradation voltage to the plurality of pixels. A liquid crystal display device that performs image display by line-sequentially driving a plurality of pixels having thin film transistors,
A source electrode and a drain electrode made of a laminated film containing aluminum provided above the thin film transistor;
An organic resin film provided above the source and drain electrodes;
A pixel electrode provided above the organic resin film;
A counter electrode provided facing the pixel electrode;
A liquid crystal layer provided between the pixel electrode and the counter electrode;
LED backlight,
Have
A voltage higher than the analog gradation voltage is applied to the liquid crystal layer before writing the analog gradation voltage to the plurality of pixels. A liquid crystal display device that performs image display by line-sequentially driving a plurality of pixels having thin film transistors,
A source electrode and a drain electrode made of a laminated film containing aluminum provided above the thin film transistor;
A silicon nitride film provided above the source and drain electrodes;
An organic resin film provided above the silicon nitride film;
A pixel electrode provided above the organic resin film;
A counter electrode provided facing the pixel electrode;
A liquid crystal layer provided between the pixel electrode and the counter electrode;
LED backlight,
Have
A voltage higher than the analog gradation voltage is applied to the liquid crystal layer before writing the analog gradation voltage to the plurality of pixels. A liquid crystal display device that performs image display by line-sequentially driving a plurality of pixels having thin film transistors,
A source electrode and a drain electrode made of a laminated film containing aluminum provided above the thin film transistor;
A silicon nitride film provided above the source and drain electrodes;
A first contact hole provided in the silicon nitride film;
An organic resin film provided above the silicon nitride film;
A second contact hole provided in the organic resin film;
A pixel electrode provided above the organic resin film and inside the first and second contact holes;
A counter electrode provided facing the pixel electrode;
A liquid crystal layer provided between the pixel electrode and the counter electrode;
LED backlight,
Have
A voltage higher than the analog gradation voltage is applied to the liquid crystal layer before writing the analog gradation voltage to the plurality of pixels. In any one of Claims 3 thru | or 5,
The LED backlight includes red (R), green (G), and blue (B) LEDs. In any one of Claims 1 thru | or 6,
The liquid crystal display device, wherein the organic resin film includes polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene).

Images