JP2006210759A - Etching liquid for controlling surface profile of silicon wafer, and process for producing silicon wafer using that etching liquid - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the load on a double-sided simultaneous polishing step or a single-sided polishing step in a process for producing a silicon wafer, and to reduce the surface roughness of a wafer, while maintaining flatness, when planarization step is ended. <P>SOLUTION: The process for producing a silicon wafer comprises a step 13 for planarizing the front and rear sides of a disc-like silicon wafer obtained by slicing a silicon single crystal ingot by grinding or lapping; a step for etching the front and rear sides of the silicon wafer, by immersing it into etching liquid for controlling surface profile of the silicon wafer produced by admixing a fluorine-based surfactant uniformly to alkaline aqueous solution; a double-sided simultaneous polishing step 16 for simultaneously polishing the front and rear sides of the etched silicon wafer; and a single-sided polishing step for polishing the front and rear sides of the etched silicon wafer one by one, in this order. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention reduces the load of the double-sided simultaneous polishing process and can achieve both high flatness and reduced surface roughness, and a silicon wafer surface shape control etching solution and a silicon wafer manufacturing method using the etching solution It is about.

Generally, the manufacturing process of a semiconductor silicon wafer is composed of steps of chamfering, mechanical polishing (lapping), etching, mirror polishing (polishing) and cleaning a wafer obtained by cutting and slicing from a pulled silicon single crystal ingot, Produced as a wafer with high precision flatness. Silicon wafers that have undergone machining processes such as block cutting, outer diameter grinding, slicing, and lapping have a damaged layer, that is, a work-affected layer on the surface. The work-affected layer must be removed completely because it induces crystal defects such as slip dislocations in the device manufacturing process, reduces the mechanical strength of the wafer, and adversely affects the electrical properties.
Etching is performed to remove the work-affected layer. For the etching treatment, either acid etching or alkali etching is employed. In this etching process, the work-affected layer is chemically removed by immersing a plurality of wafers in an etching tank storing an etching solution.

Acid etching does not have selective etching properties with respect to a silicon wafer, has a small surface roughness, improves micro shape accuracy, and has an advantage of high etching efficiency. As an etching solution for this acid etching, an etching solution containing a ternary element obtained by diluting a mixed acid of hydrofluoric acid (HF) and nitric acid (HNO ₃ ) with water (H ₂ O) or acetic acid (CH ₃ COOH) is mainly used. Yes. The above-mentioned advantage can be obtained by acid etching because the etching proceeds based on the diffusion-controlled condition with the above-mentioned etching solution, and under this diffusion-controlled condition, the reaction rate depends on the crystal surface orientation, crystal defects, etc. It is thought that the diffusion on the crystal surface has the main effect. However, with this acid etching, it is possible to etch the work-affected layer while improving the surface roughness of the silicon wafer, but as the acid etching progresses, the outer periphery of the wafer sags and the macro shape obtained by lapping The flatness, which is the accuracy, is impaired, and there is a problem in that the etching surface has undulations on the order of mm and irregularities called peels. Further, there is a drawback that the cost of the chemical solution is high and it is difficult to control and maintain the composition of the etching solution.

Alkaline etching, improves excellent macro shape precision flatness, and less metal contamination, there is a harmful by-product of the problem and there is no handling of risk features such as of the NO _x in the acid etching. KOH or NaOH is used as an etching solution for this alkali etching. It is considered that the above characteristics can be obtained by alkaline etching because this etching basically proceeds based on surface reaction rate-determining conditions. However, in alkali etching, the work-affected layer can be etched while maintaining the flatness of the silicon wafer, but the local depth is several μm and the size is about several to several tens of μm. This is called facet), and there is a problem that the wafer surface roughness deteriorates.

As a measure for solving the problems in the alkaline etching, a silicon wafer using a solution in which hydrogen peroxide is added at a ratio of 0.01 to 0.2 parts by weight with respect to 100 parts by weight of an aqueous solution of sodium hydroxide (sodium hydroxide). An etching method is disclosed (for example, refer to Patent Document 1). According to the etching method disclosed in Patent Document 1, by adding hydrogen peroxide to a caustic soda aqueous solution at a predetermined ratio, there is a problem that a problem caused in alkali etching by the caustic soda aqueous solution is solved. Specifically, compared to etching using NaOH aqueous solution, the size of the etch pits on the back surface of the silicon wafer is reduced, and the generation of minute etch pits on the back surface of the silicon wafer is suppressed. The etching rate can be adjusted to a desired value, and the etching rate is further increased.
JP-A-7-37871 (Claims 1-4, paragraph [0021])

  However, in the conventional method including the method disclosed in Patent Document 1, the wafer that has been etched is subjected to a double-sided simultaneous polishing step or a single-side polishing step and its surface is processed into a mirror surface, but the etching step is finished. On the front and back surfaces of the silicon wafer, the wafer flatness when the flattening process is finished is not maintained, and the desired wafer surface roughness is not obtained. In order to improve, it is necessary to take a lot of polishing allowance in the double-sided simultaneous polishing step and the single-sided polishing step, so that a large load is applied to the double-sided simultaneous polishing step and the single-side polishing step.

  An object of the present invention is to reduce the load of a double-sided simultaneous polishing process and a single-side polishing process, and to maintain both wafer flatness and wafer surface roughness after finishing the planarization process. An object is to provide an etching solution for shape control and a method for producing a silicon wafer using the etching solution.

The invention according to claim 1 is an etching solution for controlling the shape of the surface of a silicon wafer, wherein a fluorine-based surfactant is uniformly mixed in an alkaline aqueous solution.
In the invention according to claim 1, the etching solution obtained by uniformly mixing the fluorosurfactant with the alkaline aqueous solution can control the surface roughness and texture size of the wafer before polishing, so the planarization treatment is finished. When the silicon wafer having a damaged layer is etched using this etchant, the planarization process is completed while reducing the polishing allowance on the wafer front and back surfaces in the double-sided simultaneous polishing process and single-sided polishing process. Both the maintenance of the wafer flatness and the reduction of the wafer surface roughness can be achieved.

The invention according to claim 2 is the invention according to claim 1, wherein the alkaline aqueous solution is a 20 to 50% by weight sodium hydroxide aqueous solution, and the addition ratio of the fluorosurfactant added to the alkaline aqueous solution is hydroxylated. It is an etching liquid which is 0.0015-15g / L with respect to sodium.
In the invention which concerns on Claim 2, the wafer surface roughness and wafer flatness which finished the etching process can be reduced more by adding a fluorine-type surfactant to the sodium hydroxide aqueous solution of the said density | concentration range by a predetermined ratio. it can.

As shown in FIG. 1, the invention according to claim 3 is a planarization step 13 for grinding or lapping the front and back surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot. Or an etching step 14 for immersing the silicon wafer in the etching solution described in 2 to etch the front and back surfaces of the silicon wafer, and a double-sided simultaneous polishing step 16 for simultaneously polishing the front and back surfaces of the etched silicon wafer. This is a silicon wafer manufacturing method.
In the invention according to claim 3, the surface roughness and texture size of the wafer before polishing can be controlled by the etching step 14 using an etching solution prepared by adding a fluorosurfactant to an alkaline aqueous solution. Both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization process is completed can be achieved while reducing the polishing allowance on the wafer front and back surfaces in the double-sided simultaneous polishing process 16.

According to a fourth aspect of the present invention, there is provided a planarization step of grinding or lapping the front and back surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot; A method for producing a silicon wafer, comprising: an etching step of immersing the wafer to etch the front and back surfaces of the silicon wafer; and a single-side polishing step of polishing the front and back surfaces of the etched silicon wafer one by one in this order.
In the invention according to claim 4, the surface roughness and texture size of the wafer before polishing can be controlled by an etching process using an etching solution prepared by adding a fluorine-based surfactant to an alkaline aqueous solution. While reducing the polishing allowance on the front and back surfaces of the wafer in the single-side polishing step, it is possible to achieve both maintenance of the wafer flatness and reduction of the wafer surface roughness when the flattening step is finished.

The etching solution for controlling the surface shape of a silicon wafer according to the present invention is an etching solution characterized in that a fluorine-based surfactant is uniformly mixed in an alkaline aqueous solution. This etching solution is a surface roughness and texture of a wafer before polishing. Since the size can be controlled, the silicon wafer having a work-affected layer that has been flattened is etched using this etchant, so that both the front and back surfaces of the wafer in the double-side simultaneous polishing step and the single-side polishing step Both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization process is completed can be achieved while reducing the polishing allowance.
Also, the silicon wafer manufacturing method of the present invention controls the surface roughness and texture size of the wafer before polishing by an etching process using an etching solution prepared by adding a fluorosurfactant to an alkaline aqueous solution. Therefore, both the wafer flatness and the wafer surface roughness can be reduced when the planarization process is completed while reducing the polishing allowance on the front and back surfaces of the wafer in the double-sided simultaneous polishing process and single-sided polishing process. be able to.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
The silicon wafer surface shape control etching liquid of the present invention is characterized in that a fluorine-based surfactant is uniformly mixed in an alkaline aqueous solution. An etching solution in which a fluorosurfactant is uniformly mixed with this alkaline aqueous solution acts on metal impurities in the chemical by adding a fluorosurfactant to suppress the selectivity specific to alkaline etching. Since the surface roughness and texture size of the wafer before polishing can be controlled, the double-sided simultaneous polishing step is performed by etching the silicon wafer having the work-affected layer after the planarization treatment using this etching solution. In addition, both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization process is completed can be achieved while reducing the polishing allowance on the front and back surfaces of the wafer in the single-side polishing process.

In the etching solution of the present invention, a fluorinated surfactant is added in a predetermined ratio to an aqueous alkaline solution adjusted to a predetermined concentration, and the resultant liquid is stirred to uniformly distribute the fluorinated surfactant in the aqueous alkaline solution. Obtained by mixing. Examples of the alkaline aqueous solution contained in the etching solution of the present invention include potassium hydroxide and sodium hydroxide, and in particular, a hydroxide having a sodium hydroxide concentration of 20 to 50% by weight, preferably 40 to 50% by weight. The aqueous sodium solution is excellent in reducing the surface roughness of the wafer before polishing and suppressing the texture size. Further, when the addition ratio of the fluorosurfactant added to the 20 to 50% by weight sodium hydroxide aqueous solution is within the range of 0.0015 to 15 g / L with respect to sodium hydroxide, the wafer which has finished the etching process This is preferable because the surface roughness and the wafer flatness can be further reduced. In particular, it is preferable to make it into the range of 0.15-1.5 g / L with respect to sodium hydroxide. The fluorine-based surfactant used in the etching solution of the present invention includes 1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,8- Pentadecafluoro-1-octanesulfonic acid (C ₈ F ₁₇ SO ₃ H), potassium perfluorooctane sulfonate (C ₈ F ₁₇ SO ₃ K), sodium perfluorooctane sulfonate (C ₈ F ₁₇ SO ₃ Na), perfluoro octanoic acid ammonium _{(C 8 F 17 SO 3 NH} 4), lithium perfluorooctane sulfonate _{(C 8 F 17 SO 3 Li} ), N- propyl -N- perfluorooctyl sulfonyl glycine potassium salt (C ₈ F ₁₇ SO ₂ N _{(C 3 H 7) CH 2} COOK), N- (2- hydroxyethyl) -N- propyl perfluorooctane sulfonamide _{(C 8 F 17 SO 2 N} (C 3 H 7) CH 2 CH 2 OH), N- Polyoxyethylene-N-propyl perfluorooctane Hon'amido _{(C 8 F 17 SO 2 N} (C 3 H 7) (C 2 H 4 O) n H; n = 3,10,20), phosphoric acid bis [2-(N-propyl-perfluorooctyl sulfonylamino) ethyl ] -Ester ([C ₈ F ₁₇ SO ₂ N (C ₃ H ₇ ) (C ₂ H ₄ O)] ₂ PO (OH)), bis [2- (N-propylperfluorooctylsulfonylamino) ethyl phosphate] -Ammonium salt ([C ₈ F ₁₇ SO ₂ N (C ₃ H ₇ ) (C ₂ H ₄ O)] ₂ PO (ONH ₄ )), N- [3- (perfluorooctanesulfonamido) propyl] -N, N, N- trimethylammonium = iodide _{(C 8 F 17 SO 2 NHCH} 2 CH 2 CH 2 N + (CH 3) 3 I -), acrylic acid polyoxyalkylene (C _2-3) alkyl ether acrylate N- perfluorooctyl sulfonyl -N- alkyl aminoethyl copolymers, acrylic acid polyoxyalkylene (C _2-3) glycolate Monoester / N-perfluorooctylsulfonyl-N-alkylaminoethyl copolymer, polyoxyethylene alkyl ether / N-perfluorooctylsulfonyl-N-alkylaminoethyl copolymer (50% ethyl acetate) , Polyoxyalkylene acrylate (C _2-3 ) alkyl ether / N-perfluorooctylsulfonyl acrylate-N-alkylaminoethyl copolymer (50% ethyl acetate), Polyoxyalkylene acrylate (C _2-3 ) glycol Monoester / N-perfluorooctylsulfonyl-N-alkylaminoethyl copolymer of acrylic acid, pentadecafluorooctanoic acid (C ₇ F ₁₅ COOH), ammonium pentadecafluorooctanoate (C ₇ F ₁₅ COONH ₄ ), perfluorobutane Sulfonic acid (C ₄ F ₉ SO ₃ H), potassium perfluorobutane sulfonate _{(C 4 F 9 SO 3 K} ), lithium perfluorobutane sulfonate _{(C 4 F 9 SO 3 Li} ) , and the like. Among them, C ₈ F ₁₇ SO ₃ K and C ₈ F ₁₇ SO ₃ Na are preferable because they act upon reaction with the silicon interface in alkali etching and have an effect of weakening the selectivity specific to alkali etching.

Next, a method for producing a silicon wafer using the silicon wafer surface shape control etching solution of the present invention will be described.
First, the grown silicon single crystal ingot is cut into a block shape by cutting the front end portion and the terminal end portion, and the outer diameter of the ingot is ground to obtain a block body in order to make the diameter of the ingot uniform. In order to show a specific crystal orientation, an orientation flat or an orientation notch is applied to the block body. After this process, as shown in FIG. 1, the block body is sliced at a predetermined angle with respect to the rod axis direction (step 11). The wafer sliced in step 11 is chamfered around the wafer in order to prevent chipping and chips at the periphery of the wafer (step 12). By applying this chamfering, for example, when the epitaxial growth is performed on the surface of the silicon wafer that is not chamfered, a crown phenomenon in which abnormal growth occurs in the peripheral portion and rises in a ring shape can be suppressed.

Subsequently, the uneven layers on the front and rear surfaces of the thin disk-shaped silicon wafer generated in the process such as slicing are planarized to increase the flatness of the wafer front and rear surfaces and the parallelism of the wafer (step 13). In the flattening step 13, the front and back surfaces of the wafer are flattened by grinding or lapping.
As a method for flattening the wafer by grinding, a grinding apparatus 20 as shown in FIGS. 2 and 3 is used. As shown in FIG. 2, a turntable 22 that is an object supporting portion for placing the silicon wafer 21 is configured to be rotatable around a vertical axis by a drive mechanism (not shown). Further, on the upper side of the turntable 22, as shown in FIG. 3, the grinding wheel is pressed against the silicon wafer 21 sucked and mounted on the turntable 22 via the chuck 22a so as to press the ground surface. A grindstone support means 24 for supporting the head 23 is provided. The grindstone support means 24 is configured such that the grindstone 23 can be rotated around a vertical axis by a drive mechanism (not shown). A water supply nozzle 26 is provided above the silicon wafer to supply grinding water to the surface of the silicon wafer 21 during grinding. In such a grinding apparatus 20, the grinding wheel 23 and the silicon wafer 21 are relatively rotated by each driving mechanism, and water is supplied to a portion of the surface of the silicon wafer 21 that is out of contact with the grinding wheel 23. Grinding water is supplied from the nozzle 26, and the grinding wheel 23 is pressed against the surface of the silicon wafer 21 and ground while cleaning the surface of the silicon wafer 21.

  As a method for flattening the wafer by lapping, a lapping apparatus 30 as shown in FIG. 4 is used. As shown in FIG. 4, first, the carrier plate 31 is engaged with the sun gear 37 and the internal gear 38 of the wrapping device 30, and the silicon wafer 21 is set in the holder of the carrier plate 31. Thereafter, both sides of the silicon wafer 21 are held so as to be sandwiched between the upper surface plate 32 and the lower surface plate 33, the abrasive 36 is supplied from the nozzle 34, and the carrier plate 31 is caused to perform planetary motion by the sun gear 37 and the internal gear 38, At the same time, the upper surface plate 32 and the lower surface plate 33 are rotated in the relative direction to simultaneously wrap both surfaces of the silicon wafer 21. The silicon wafer that has been subjected to the planarization step 13 in this way has improved flatness on the front and back surfaces of the wafer and parallelism of the wafer, is cleaned in the cleaning step, and is sent to the next step.

  Next, returning to FIG. 1, the planarized silicon wafer is immersed in an etching solution to etch the front and back surfaces of the silicon wafer (step 14). The etching solution used here is the above-described etching solution for controlling the surface shape of the silicon wafer of the present invention. In this etching step 14, the work-affected layer introduced by the machining process such as the chamfering step 12 and the flattening step 13 is completely removed by etching. By performing etching using the etching solution for controlling the surface shape of the present invention prepared by adding silica powder, the surface roughness and texture size of the wafer can be controlled. In addition, both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization process is completed can be achieved while reducing the polishing allowance on the front and back surfaces of the wafer in the single-side polishing process. The etching allowance in the etching step 14 is preferably 8 to 10 μm on one side and 16 to 20 μm in terms of the total allowance on the front and back surfaces of the wafer. By setting the etching allowance within the above range, the polishing allowance in the subsequent double-side simultaneous polishing step and single-side polishing step can be greatly reduced. If the etching allowance is less than the lower limit, the wafer surface roughness is not sufficiently reduced, so the load of simultaneous double-side polishing and single-side polishing is large.If the upper limit is exceeded, the wafer flatness is impaired and the productivity in wafer manufacturing is reduced. Getting worse.

  In this etching step 14, as shown in FIG. 5, first, a plurality of wafers 41 a are held vertically in a holder 41, and the holder 41 is lowered as shown by a solid line arrow in FIG. It is immersed in the stored etching solution 42a for controlling the surface shape of the present invention, and the work-affected layer on the wafer surface is removed with the etching solution. Subsequently, the holder 41 holding the wafer 41a soaked in the etching solution 42a for a predetermined time is pulled up as shown by a broken line arrow in FIG. Next, the holder 41 holding the etched wafer 41a is lowered as shown by the solid line arrow in FIG. The adhering etching solution is removed. Subsequently, the holder 41 holding the wafer 41a immersed in the rinsing liquid 43a for a predetermined time is pulled up as indicated by the broken line arrow in FIG. 5, and the silicon wafer is dried.

Next, referring back to FIG. 1, double-sided simultaneous polishing is performed to simultaneously polish the front and back surfaces of the wafer after the etching step 14 (step 16).
The double-side simultaneous polishing method is performed by a double-sided simultaneous polishing apparatus 50 as shown in FIG. As shown in FIG. 6, first, the carrier plate 51 is engaged with the sun gear 57 and the internal gear 58 of the double-sided simultaneous polishing apparatus 50, and the silicon wafer 21 is set in the holder of the carrier plate 51. Thereafter, both sides of the silicon wafer 21 are held so as to be sandwiched between an upper surface plate 52 having a first polishing cloth 52a attached to the polishing surface side and a lower surface plate 53 having a second polishing cloth 53a attached to the polishing surface side. Then, while supplying the polishing agent 56 from the nozzle 54, the carrier plate 51 is caused to undergo planetary movement by the sun gear 57 and the internal gear 58, and at the same time, the upper surface plate 52 and the lower surface plate 53 are rotated in relative directions, thereby Mirror-polished both sides at the same time. Further, in the double-sided simultaneous polishing step 16, the front and back surfaces of the silicon wafer are simultaneously polished while controlling the rotation speeds of the upper surface plate 52 and the lower surface plate 53, so that the front and back surfaces of the wafer can be visually identified. A wafer can be obtained. Thus, by performing the silicon wafer manufacturing method of the present invention, productivity in wafer manufacturing is greatly improved.

  In this embodiment, the front and back surfaces of the wafer are simultaneously polished by double-sided simultaneous polishing, but the same effect can be obtained by polishing the wafer by single-sided polishing in which the front and back surfaces of the wafer are polished one by one instead of this double-sided simultaneous polishing. It goes without saying that can be obtained.

Next, examples of the present invention will be described in detail together with comparative examples.
<Examples 1-5>
First, a plurality of φ200 mm silicon wafers were prepared, and as a planarization step, lapping was performed on the front and back surfaces of the silicon wafer using a lapping apparatus shown in FIG. The lapping process uses an abrasive containing # 1500 Al ₂ O ₃ as the abrasive, the supplied abrasive flow rate is 2.0 L / min, the upper platen load is 70 g / cm ² , and the upper platen The silicon wafer was planarized while controlling the rotation speed to 10 rpm and the lower platen rotation speed to 40 rpm. Next, as an etching process, the silicon wafer that had been planarized was etched using the etching apparatus shown in FIG. As an etching solution, C ₈ F ₁₇ SO ₃ K (manufactured by Mitsubishi Materials Corporation, trade name: EFTOP EF-102) as a surfactant in 50 wt% sodium hydroxide is 15 g / L (1: 100) with respect to sodium hydroxide. ), 1.5 g / L (1: 1000), 0.15 g / L (1: 10000), 0.015 g / L (1: 100,000) and 0.0015 g / L (1: 1000000). Five types of etching solutions prepared in this way were used. In this etching process, the silicon wafer was immersed in an etching solution for 15 minutes for etching. The etching allowance in this etching was 10 μm on one side of the wafer and 20 μm on both sides of the wafer.

<Examples 6 to 10>
A planarization step and an etching step were performed in the same manner as in Examples 1 to 5 except that the alkaline aqueous solution used for the etching solution in the etching step was replaced with a 40 wt% aqueous sodium hydroxide solution.

<Comparative Examples 1-5>
Five types of chemical solutions consisting only of a 50 wt% sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 1 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no fluorine-based surfactant was added to the etching solution.
<Comparative Examples 6 to 10>
Five types of chemical solutions consisting only of a 40 wt% sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 1 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no silica powder was added to the etching solution.

<Examples 11 to 20>
Etching is performed except that the silicon wafer is immersed in the etching solution for 3.5 to 4.5 minutes in the etching process, and the etching allowance in this etching is 2.5 μm on one side of the wafer and 5 μm on both sides of the wafer. The planarization process and the etching process were performed like Example 1-10.

<Comparison test 1>
With respect to the silicon wafers obtained in Examples 1 to 20 and Comparative Examples 1 to 10, the wafer surface roughness was measured using a non-contact surface roughness meter (manufactured by Chapman), and the basic parameters of the wafer surface properties Ra and Rmax were determined respectively. The arithmetic average roughness Ra, which is an amplitude average parameter in the height direction, is expressed as Z in the reference length as shown in the following formula (1) when the reference length is lr on the wafer surface shown in FIG. Expressed as the average of the absolute values of (x).

Further, the maximum cross-sectional height Rmax of the roughness curve, which is a peak / valley parameter in the height direction, is the contour curve at the evaluation length ln on the wafer surface shown in FIG. The maximum value of the peak height Zp and the maximum value of the valley depth Zv are represented by the sum. In FIG. 8, the maximum value of the peak height Zp is Zp ₂ , and the maximum value of the valley depth Zv is Zv ₄ .

Tables 1 and 2 show the results of Ra and Rmax for the silicon wafers obtained in Examples 1 to 20 and Comparative Examples 1 to 10, respectively.

  As is clear from Table 1, when Examples 1 to 10 in which a fluorinated surfactant was added to an alkaline aqueous solution and Comparative Examples 1 to 10 in which no fluorinated surfactant was added to an alkaline aqueous solution were compared, the results were the same. It can be seen that the results of Ra and Rmax of Examples 1 to 20 are lowered between the wafers subjected to the planarization treatment under the conditions. From this result, the wafer surface roughness and wafer flatness are improved by using an etching solution in which a fluorosurfactant is added to an alkaline aqueous solution, and the polishing allowance in the subsequent double-side simultaneous polishing process can be greatly reduced. was gotten. Moreover, when the results of Examples 1 to 10 were compared, there was a tendency for the results of Ra and Rmax to decrease as the amount of the fluorosurfactant added to the alkaline aqueous solution increased.

  As is clear from Table 2, when the results of Examples 11 to 20 are compared, unlike Table 1 described above, when the removal allowance by etching is as small as 5 μm, the addition amount of the fluorosurfactant added to the alkaline aqueous solution It was found that the lower the value, the lower the Ra and Rmax results.

<Examples 21 to 25>
First, a plurality of φ200 mm silicon wafers were prepared, and lapping was performed on the front and back surfaces of the silicon wafer as in Example 1 as a planarization step. Next, finish grinding was performed on the surface of the silicon wafer using the grinding apparatus shown in FIGS. Grinding conditions are # 2000 for grinding wheel count, 3-4 μm for diamond distribution center particle size, 4800 rpm for spindle (wheel) rotation, 0.3 μm / sec for feed speed, 20 rpm for wafer (wafer chuck) rotation, The machining allowance was 10 μm or less. Next, as an etching process, the silicon wafer that had been planarized was etched using the etching apparatus shown in FIG. As an etching solution, C ₈ F ₁₇ SO ₃ K (manufactured by Mitsubishi Materials Corporation, trade name: EFTOP EF-102) as a surfactant in 50 wt% sodium hydroxide is 15 g / L (1: 100) with respect to sodium hydroxide. ), 1.5 g / L (1: 1000), 0.15 g / L (1: 10000), 0.015 g / L (1: 100,000) and 0.0015 g / L (1: 1000000). Five types of etching solutions prepared in this way were used. In this etching process, the silicon wafer was immersed in an etching solution for 15 minutes for etching. The etching allowance in this etching was 10 μm on one side of the wafer and 20 μm on both sides of the wafer.

<Examples 26 to 30>
The planarization step and the etching step were performed in the same manner as in Examples 21 to 25 except that the alkaline aqueous solution used for the etching solution in the etching step was replaced with a 40 wt% sodium hydroxide aqueous solution.
<Examples 31-35>
A planarization step and an etching step were performed in the same manner as in Examples 21 to 25 except that the alkaline aqueous solution used for the etching solution in the etching step was replaced with a 30 wt% sodium hydroxide aqueous solution.
<Examples 36 to 40>
A planarization step and an etching step were performed in the same manner as in Examples 21 to 25 except that the alkaline aqueous solution used for the etching solution in the etching step was replaced with a 20 wt% aqueous sodium hydroxide solution.

<Comparative Examples 11-15>
Five types of chemical solutions consisting only of a 50 wt% sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 21 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no fluorine-based surfactant was added to the etching solution.
<Comparative Examples 16-20>
Five types of chemical solutions consisting only of a 40 wt% sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 21 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no silica powder was added to the etching solution.
<Comparative Examples 21-25>
Five types of chemical solutions consisting only of a 30% by weight sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 21 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no fluorine-based surfactant was added to the etching solution.
<Comparative Examples 26-30>
Five types of chemical solutions consisting only of a 20 wt% sodium hydroxide aqueous solution were prepared as an alkaline aqueous solution, and the planarization step and the etching step were performed in the same manner as in Example 21 except that this chemical solution was directly used as an etching solution in the etching step. . That is, no silica powder was added to the etching solution.

<Examples 41 to 60>
Etching is performed except that the silicon wafer is immersed in the etching solution for 3.5 to 4.5 minutes in the etching process, and the etching allowance in this etching is 2.5 μm on one side of the wafer and 5 μm on both sides of the wafer. A planarization step and an etching step were performed in the same manner as in Examples 21 to 40.

<Comparison test 2>
For the silicon wafers obtained in Examples 21 to 60 and Comparative Examples 11 to 30, respectively, the wafer surface roughness was measured using a non-contact surface roughness meter (manufactured by Chapman) in the same manner as in Comparative Test 1 above. Then, Ra and Rmax, which are basic parameters of the wafer surface properties, were obtained. Tables 3 to 5 show the results of Ra and Rmax in the silicon wafers obtained in Examples 21 to 60 and Comparative Examples 11 to 30, respectively.

  As is clear from Tables 3 to 4, Examples 21 to 40 in which a fluorinated surfactant was added to an alkaline aqueous solution and Comparative Examples 11 to 30 in which no fluorinated surfactant was added to an alkaline aqueous solution were compared. Then, it turns out that the result of Ra and Rmax of Examples 21-40 is falling, respectively. From this result, the wafer surface roughness and wafer flatness are improved by using an etching solution in which a fluorosurfactant is added to an alkaline aqueous solution, and the polishing allowance in the subsequent double-side simultaneous polishing process can be greatly reduced. was gotten. Moreover, when the results of Examples 21 to 40 were compared, there was a tendency for the results of Ra and Rmax to decrease as the amount of the fluorosurfactant added to the alkaline aqueous solution increased.

  As is apparent from Table 5, when the results of Examples 41 to 60 are compared, unlike Table 3 described above, the amount of fluorine-based surfactant added to the alkaline aqueous solution when the machining allowance by etching is as small as 5 μm. It was found that the lower the value, the lower the Ra and Rmax results.

Process drawing which shows the manufacturing method of the silicon wafer of this invention. The top view of a grinding device. The longitudinal cross-sectional view of a grinding device. The block diagram of a wrapping apparatus. The figure which shows an etching process process. The block diagram of a double-sided simultaneous polishing apparatus. The wafer sectional view for explaining how to obtain Ra. The wafer sectional view for explaining how to obtain Rmax.

Explanation of symbols

13 Planarization process 14 Etching process 16 Double-sided simultaneous polishing process

Claims (4)

  An etching solution for controlling the shape of a surface of a silicon wafer, wherein a fluorine-based surfactant is uniformly mixed in an alkaline aqueous solution. The alkaline aqueous solution is a 20-50 wt% aqueous sodium hydroxide solution,
The etching solution according to claim 1, wherein the addition ratio of the fluorosurfactant added to the alkaline aqueous solution is 0.0015 to 15 g / L with respect to sodium hydroxide. A planarization step of grinding or lapping the front and back surfaces of a thin disc-shaped silicon wafer obtained by slicing a silicon single crystal ingot;
An etching step of immersing a silicon wafer in the etching solution according to claim 1 or 2 to etch the front and back surfaces of the silicon wafer;
And a double-sided simultaneous polishing step of simultaneously polishing the front and back surfaces of the etched silicon wafer in this order. A planarization step of grinding or lapping the front and back surfaces of a thin disc-shaped silicon wafer obtained by slicing a silicon single crystal ingot;
An etching step of immersing a silicon wafer in the etching solution according to claim 1 or 2 to etch the front and back surfaces of the silicon wafer;
And a single-side polishing step of polishing the front and back surfaces of the etched silicon wafer one by one in this order.

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