JP2006210398A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of a high-reliability circuit operation by suppressing electric charges to be discharged from a holding node via the parasitic capacitance of fuse wirings. <P>SOLUTION: The semiconductor integrated circuit has an internal circuit 200, a fuse circuit 20 for setting the circuit operation of the internal circuit 200, and a protective capacitance 30 to be coupled capacitively to the parasitic capacitance C1 of the fuse circuit 20. This semiconductor integrated circuit is provided with a latching circuit 10 for holding a signal FINT to be made to propagate to the internal circuit 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a latch circuit with a fuse (hereinafter simply referred to as a “latch circuit”) connected to a fuse circuit.

  Based on the test results in the wafer state after manufacturing the product of the semiconductor integrated circuit, the output of the latch circuit is changed by cutting the fuse, the redundancy replacement to replace the defective memory cell with the spare memory cell, and the circuit operation change. May do. Therefore, a latch circuit to which a fuse circuit is connected is used in a redundancy circuit or an optional fuse circuit in a semiconductor integrated circuit.

In recent years, with the miniaturization of semiconductor integrated circuits and the reduction in chip size, double density structure fuses have been employed (see, for example, Patent Document 1). In a latch circuit to which a fuse circuit using a double density structure fuse is connected, a diffused resistor is used for wiring from the fuse to the transistor of the latch circuit (hereinafter referred to as “fuse wiring”). The diffusion resistance has a larger parasitic capacitance than a metal wiring such as an aluminum (Al) film. When the fuse is cut, capacitive coupling occurs between the parasitic capacitance of the fuse wiring and the parasitic capacitance of a node in the latch circuit (hereinafter referred to as “holding node”) in which a signal is held. When the capacitance value of the parasitic capacitance of the fuse wiring is larger than the capacitance value of the parasitic capacitance of the holding node, the electric charge may be discharged from the holding node through the parasitic capacitance of the fuse wiring. As a result, the signal held in the latch circuit changes and the latch circuit malfunctions. That is, when the parasitic capacitance of the fuse wiring is large, the reliability of the circuit operation of the latch circuit to which the fuse circuit is connected is lowered.
JP 2001-265831 A

  The present invention provides a semiconductor integrated circuit capable of suppressing a charge discharged from a holding node through a parasitic capacitance of a fuse wiring and performing a highly reliable circuit operation.

  The first feature of the present invention includes (a) an internal circuit, (b) a fuse circuit that sets the circuit operation of the internal circuit, and (c) a protective capacitor that is capacitively coupled to the parasitic capacitance of the fuse circuit. The gist of the invention is a semiconductor integrated circuit including a latch circuit that holds a signal propagated to the circuit.

  The second feature of the present invention is (a) an internal circuit, (b) a fuse circuit for setting the circuit operation of the internal circuit, (c) a first input transistor, and a second input transistor connected to the fuse circuit. And a latch circuit having a lead resistor connected between the first input transistor and the second input transistor, and a signal propagated to the internal circuit to a holding node to which the first input transistor and the lead resistor are connected The gist of the present invention is that it is a semiconductor integrated circuit in which is held.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of suppressing a charge discharged from a holding node through a parasitic capacitance of a fuse wiring and performing a highly reliable circuit operation.

  Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the following first and second embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is a component part. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, the semiconductor integrated circuit according to the first embodiment of the present invention includes an internal circuit 200, a fuse circuit 20 for setting the circuit operation of the internal circuit 200, and a parasitic capacitance C1 of the fuse circuit 20. The latch circuit 10 includes a protection capacitor 30 that is capacitively coupled and holds a holding signal FINT propagated to the internal circuit 200. The protection capacitor 30 is connected between the holding node N of the latch circuit 10 that holds the holding signal FINT and the low potential power supply VSS. As the protection capacitor 30, a gate capacitance of a MOS transistor, a capacitance between wirings, a diffusion capacitance, or the like can be employed.

  The latch circuit 10 includes a first input transistor Q1, a second input transistor Q2, a first holding transistor Q3, a third input transistor Q4, a second holding transistor Q5, a first inverter circuit I1, and a second inverter circuit I2.

  The first input signal bFPUP is input to the first input transistor Q1. The second input signal FPUN is input to the second input transistor Q2. The first input transistor Q1 is a p-channel MOS (hereinafter referred to as “pMOS”) transistor. The first input transistor Q1 has a gate terminal connected to the first input terminal 101, a drain terminal connected to the drain terminal of the second input transistor Q2, and a source terminal connected to the high potential power supply VCC. On the other hand, the second input transistor Q2 is an n-channel MOS (hereinafter referred to as “nMOS”) transistor. In the second input transistor Q2, the second input terminal 102 is connected to the gate terminal, and the fuse circuit 20 is connected to the source terminal. The drain terminal of the first input transistor Q1 and the drain terminal of the second input transistor Q2 are connected to the holding node N. The first holding transistor Q3 is a pMOS transistor, and the third input transistor Q4 and the second holding transistor Q5 are nMOS transistors.

  The input terminal of the first inverter circuit I1 is connected to the holding node N, and the first output terminal 111 is connected to the output terminal. The input terminal of the first inverter circuit I1 is connected to the input terminal of the second inverter circuit I2, and the second output terminal 112 is connected to the output terminal. An output signal bFRBLOWN is output from the first inverter circuit I1. An inverted output signal FRBLOWN of the output signal bFRBLOWN is output from the second inverter circuit I2. The output signal bFRBLOWN is output to the internal circuit 200 via the first output terminal 111. The inverted output signal FRBLOWN is output to the internal circuit 200 via the second output terminal 112. That is, the holding signal FINT is propagated to the internal circuit 200 via the first inverter circuit I1 and the second inverter circuit I2.

  The gate terminal of the first holding transistor Q3 and the gate terminal of the second holding transistor Q5 are connected to the output terminal of the first inverter circuit I1. The first holding transistor Q3 has a drain terminal connected to the drain terminal of the third input transistor Q4 and a source terminal connected to the high potential power supply VCC. The second holding transistor Q5 has a drain terminal connected to the source terminal of the third input transistor Q4, and a source terminal connected to the low potential power supply VSS. The third input transistor Q4 has a gate terminal connected to the first input terminal 101.

  The fuse circuit 20 includes a fuse F1 connected to the low potential power supply VSS, and a fuse wiring connecting the fuse F1 and the source terminal of the second input transistor Q2. In FIG. 1, the resistance of the fuse wiring is shown as a fuse resistance R1. The parasitic capacitance C1 of the fuse wiring shown in FIG. 1 is a parasitic capacitance between the fuse wiring and the low potential power supply VSS.

  The internal circuit 200 is a semiconductor logic circuit or a semiconductor memory device. For example, when the internal circuit 200 is a semiconductor memory device, the memory cell to be accessed can be switched in the memory cell array of the semiconductor memory device by setting the levels of the output signal bFRBLOWN and the inverted output signal FRBLOWN. As a result, it is possible to replace a defective memory cell with a spare memory cell among the memory cells of the memory cell array.

  Next, the operation of the latch circuit 10 shown in FIG. 1 will be described. First, the case where the fuse F1 is not cut will be described with reference to the timing chart shown in FIG. In the following description, the high level of the first input signal bFPUP and the second input signal FPUN input to the latch circuit 10 is set to the potential VH of the high potential power supply VCC, and the first input signal bFPUP and the second input signal. The low level of FPUN is set to the potential VL of the low potential power supply VSS. The high level of the output signal bFRBLOWN and the inverted output signal FRBLOWN is the potential VH, and the low level of the output signal bFRBLOWN and the inverted output signal FRBLOWN is the potential VL. In the initial state of the timing chart of FIG. 2, the high-level first input signal bFPUP is input to the first input transistor Q1, and the first input transistor Q1 is off. Further, the low-level second input signal FPUN is input to the second input transistor Q2, and the second input transistor Q2 is turned off. Therefore, the holding signal FINT of the latch circuit 10 is indefinite, but FIG. 2 shows the case where the holding signal FINT is at a low level. The same applies to other timing charts.

  (A) At time t1, the low-level first input signal bFPUP is input to the first input transistor Q1, and the first input transistor Q1 is turned on. On the other hand, since the second input signal FPUN is at a low level, the second input transistor Q2 is off. Therefore, the holding signal FINT becomes a high level. On the other hand, the third input transistor Q4 to which the low-level first input signal bFPUP is input is turned off. As a result, there is no discharge of charge from the holding node N to the low potential power supply VSS via the third input transistor Q4 and the second holding transistor Q5. Since the holding signal FINT is at a high level, the output signal bFRBLOWN output from the first inverter circuit I1 is at a low level. Therefore, the first holding transistor Q3 is turned on, and the holding signal FINT is maintained at a high level. Further, the inverted output signal FRBLOWN output from the second inverter circuit I2 becomes high level.

  (B) At time t2, the first input signal bFPUP becomes high level, and the first input transistor Q1 is turned off. However, since the first holding transistor Q3 is on, the holding signal FINT maintains a high level. The third input transistor Q4 is turned on, but the second holding transistor Q5 is turned off. Therefore, no discharge occurs from the holding node N to the low potential power supply VSS. As a result, the output signal bFRBLOWN is maintained at a low level, and the inverted output signal FRBLOWN is maintained at a high level.

  (C) At time t3, the high-level second input signal FPUN is input to the second input transistor Q2, and the second input transistor Q2 is turned on. Then, charges are discharged from the holding node N to the low potential power supply VSS through the second input transistor Q2, the fuse resistor R1, and the fuse F1. Therefore, the holding signal FINT changes to a low level. As a result, the output signal bFRBLOWN of the first inverter circuit I1 becomes high level, the first holding transistor Q3 is turned off and the second holding transistor Q5 is turned on. That is, since the third input transistor Q4 and the second holding transistor Q5 are turned on, the holding signal FINT maintains a low level. The inverted output signal FRBLOWN becomes low level.

  (D) At time t4, the second input signal FPUN becomes low level, and the second input transistor Q2 is turned off. However, since the third input transistor Q4 and the second holding transistor Q5 are on, the holding signal FINT maintains a low level.

  With the above circuit operation, the output signal bFRBLOWN of the latch circuit 10 is fixed at the high level and the inverted output signal FRBLOWN is determined at the low level. The levels of the output signal bFRBLOWN and the inverted output signal FRBLOWN of the latch circuit 10 are maintained as long as the first input signal bFPUP and the second input signal FPUN do not change.

  Next, the operation of the latch circuit 10 when the fuse F1 is cut will be described with reference to the timing chart shown in FIG.

  (A) From time t1 to time t2, the latch circuit 10 operates in the same manner as described with reference to the timing chart of FIG. As a result, the holding signal FINT is at a high level at time t2. The output signal bFRBLOWN is at a low level, and the inverted output signal FRBLOWN is at a high level.

  (B) At time t3, the high-level second input signal FPUN is input to the second input transistor Q2, and the second input transistor Q2 is turned on. However, since the fuse F1 is cut, no electric charge is discharged from the holding node N to the low potential power supply VSS via the second input transistor Q2 and the fuse circuit 20. For this reason, the holding signal FINT maintains a high level. The output signal bFRBLOWN is maintained at a low level, and the inverted output signal FRBLOWN is maintained at a high level. However, as will be described later, when the protection capacitor 30 is not connected to the holding node N, charge may be discharged from the holding node N to the low potential power supply VSS via the parasitic capacitance C1 of the fuse wiring. .

  (C) At time t4, the second input signal FPUN becomes low level, and the second input transistor Q2 is turned off. The holding signal FINT maintains a high level.

  With the above circuit operation, the output signal bFRBLOWN of the latch circuit 10 is fixed at a low level and the inverted output signal FRBLOWN is determined at a high level. The levels of the output signal bFRBLOWN and the inverted output signal FRBLOWN of the latch circuit 10 are maintained as long as the first input signal bFPUP and the second input signal FPUN do not change.

  As described above, the circuit operation of the latch circuit 10 changes depending on whether or not the fuse F1 is cut. That is, by cutting the fuse F1, the levels of the output signal bFRBLOWN and the inverted output signal FRBLOWN of the latch circuit 10 can be set.

  Next, the operation of the latch circuit 100 in which the protection capacitor 30 illustrated in FIG. 5 is not connected to the holding node N will be described. In the following description, the influence of the parasitic capacitance C1 of the fuse wiring on the latch circuit 100 when the fuse F1 is cut will be described with reference to the timing chart of FIG.

  (A) From time t1 to time t2, the latch circuit 100 operates as in the case described with reference to the timing chart of FIG. As a result, the holding signal FINT is at a high level at time t2. The output signal bFRBLOWN is at a low level, and the inverted output signal FRBLOWN is at a high level.

  (B) At time t3, the high-level second input signal FPUN is input to the second input transistor Q2, and the second input transistor Q2 is turned on. The holding node N includes a parasitic capacitance of a wiring connected to the holding node N, a drain capacitance of the first input transistor Q1, a drain capacitance of the second input transistor Q2, a drain capacitance of the first holding transistor Q3, and a third input transistor Q4. There is a holding node parasitic capacitance composed of the drain capacitance of the first inverter circuit I1 and the input capacitance of the first inverter circuit I1. Therefore, when the second input transistor Q2 is turned on, capacitive coupling between the holding node parasitic capacitance and the parasitic capacitance C1 of the fuse wiring occurs. Until the second input transistor Q2 is turned on, the parasitic capacitance C1 of the fuse wiring is charged by the low potential power supply VSS. Therefore, when the second input transistor Q2 is turned on, a discharge current Idis flows from the holding node N to the parasitic capacitance C1 of the fuse wiring as shown in FIG. Here, the discharge current Idis increases as the capacitance value of the parasitic capacitance C1 of the fuse wiring is larger than the capacitance value of the holding node parasitic capacitance. For example, when the capacitance value of the parasitic capacitance C1 of the fuse wiring is about five times or more the capacitance value of the holding node parasitic capacitance, the discharge current Idis is supplied from the high potential power supply VCC via the first holding transistor Q3. It becomes larger than the latch current Ichg flowing through the holding node N. When discharge current Idis is larger than latch current Ichg, the level of holding node N decreases. When the level of the holding signal FINT becomes equal to or lower than the circuit threshold value of the first inverter circuit I1, the output signal bFRBLOWN changes to a high level. As a result, the first holding transistor Q3 is turned off and the second holding transistor Q5 is turned on, so that the holding signal FINT is at a low level. Further, the inverted output signal FRBLOWN becomes low level. In FIG. 4, the originally expected levels of the holding signal FINT, the output signal bFRBLOWN, and the inverted output signal FRBLOWN are indicated by dotted lines.

  (C) At time t4, the second input signal FPUN becomes low level, and the second input transistor Q2 is turned off. However, since the first holding transistor Q3 is off and the second holding transistor Q5 is on, the holding signal FINT maintains a low level. Therefore, the output signal bFRBLOWN is maintained at a high level, and the inverted output signal FRBLOWN is maintained at a low level.

  With the above circuit operation, the output signal bFRBLOWN of the latch circuit 100 is determined to be high level and the inverted output signal FRBLOWN is determined to be low level. The levels of the output signal bFRBLOWN and the inverted output signal FRBLOWN of the latch circuit 100 are maintained as long as the first input signal bFPUP and the second input signal FPUN do not change.

  That is, there is a case where the latch circuit 100 in which the protection capacitor 30 is not connected to the holding node N malfunctions and the output signal bFRBLOWN and the inverted output signal FRBLOWN do not reach the desired levels. On the other hand, as shown in FIG. 1, in the case of the latch circuit 10 in which the protection capacitor 30 is connected to the holding node N, the sum of the capacitance value of the protection capacitor 30 and the capacitance value of the holding node parasitic capacitance is the parasitic capacitance C1 of the fuse wiring. By setting the capacitance value or more, the discharge current Idis can be made equal to or less than the latch current Ichg. As a result, malfunction of the latch circuit 10 can be prevented.

  As described above, according to the semiconductor integrated circuit according to the first embodiment of the present invention, even if the capacitance value of the parasitic capacitance C1 of the fuse wiring is large, it depends on the capacitance value of the parasitic capacitance C1 of the fuse wiring. By connecting the protective capacitor 30 to the holding node, malfunction of the latch circuit 10 can be prevented. That is, the reliability of the circuit operation of the latch circuit 10 is improved.

  FIG. 6 shows an example in which the semiconductor integrated circuit according to the first embodiment of the present invention is applied to a fuse circuit 21 having a double density structure. As shown in FIG. 6, a plurality of latch circuits 100 a, 10 b, 100 c, and 10 d are connected to the fuse circuit 21. For example, the latch circuit 100 shown in FIG. 5 can be employed as the latch circuits 100a and 100c. On the other hand, the latch circuit 10 shown in FIG. 1 is employed as the latch circuits 10b and 10d. The latch circuit 100a is connected to the low potential power supply VSS via the fuse F1a. The latch circuit 10b is connected to the low potential power source VSS via the fuse resistor R1b and the fuse F1b. The latch circuit 100c is connected to the low potential power supply VSS via the fuse F1c. The latch circuit 10d is connected to the low potential power supply VSS through the fuse resistor R1d and the fuse F1d.

  As shown in FIG. 6, the fuse circuit 21 is a fuse circuit having a so-called double density structure including fuses F1a to F1d and fuse resistors R1b and R1d used as fuse wirings. Here, the fuse resistors R1b and R1d are diffused resistors formed in the diffusion layer. A layout example of the fuse circuit 21 shown in FIG. 6 is shown in FIG. FIG. 7 is a top view showing fuse resistors R1b and R1d formed in the diffusion layer through the metal wiring layer where the fuses F1a to F1d are formed. The fuse resistor R1b is connected to the fuse F1b through the via V1. The fuse resistor R1d is connected to the fuse F1d through the via V2. The double density structure is effective when the minimum arrangement interval of the fuses F1a to F1d is larger than the minimum arrangement interval of the latch circuits 100a, 10b, 100c, and 10d. That is, by adopting the double density structure shown in FIG. 7, the length of the fuse circuit 21 in the lateral direction of the paper surface can be made shorter than when the fuses F1a to F1d are arranged in parallel.

  As shown in FIG. 7, no diffused resistor is used for the fuse wiring connecting the fuse F1a and the latch circuit 100a and the fuse wiring connecting the fuse F1c and the latch circuit 100c. That is, the parasitic capacitance of the fuse wiring connected to the latch circuits 100a and 100c is small. Therefore, the latch circuit 100 that does not include the protection capacitor 30 can be employed as the latch circuits 100a and 100c. On the other hand, a fuse resistor R1b exists in the fuse wiring connecting the fuse F1b and the latch circuit 10b. A fuse resistor R1d exists in the fuse wiring connecting the fuse F1d and the latch circuit 10d. As already described, the diffusion resistance has a larger parasitic capacitance than the metal wiring. Therefore, the parasitic capacitance of the fuse wiring connected to the latch circuits 10b and 10d is large. Therefore, as shown in FIG. 6, the latch circuit 10 including the protection capacitor 30 is employed for the latch circuits 10b and 10d.

  As described above, when the double density structure fuse circuit 21 shown in FIG. 6 is used, it is necessary to employ the latch circuit 10 including the protective capacitor 30 in all the latch circuits 100a, 10b, 100c, and 10d. There is no. Therefore, the area of the entire circuit including the latch circuits 100a, 10b, 100c, and 10d can be suppressed.

(Second Embodiment)
As shown in FIG. 8, the semiconductor integrated circuit according to the second embodiment of the present invention includes an internal circuit 200, a fuse circuit 22 for setting the circuit operation of the internal circuit 200, a first input transistor Q1, and a fuse. And a latch circuit 11 having a second input transistor Q2 connected to the circuit 22 and a lead-out resistor R2 connected between the first input transistor Q1 and the second input transistor Q2. The first input transistor Q1 and the lead-out The holding signal FINT propagated to the internal circuit 200 is held at the holding node N to which the resistor R2 is connected. The latch circuit 11 is different from that of FIG. 1 in that the lead-out resistor R2 is connected between the first input transistor Q1 and the second input transistor Q2, and the protection capacitor 30 is not connected to the holding node N. Other configurations are the same as those of the first embodiment shown in FIG.

  The latch circuit 11 includes a first circuit 120 obtained by removing the second input transistor Q2 and the protection capacitor 30 from the latch circuit 10 illustrated in FIG. 1, a second circuit 130 including the second input transistor Q2, and a lead resistor R2. A diffused resistor or the like can be used as the lead resistor R2. The lead-out resistor parasitic capacitance C2 shown in FIG. 8 is a parasitic capacitance between the lead-out resistor R2 and the low potential power supply VSS.

  As shown in FIG. 8, the fuse circuit 22 includes a fuse F1, and the fuse F1 is connected between the source terminal of the second input transistor Q2 and the low potential power supply VSS.

  According to the latch circuit 11 shown in FIG. 8, when the holding signal FINT becomes high level while the fuse F1 is cut, the lead-out resistor parasitic capacitance C2 is charged at high level. Therefore, when the second input transistor Q2 is turned on at time t3 in the timing chart shown in FIG. 4, the discharge current is suppressed from the holding node N to the low potential power supply VSS via the lead-out resistance parasitic capacitance C2. As a result, it is possible to prevent a sudden decrease in the level of the holding signal FINT. That is, it is possible to prevent the level of the holding signal FINT from being equal to or lower than the circuit threshold value of the first inverter circuit I1.

  FIG. 9 shows an example in which a double-density fuse circuit is configured using the latch circuit 11 shown in FIG. The latch circuit 11 shown in FIG. 8 is employed as the latch circuits 11b and 11d shown in FIG. That is, the latch circuit 11b includes the first circuit 120b, the drawing resistor R2b, and the second circuit 130b, and the second circuit 130b is connected to the low potential power supply VSS via the fuse F1b. Similarly, the latch circuit 11d includes a first circuit 120d, a lead resistor R2d, and a second circuit 130d, and the second circuit 130d is connected to the low potential power supply VSS via the fuse F1d.

  On the other hand, the latch circuit 100a is connected to the low potential power supply VSS via the fuse F1a, and the latch circuit 100c is connected to the low potential power supply VSS via the fuse F1c. Diffusion resistors are not used for the fuse wiring connecting the fuse F1a and the latch circuit 100a and the fuse wiring connecting the fuse F1c and the latch circuit 100c. That is, the parasitic capacitance of the fuse wiring connected to the latch circuits 100a and 100c is small. Therefore, for example, the latch circuit 100 shown in FIG. 5 can be employed as the latch circuits 100a and 100c.

  As shown in FIG. 9, by applying the latch circuit 11, a double density structure fuse circuit including fuses F1a to F1d, a drawing resistor R2b, and a drawing resistor R2d is formed.

  According to the semiconductor integrated circuit according to the second embodiment of the present invention, since it is not necessary to connect the protective capacitor 30 to the holding node N, an increase in the area of the entire circuit can be suppressed. Others are substantially the same as those in the first embodiment, and thus redundant description is omitted.

  As described above, the present invention has been described according to the first or second embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art. In other words, the present invention includes various embodiments and the like not described here. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a schematic equivalent circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 6 is a timing chart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention (No. 1); 6 is a timing chart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention (No. 2). 3 is a timing chart for explaining an effect of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a typical equivalent circuit diagram for demonstrating the effect of the semiconductor integrated circuit which concerns on the 1st Embodiment of this invention. 1 is a schematic diagram illustrating a configuration example of a semiconductor integrated circuit and a double density structure fuse circuit according to a first embodiment of the present invention; It is a top view for demonstrating the fuse circuit of a double density structure. FIG. 6 is a schematic equivalent circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. It is a schematic diagram which shows the example of a circuit structure using the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

C1: Parasitic capacitance of fuse wiring C2: Parasitic capacitance of extraction resistor N: Holding node Q1: First input transistor Q2: Second input transistor R1: Fuse resistor R2: Extraction resistor VCC: High potential power supply VSS: Low potential power supply 10, 11 ... Latch circuit 20, 21, 22 ... Fuse circuit 30 ... Protection capacitor 200 ... Internal circuit

Claims (5)

Internal circuitry,
A fuse circuit for setting the circuit operation of the internal circuit;
A semiconductor integrated circuit, comprising: a protection capacitor that is capacitively coupled to a parasitic capacitance of the fuse circuit, and a latch circuit that holds a signal propagated to the internal circuit.   The semiconductor integrated circuit according to claim 1, wherein the protection capacitor is connected to a holding node of the latch circuit that holds a signal propagated to the internal circuit.   The semiconductor integrated circuit according to claim 1, wherein the fuse circuit includes a diffused resistor. Internal circuitry,
A fuse circuit for setting the circuit operation of the internal circuit;
A latch circuit comprising: a first input transistor; a second input transistor connected to the fuse circuit; and a lead resistor connected between the first input transistor and the second input transistor. A semiconductor integrated circuit, wherein a signal propagated to the internal circuit is held in a holding node to which an input transistor and the drawing resistor are connected.   The semiconductor integrated circuit according to claim 4, wherein the lead-out resistor is a diffused resistor.

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