JP2006202996A - Mounting structure of semiconductor chip and its mounting method - Google Patents

Mounting structure of semiconductor chip and its mounting method Download PDF

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Publication number
JP2006202996A
JP2006202996A JP2005013334A JP2005013334A JP2006202996A JP 2006202996 A JP2006202996 A JP 2006202996A JP 2005013334 A JP2005013334 A JP 2005013334A JP 2005013334 A JP2005013334 A JP 2005013334A JP 2006202996 A JP2006202996 A JP 2006202996A
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semiconductor chip
mounting substrate
mounting
adhesive
mounting structure
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JP4654695B2 (en
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Yoshiharu Sanagawa
佳治 佐名川
Toshihiko Takahata
利彦 高畑
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the mounting structure of a semiconductor chip capable of firmly fixing the semiconductor chip and capable of reducing the effect of a stress due to a temperature change, and to provide a mounting method for the mounting structure. <P>SOLUTION: In the mounting structure of the semiconductor chip, an adhesive 4 composed of a high elastic material such as an epoxy resin is used for joining the semiconductor chip 1 such as an Si chip, an IC chip or the like; and a mounting substrate 2 in which an electrode as a thin-film composed of gold, nickel, copper or the like is formed on one surface of an insulating substrate 20 formed of ceramics, a resin or the like. In the mounting structure, the semiconductor chip 1 is mounted on the mounting substrate 2 by joining one-side side of the semiconductor chip 1 with the mounting substrate 2 by the adhesive 4 composed of the high elastic material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、実装基板への半導体チップの実装構造、及びその実装方法に関するものである。   The present invention relates to a mounting structure of a semiconductor chip on a mounting substrate and a mounting method thereof.

従来の半導体チップの実装構造としては、半導体チップの一辺側を金ワイヤ等から形成したバンプを用いて実装基板に接合することで、半導体チップを実装基板に片持ち保持させたものが提供されている。   As a conventional semiconductor chip mounting structure, a semiconductor chip is cantilevered on a mounting substrate by bonding one side of the semiconductor chip to a mounting substrate using a bump formed from a gold wire or the like. Yes.

また、半導体チップの一辺側を上記のようなバンプにより保持するとともに、半導体チップの他辺側をダミーバンプ（特許文献１）や、絶縁性接着剤（特許文献２）で保持することで、半導体チップを実装基板に両持ち保持させたものが提供されている。
特開平８−２９８４２４号公報（第１図） 特開平９−９３０７３号公報（第１図） Further, while holding one side of the semiconductor chip with the bumps as described above, the other side of the semiconductor chip is held with a dummy bump (Patent Document 1) or an insulating adhesive (Patent Document 2). Is provided in which both are held on a mounting board.
JP-A-8-298424 (FIG. 1) JP-A-9-93073 (FIG. 1)

ところで、このような半導体チップと実装基板とはそれぞれ線膨張率が異なるものであるから、温度変化が生じた際には、実装基板に接合された半導体チップは、強制的に実装基板と同一の伸び縮みをさせられることになる。つまり、線膨張率の違いによって実装基板と半導体チップとの間には半導体チップを強制的に伸縮させる応力（界面応力）が生じ、これにより、半導体チップが破壊されるおそれがあった。   By the way, since such a semiconductor chip and a mounting substrate have different linear expansion coefficients, when a temperature change occurs, the semiconductor chip bonded to the mounting substrate is forcibly the same as the mounting substrate. It will be able to stretch. That is, a stress (interface stress) that forcibly expands and contracts the semiconductor chip is generated between the mounting substrate and the semiconductor chip due to a difference in linear expansion coefficient, which may cause the semiconductor chip to be destroyed.

これに対して上記の前者は、半導体チップを実装基板にバンプにより片持ち保持しているので、このような応力の影響を低減できるものであったが、片持ち保持であるために半導体チップの固定強度が弱く、半導体チップが傾いたりしてその動作に悪影響を及ぼすおそれがあった。一方、上記の後者（特許文献１，２）は、バンプとダミーバンプ（或いは絶縁性接着剤）とによって半導体チップを実装基板に両持ち保持しているので、半導体チップの固定強度は確保できていたが、実装基板の伸縮にともなってバンプとダミーバンプ（或いは絶縁性接着剤）との間の距離が伸縮するため、半導体チップにかかる応力の影響を低減できず、半導体チップの破損や、接合外れ等が生じるおそれがあった。   On the other hand, in the former, since the semiconductor chip is cantilevered by the bumps on the mounting substrate, the influence of such stress can be reduced. The fixing strength is weak, and the semiconductor chip may be tilted, which may adversely affect its operation. On the other hand, since the latter (Patent Documents 1 and 2) holds the semiconductor chip on both sides of the mounting substrate by the bump and the dummy bump (or insulating adhesive), the fixing strength of the semiconductor chip can be secured. However, since the distance between the bump and the dummy bump (or insulating adhesive) expands and contracts with the expansion and contraction of the mounting substrate, the effect of stress on the semiconductor chip cannot be reduced, and the semiconductor chip is damaged or disconnected. Could occur.

つまり、従来の半導体チップの実装構造では、半導体チップの固定強度の向上と、温度変化による応力の影響の低減とを同時に解決することができなかった。   That is, in the conventional semiconductor chip mounting structure, it has been impossible to simultaneously solve the improvement of the fixing strength of the semiconductor chip and the reduction of the influence of the stress due to the temperature change.

本発明は上述の点に鑑みて為されたもので、その目的は、半導体チップを強固に固定でき、かつ温度変化による応力の影響を低減できる半導体チップの実装構造、及びその実装方法を提供することである。   The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor chip mounting structure that can firmly fix a semiconductor chip and reduce the influence of stress due to temperature change, and a mounting method thereof. That is.

上記の課題を解決するために、請求項１の半導体チップの実装構造では、半導体チップと、該半導体チップの一辺側を高弾性材料の接着剤により接合する実装基板とからなることを特徴とする。   In order to solve the above-described problems, the semiconductor chip mounting structure according to claim 1 is characterized by comprising a semiconductor chip and a mounting substrate for joining one side of the semiconductor chip with an adhesive of a highly elastic material. .

請求項１の発明によれば、半導体チップを実装基板に接合する接着剤として高弾性材料のものを用いているので、従来のように単にバンプのみで接合するものに比べて、半導体チップを実装基板に強固に固定することができる。しかも、温度変化が生じた際に、半導体チップと実装基板の線膨張率の相違によって応力が生じたとしても、半導体チップを一辺側で実装基板に強固に固定しているだけなので、このような応力の影響を低減して、半導体チップの破損等を防止することができる。   According to the first aspect of the present invention, since a highly elastic material is used as an adhesive for bonding the semiconductor chip to the mounting substrate, the semiconductor chip is mounted as compared with the conventional case where the bonding is performed only by bumps. It can be firmly fixed to the substrate. Moreover, even when stress occurs due to the difference in the linear expansion coefficient between the semiconductor chip and the mounting substrate when the temperature change occurs, the semiconductor chip is only firmly fixed to the mounting substrate on one side. It is possible to reduce the influence of the stress and prevent the semiconductor chip from being damaged.

請求項２の半導体チップの実装構造では、請求項１の構成において、半導体チップは、少なくとも他辺側を低弾性材料の接着剤により実装基板に接合されていることを特徴とする。   The semiconductor chip mounting structure according to claim 2 is characterized in that, in the structure according to claim 1, at least the other side of the semiconductor chip is bonded to the mounting substrate with an adhesive of a low elastic material.

請求項２の発明によれば、少なくとも半導体チップの他辺側を低弾性材料の接着剤で実装基板に接合しているので、半導体チップや実装基板に衝撃が加えられたとしても、低弾性材料の接着剤で衝撃を吸収することができ、これにより耐衝撃性が向上する。また、接着剤として低弾性材料のものを使用しているので、半導体チップと実装基板の線膨張率の相違によって応力が生じたとしても、低弾性材料の接着剤が伸びることにより、このような応力による影響を低減することができる。   According to the invention of claim 2, since at least the other side of the semiconductor chip is bonded to the mounting substrate with the adhesive of the low elastic material, even if an impact is applied to the semiconductor chip or the mounting substrate, the low elastic material It is possible to absorb the impact with this adhesive, thereby improving the impact resistance. In addition, since a low elastic material is used as the adhesive, even if stress is generated due to the difference in the coefficient of linear expansion between the semiconductor chip and the mounting substrate, the adhesive of the low elastic material expands, The influence of stress can be reduced.

請求項３の半導体チップの実装構造では、請求項２の構成において、実装基板の低弾性材料の接着剤が接合される部位に、スペーサを設けていることを特徴とする。   The semiconductor chip mounting structure according to claim 3 is characterized in that, in the structure of claim 2, a spacer is provided at a portion of the mounting substrate where the adhesive of the low elastic material is bonded.

請求項３の発明によれば、スペーサによって半導体チップの実装基板に対する傾きを補正して、半導体チップが実装基板に対して略平行となるようにすることができ、これにより半導体チップの平行度を確保することができる。   According to the invention of claim 3, the inclination of the semiconductor chip with respect to the mounting substrate can be corrected by the spacer so that the semiconductor chip is substantially parallel to the mounting substrate. Can be secured.

請求項４の半導体チップの実装構造では、請求項１乃至３のいずれか１項の構成において、半導体チップと実装基板との接合部位を分割していることを特徴とする。   A semiconductor chip mounting structure according to a fourth aspect is characterized in that, in the configuration according to any one of the first to third aspects, a joint portion between the semiconductor chip and the mounting substrate is divided.

請求項４の発明によれば、半導体チップと実装基板との接合部位を分割していることによって、接合部位の接触面積を少なくすることができ、これにより、半導体チップと実装基板の線膨張率の相違によって生じる応力の影響を低減することができる。   According to the invention of claim 4, by dividing the bonding portion between the semiconductor chip and the mounting substrate, the contact area of the bonding portion can be reduced, and thereby the linear expansion coefficient between the semiconductor chip and the mounting substrate. It is possible to reduce the influence of stress caused by the difference between the two.

請求項５の半導体チップの実装方法では、実装基板に、高弾性材料の接着剤、及び低弾性材料の接着剤を塗布する第１の工程と、第１の工程後に半導体チップの一辺側を高弾性材料の接着剤に重複させるとともに、少なくとも他辺側を低弾性材料の接着剤に重複させて、半導体チップを実装基板に配置する第２の工程と、第２の工程後に高弾性材料の接着剤を硬化させて半導体チップの一辺側を実装基板に接合する第３の工程と、第３の工程後に低弾性材料の接着剤を硬化させて半導体チップの少なくとも他辺側を実装基板に接合する第４の工程とを有していることを特徴とする。   According to another aspect of the semiconductor chip mounting method of the present invention, a first step of applying an adhesive of a high elastic material and an adhesive of a low elastic material to the mounting substrate, and raising one side of the semiconductor chip after the first step is performed. A second step of placing the semiconductor chip on the mounting substrate by overlapping the adhesive of the elastic material and at least the other side of the adhesive with the adhesive of the low elastic material; and bonding the high elastic material after the second step A third step of curing the agent to bond one side of the semiconductor chip to the mounting substrate; and after the third step, curing an adhesive of a low elastic material to bond at least the other side of the semiconductor chip to the mounting substrate. And a fourth step.

請求項５の発明によれば、高弾性材料の接着剤と低弾性材料の接着剤をそれぞれに適した条件で硬化させることができるので、両接着剤を一括で硬化させるような場合に比べて、両接着剤による接合強度を向上することができる。また、半導体チップの一辺側を高弾性材料の接着剤で実装基板に接合するとともに、少なくとも半導体チップの他辺側を低弾性材料の接着剤で実装基板に接合しているので、従来のように単にバンプのみで接合するものに比べて、半導体チップを実装基板に強固に固定することができ、加えて半導体チップや実装基板に加えられた衝撃を低弾性材料の接着剤で吸収することができるから、耐衝撃性が向上する。さらに、半導体チップと実装基板の線膨張率の相違によって応力が生じたとしても、低弾性材料の接着剤が伸びることにより、このような応力による影響を低減することができる。   According to the invention of claim 5, since the adhesive of the high elastic material and the adhesive of the low elastic material can be cured under conditions suitable for each, compared to a case where both adhesives are cured at once. The joint strength by both adhesives can be improved. In addition, since one side of the semiconductor chip is bonded to the mounting substrate with an adhesive of a high elastic material, and at least the other side of the semiconductor chip is bonded to the mounting substrate with an adhesive of a low elastic material, The semiconductor chip can be firmly fixed to the mounting substrate as compared with the case where it is bonded only by bumps, and the impact applied to the semiconductor chip and the mounting substrate can be absorbed by the adhesive of the low elastic material. Therefore, the impact resistance is improved. Furthermore, even if stress occurs due to the difference in linear expansion coefficient between the semiconductor chip and the mounting substrate, the influence of such stress can be reduced by extending the adhesive of the low elastic material.

本発明は、半導体チップを実装基板に強固に接合することができ、しかも半導体チップと実装基板の線膨張率の相違による応力の影響を低減して、半導体チップの破損等を防止することができるという効果がある。   The present invention can firmly bond a semiconductor chip to a mounting substrate, and can reduce the influence of stress due to the difference in linear expansion coefficient between the semiconductor chip and the mounting substrate, thereby preventing damage to the semiconductor chip and the like. There is an effect.

（実施形態１）
本実施形態の半導体チップの実装構造は、図１（ａ）に示すように、半導体チップ（ベアチップ）１と、該半導体チップ１の一辺側（図１（ａ）における左辺側）を高弾性材料の接着材４により接合する実装基板２とからなる。 (Embodiment 1)
As shown in FIG. 1A, the semiconductor chip mounting structure of the present embodiment has a semiconductor chip (bare chip) 1 and one side of the semiconductor chip 1 (the left side in FIG. 1A) as a highly elastic material. The mounting substrate 2 is joined by the adhesive 4.

ここで、半導体チップ１は、例えばＳｉチップやＩＣチップ等の平板状の半導体チップであり、このチップ本体１０の一面の一辺側に薄膜の電極１１（図２参照）が形成されている。実装基板２は、例えばセラミックスや樹脂等から平板状に形成された絶縁基板２０の少なくとも一面に、金又はニッケル又は銅等からなる薄膜の電極２１（図２参照）が形成されているものである。また、高弾性材料の接着剤（以下、高弾性接着剤という）４は、例えば、エポキシ系樹脂等の熱硬化性樹脂であり、弾性率が２０００ＭＰａ〜８０００ＭＰａ、線膨張率が３０ｐｐｍ〜７０ｐｐｍであるものが好ましく、本実施形態では、このような高弾性接着剤４として、弾性率が６８００ＭＰａ、線膨張率が３８ｐｐｍ、硬化条件が約２４０℃で５秒であるようなエポキシ系樹脂（松下電工社製のＸＶ５３４０Ｈ（商品名））を用いている。   Here, the semiconductor chip 1 is a flat semiconductor chip such as a Si chip or an IC chip, for example, and a thin film electrode 11 (see FIG. 2) is formed on one side of one surface of the chip body 10. The mounting substrate 2 is such that a thin film electrode 21 (see FIG. 2) made of gold, nickel, copper, or the like is formed on at least one surface of an insulating substrate 20 formed in a flat plate shape from ceramics, resin, or the like. . Moreover, the adhesive (hereinafter, referred to as a highly elastic adhesive) 4 of a highly elastic material is a thermosetting resin such as an epoxy resin, and has an elastic modulus of 2000 MPa to 8000 MPa and a linear expansion coefficient of 30 ppm to 70 ppm. In this embodiment, such a high elastic adhesive 4 is an epoxy resin (Matsushita Electric Works, Ltd.) having an elastic modulus of 6800 MPa, a linear expansion coefficient of 38 ppm, and a curing condition of about 240 ° C. for 5 seconds. Manufactured by XV5340H (trade name).

次に、本実施形態の半導体チップの実装構造を得るための実装方法について説明する。本実施形態の半導体チップの実装方法は、いわゆるフリップチップ実装によるものであり、図２に示すように、第１の工程（Ｉ）〜第３の工程（III）までの３つの工程からなる。   Next, a mounting method for obtaining the semiconductor chip mounting structure of the present embodiment will be described. The semiconductor chip mounting method of this embodiment is based on so-called flip chip mounting, and includes three steps from a first step (I) to a third step (III) as shown in FIG.

第１の工程（Ｉ）は、半導体チップ１の電極１１の表面に、例えば金ワイヤ（９９％以上、望ましくは９９．９９％以上の金を含み、直径がφ２５μｍ程度のもの）を用いてバンプ３を形成するバンプ形成工程（（ａ）で示す）と、実装基板２に形成した電極２１を含む部位に、アンダーフィル材として高弾性接着剤４を、図１（ｂ）に示すように半導体チップ１の一辺の長さ寸法程度の長尺状に塗布する工程（（ｂ）で示す）とからなる。   In the first step (I), bumps are formed on the surface of the electrode 11 of the semiconductor chip 1 using, for example, a gold wire (having 99% or more, preferably 99.99% or more gold and having a diameter of about 25 μm). 1 and a high-elastic adhesive 4 as an underfill material at a portion including the electrode 21 formed on the mounting substrate 2 and a semiconductor as shown in FIG. And a step (shown by (b)) in which the chip 1 is applied in a long shape about the length of one side.

次の第２の工程（II）は、表面にバンプ３が形成された電極１１を、実装基板２の高弾性接着剤４が塗布された電極２１に対向させるようにして、半導体チップ１を実装基板２上に配置する位置決め工程である。   In the next second step (II), the semiconductor chip 1 is mounted so that the electrode 11 having the bump 3 formed on the surface faces the electrode 21 to which the high elastic adhesive 4 of the mounting substrate 2 is applied. This is a positioning step for placement on the substrate 2.

そして、第３の工程（III）は、半導体チップ１を実装基板２に接合する工程であり、ボンディングツールＴを用いて、バンプ３に０．９８Ｎ／ｂｕｍｐ程度の荷重をかける。このとき同時に、高弾性接着剤４を硬化させる（本実施形態では、約２４０℃で５秒間加熱する）処理を行う。これにより、半導体チップ１の電極１１が実装基板２の電極２１にバンプ３を介して電気的に接続されるとともに、半導体チップ１の一辺側が高弾性接着剤４により実装基板２に接合される。   The third step (III) is a step of bonding the semiconductor chip 1 to the mounting substrate 2, and a load of about 0.98 N / bump is applied to the bump 3 using the bonding tool T. At the same time, the high-elastic adhesive 4 is cured (in this embodiment, heated at about 240 ° C. for 5 seconds). Thereby, the electrode 11 of the semiconductor chip 1 is electrically connected to the electrode 21 of the mounting substrate 2 via the bump 3, and one side of the semiconductor chip 1 is bonded to the mounting substrate 2 by the high elastic adhesive 4.

以上の工程（Ｉ）〜（III）を経て、図１に示す本実施形態の半導体チップの実装構造が得られることになる。   Through the above steps (I) to (III), the semiconductor chip mounting structure of this embodiment shown in FIG. 1 is obtained.

この本実施形態の半導体チップの実装構造によれば、半導体チップ１を実装基板２に接合する接着剤として比較的硬い高弾性材料の接着剤４を用いているので、半導体チップ１の実装基板２への固定強度が向上し、これにより半導体チップの実装構造が一辺側だけの片持ち保持であっても、従来例のようなバンプのみで片持ち保持させるものに比べて十分な固定強度を得ることができる。しかも、半導体チップ１を一辺側だけで実装基板２に片持ち保持させているものであるから、温度変化が生じた際に半導体チップ１と実装基板２の線膨張率の相違によって応力が生じたとしても、このような応力の影響を低減して、半導体チップの破損等を防止することができる。   According to the semiconductor chip mounting structure of the present embodiment, the adhesive 4 made of a relatively hard and highly elastic material is used as an adhesive for bonding the semiconductor chip 1 to the mounting substrate 2. As a result, even if the mounting structure of the semiconductor chip is cantilevered only on one side, sufficient securing strength can be obtained compared to the conventional cantilevered only with bumps. be able to. In addition, since the semiconductor chip 1 is cantilevered on the mounting substrate 2 only on one side, stress is generated due to a difference in linear expansion coefficient between the semiconductor chip 1 and the mounting substrate 2 when a temperature change occurs. However, it is possible to reduce the influence of such stress and prevent the semiconductor chip from being damaged.

ところで、半導体チップ１として、図３に示すように、圧力センサや加速度センサ等の検知部１２を備えたものを用いることができる。しかしながら、図３に示すように、検知部１２を半導体チップ１と実装基板２との接合部位（接着剤により接合されている部位）Ａと重複するように配置すると、検知部１２が線膨張率の差に起因する応力の影響を受け易くなってしまう。そのため、上記のようなセンサを備えた半導体チップ１を用いる場合は、図４に示すように、検知部１２を半導体チップ１の他辺側（右辺側）に配置することで、接合部位Ａから離間させるのである。このように、検知部１２を接合部位Ａから離間させることにより、検知部１２への応力の影響を低減させることができる。   By the way, as the semiconductor chip 1, as shown in FIG. 3, a semiconductor chip 1 including a detection unit 12 such as a pressure sensor or an acceleration sensor can be used. However, as shown in FIG. 3, when the detection unit 12 is arranged so as to overlap with a bonding portion (a portion bonded by an adhesive) A between the semiconductor chip 1 and the mounting substrate 2, the detection unit 12 has a linear expansion coefficient. It becomes easy to receive the influence of the stress resulting from the difference. Therefore, when using the semiconductor chip 1 provided with the sensor as described above, as shown in FIG. 4, by arranging the detection unit 12 on the other side (right side) of the semiconductor chip 1, They are separated. Thus, by separating the detection unit 12 from the bonding site A, the influence of the stress on the detection unit 12 can be reduced.

加えて、検知部１２に加わる界面応力を緩和するために、応力緩和構造を半導体チップ１に設けることとしてもよい。このような応力緩和構造は、接合部位Ａと検知部１２との間に、例えば、図５に示すような半導体チップ１の表裏に貫通する切欠孔１３や、図６に示すような溝部１４を形成することで得ることができ、このような切欠孔１３や溝部１４等を形成しておくことによって、温度変化によって応力が生じた際に、切欠孔１３や溝部１４が形成された部位で応力が発散され、これにより、検知部１２への応力の影響を低減することができる。   In addition, a stress relaxation structure may be provided in the semiconductor chip 1 in order to relieve the interface stress applied to the detection unit 12. Such a stress relaxation structure includes, for example, a notch hole 13 penetrating the front and back of the semiconductor chip 1 as shown in FIG. 5 and a groove 14 as shown in FIG. By forming such a notch hole 13 and groove 14 or the like, when stress is generated due to temperature change, stress is generated at the site where the notch hole 13 or groove 14 is formed. Is diverged, thereby reducing the influence of stress on the detection unit 12.

（実施形態２）
本実施形態の半導体チップの実装構造は、高弾性接着剤４に加えて、低弾性材料の接着剤５を用いたことに特徴があり、上記実施形態１と同様の構成については同一の符号を付して説明を省略する。 (Embodiment 2)
The semiconductor chip mounting structure of this embodiment is characterized by using a low-elasticity adhesive 5 in addition to the high-elasticity adhesive 4, and the same reference numerals are used for the same configurations as in the first embodiment. The description will be omitted.

半導体チップの実装構造は、図７（ａ）に示すように、半導体チップ１と、該半導体チップ１の一辺側（図７（ａ）における左辺側）を高弾性接着材４により接合するとともに、半導体チップ１の他辺側（図７（ａ）における右辺側）を低弾性材料の接着剤５により接合する実装基板２とからなる。   As shown in FIG. 7A, the semiconductor chip mounting structure is formed by joining the semiconductor chip 1 and one side of the semiconductor chip 1 (the left side in FIG. 7A) with a highly elastic adhesive material 4, The mounting board 2 is formed by joining the other side of the semiconductor chip 1 (the right side in FIG. 7A) with an adhesive 5 made of a low elastic material.

ここで、半導体チップ１は、例えばＳｉチップやＩＣチップ等の平板状の半導体チップであり、このチップ本体１０の一面の一辺側に薄膜の電極１１が形成されるとともに、他辺側に電極１１と略同形状の薄膜のダミー電極１５（図８参照）が形成されている。実装基板２は、例えばセラミックスや樹脂等から平板状に形成された絶縁基板２０の一面に、半導体チップ１の電極１１に対応する金又はニッケル又は銅等からなる薄膜の電極２１、及び半導体チップ１のダミー電極１５に対応するダミー電極２２が形成されているものである。また、低弾性材料の接着剤（以下、低弾性接着剤という）５は、例えば、シリコン系樹脂等の熱硬化性樹脂であり、弾性率が０．９ＭＰａ〜１０ＭＰａ、線膨張率が１６０ｐｐｍ〜３００ｐｐｍであるものが好ましく、本実施形態では、このような低弾性接着剤５として、弾性率が０．９ＭＰａ、線膨張率が３００ｐｐｍ、硬化条件が約１５０℃で３０分であるようなシリコン系樹脂（東レ・ダウコーニング社製のＤＡ６５０１（商品名））を用いている。尚、高弾性接着剤４は上記実施形態１と同じものを使用している。   Here, the semiconductor chip 1 is a flat semiconductor chip such as an Si chip or an IC chip, for example. A thin film electrode 11 is formed on one side of one surface of the chip body 10 and the electrode 11 is formed on the other side. A thin-film dummy electrode 15 (see FIG. 8) having substantially the same shape is formed. The mounting substrate 2 includes, for example, a thin film electrode 21 made of gold, nickel, or copper corresponding to the electrode 11 of the semiconductor chip 1 on the one surface of the insulating substrate 20 formed in a flat plate shape from ceramics, resin, or the like, and the semiconductor chip 1. The dummy electrode 22 corresponding to the dummy electrode 15 is formed. The low-elastic material adhesive (hereinafter referred to as low-elastic adhesive) 5 is, for example, a thermosetting resin such as a silicon-based resin, and has an elastic modulus of 0.9 MPa to 10 MPa and a linear expansion coefficient of 160 ppm to 300 ppm. In this embodiment, the low-elastic adhesive 5 is a silicon-based resin having an elastic modulus of 0.9 MPa, a linear expansion coefficient of 300 ppm, and a curing condition of about 150 ° C. for 30 minutes. (DA6501 (trade name) manufactured by Toray Dow Corning) is used. The high elastic adhesive 4 is the same as that of the first embodiment.

次に、本実施形態の半導体チップの実装構造を得るための実装方法について説明する。本実施形態の半導体チップの実装方法は、いわゆるフリップチップ実装によるものであり、図８に示すように、第１の工程（Ｉ）〜第４の工程（IV）までの４つの工程からなる。   Next, a mounting method for obtaining the semiconductor chip mounting structure of the present embodiment will be described. The semiconductor chip mounting method of this embodiment is based on so-called flip chip mounting, and includes four steps from the first step (I) to the fourth step (IV) as shown in FIG.

第１の工程（Ｉ）は、半導体チップ１の電極１１の表面にバンプ３、及びダミー電極１５の表面にバンプ３と同様なダミーバンプ６を形成するバンプ形成工程（（ａ）で示す）と、実装基板２に形成した電極２１を含む部位にアンダーフィル材として高弾性接着剤４を、ダミー電極２２を含む部位にアンダーフィル材として低弾性接着剤５を、それぞれ図７（ｂ）に示すように半導体チップ１の一辺の長さ寸法程度の長尺状に塗布するアンダーフィル材塗布工程（（ｂ）で示す）とからなる。   The first step (I) is a bump forming step (shown by (a)) for forming bumps 3 on the surface of the electrodes 11 of the semiconductor chip 1 and dummy bumps 6 similar to the bumps 3 on the surface of the dummy electrodes 15; As shown in FIG. 7B, the high elastic adhesive 4 is used as an underfill material in a portion including the electrode 21 formed on the mounting substrate 2, and the low elastic adhesive 5 is used as an underfill material in a portion including the dummy electrode 22. And an underfill material coating step (shown by (b)) in which the semiconductor chip 1 is coated in a long shape about the length of one side.

次の第２の工程（II）は、バンプ３が形成された電極１１を高弾性接着剤４が塗布された電極２１に対向させるとともに、ダミーバンプ６が形成されたダミー電極１５を低弾性接着剤５が塗布されたダミー電極２２に対向させて、半導体チップ１を実装基板２上に配置する位置決め工程である。   In the next second step (II), the electrode 11 on which the bump 3 is formed is opposed to the electrode 21 to which the high elastic adhesive 4 is applied, and the dummy electrode 15 on which the dummy bump 6 is formed is made to have a low elastic adhesive. 5 is a positioning step in which the semiconductor chip 1 is placed on the mounting substrate 2 so as to face the dummy electrode 22 coated with 5.

そして、第３の工程（III）は、半導体チップ１と実装基板２とを接合する前期工程であり、ボンディングツールＴを用いて、各バンプ３，６に０．９８Ｎ／ｂｕｍｐ程度の荷重をかけるとともに、高弾性接着剤４を硬化させる（本実施形態では、約２４０℃で５秒間加熱する）処理を行う。これにより、半導体チップ１の電極１１が実装基板２の電極２１にバンプ３を介して電気的に接続されるとともに、半導体チップ１のダミー電極１５に形成したダミーバンプ６が実装基板２のダミー電極２２上に載置され、同時に半導体チップ１の一辺側が高弾性接着剤４により実装基板２に接合される。   The third step (III) is a previous step for bonding the semiconductor chip 1 and the mounting substrate 2, and a load of about 0.98 N / bump is applied to each bump 3, 6 using the bonding tool T. At the same time, the high-elastic adhesive 4 is cured (in this embodiment, heated at about 240 ° C. for 5 seconds). Thereby, the electrode 11 of the semiconductor chip 1 is electrically connected to the electrode 21 of the mounting substrate 2 via the bump 3, and the dummy bump 6 formed on the dummy electrode 15 of the semiconductor chip 1 is connected to the dummy electrode 22 of the mounting substrate 2. At the same time, one side of the semiconductor chip 1 is bonded to the mounting substrate 2 by the high elastic adhesive 4.

最後の第４の工程（IV）は、半導体チップ１と実装基板２とを接合する後記工程であり、低弾性接着剤５を硬化させる（本実施形態では、約１５０℃で３０分間加熱する）処理を行う。これによって、半導体チップ１の他辺側が低弾性接着剤５で実装基板２に接合される。   The final fourth step (IV) is a postscript step for bonding the semiconductor chip 1 and the mounting substrate 2, and the low elastic adhesive 5 is cured (in this embodiment, heating is performed at about 150 ° C. for 30 minutes). Process. As a result, the other side of the semiconductor chip 1 is bonded to the mounting substrate 2 with the low elastic adhesive 5.

以上の工程（Ｉ）〜（IV）を経て、図７に示す本実施形態の半導体チップの実装構造が得られ、本実施形態の実装方法によれば、各接着剤４，５をそれぞれに適した条件で硬化させる処理を行っているので、両接着剤４，５を一括で硬化させるような場合に比べて、各接着剤４，５の接合強度を向上することができる。   Through the above steps (I) to (IV), the mounting structure of the semiconductor chip of the present embodiment shown in FIG. 7 is obtained. According to the mounting method of the present embodiment, each of the adhesives 4 and 5 is suitable for each. Therefore, the bonding strength of the adhesives 4 and 5 can be improved as compared with the case where both the adhesives 4 and 5 are cured at a time.

本実施形態の半導体チップの実装構造によれば、半導体チップ１を実装基板２に接合する接着剤として比較的硬い高弾性材料の接着剤４を用いているので、半導体チップ１の実装基板２への固定強度が向上し、しかも半導体チップ１の他辺側を低弾性接着剤５により実装基板２に接合しているので、固定強度がさらに向上する。加えて、このように半導体チップ１の他辺側を低弾性接着剤５で実装基板２に接合していることによって、半導体チップ１や実装基板２に衝撃が加えられたとしても、柔らかい低弾性接着剤５で上記のような衝撃を吸収することができ、これにより耐衝撃性が向上する。さらに、接着剤として低弾性材料のものを使用しているので、温度変化が生じた際に半導体チップ１と実装基板２の線膨張率の相違によって応力が生じたとしても、低弾性接着剤５が伸びることにより、このような応力による影響を低減することができ、従来例のように半導体チップ１が破損したりすることがなくなり、たとえ応力がかかったとしても、高弾性接着剤４によりバンプ３を覆っているので、バンプ３の接合外れを防止することができる。   According to the semiconductor chip mounting structure of the present embodiment, since the adhesive 4 of a relatively hard high-elastic material is used as an adhesive for bonding the semiconductor chip 1 to the mounting substrate 2, the semiconductor chip 1 is mounted on the mounting substrate 2. In addition, since the other side of the semiconductor chip 1 is joined to the mounting substrate 2 by the low elastic adhesive 5, the fixing strength is further improved. In addition, since the other side of the semiconductor chip 1 is bonded to the mounting substrate 2 with the low-elasticity adhesive 5 in this way, even if an impact is applied to the semiconductor chip 1 or the mounting substrate 2, soft low elasticity The adhesive 5 can absorb the impact as described above, thereby improving the impact resistance. Further, since a low elastic material is used as the adhesive, even if a stress is generated due to a difference in linear expansion coefficient between the semiconductor chip 1 and the mounting substrate 2 when a temperature change occurs, the low elastic adhesive 5 As a result, the influence of such stress can be reduced, and the semiconductor chip 1 is not damaged as in the conventional example. Even if stress is applied, the bumps are formed by the highly elastic adhesive 4. 3 is covered, it is possible to prevent the bump 3 from being detached.

また、スペーサとしてダミーバンプ６を用いているため、半導体チップ１の実装基板２に対する傾きを補正して、半導体チップ１が実装基板２に対して略平行となるようにすることができ、これにより半導体チップ１の平行度を確保することができる。ところで、このようなスペーサとしては、上記のダミーバンプ６のようなものに限られるものではなく、例えば、図９（ａ），（ｂ）に示すように、樹脂成形品や金属製品等の半球状のスペーサ７，７等、状況に応じて好適なものを選択して使用することとしても良く、これらによっても半導体チップ１の平行度を確保することができる。   Further, since the dummy bumps 6 are used as the spacers, the inclination of the semiconductor chip 1 with respect to the mounting substrate 2 can be corrected so that the semiconductor chip 1 is substantially parallel to the mounting substrate 2. The parallelism of the chip 1 can be ensured. By the way, such a spacer is not limited to the above-described dummy bump 6, and for example, as shown in FIGS. 9A and 9B, a hemispherical shape such as a resin molded product or a metal product. The spacers 7, 7, etc. may be selected and used in accordance with the situation, and the parallelism of the semiconductor chip 1 can be secured also by these.

一方、本実施形態ではフリップチップ実装を利用したものについて述べたが、このような実装方法としては、フリップチップ実装によるものに限られるものではなく、ワイヤボンディング実装によっても本実施形態の実装構造を得ることができる。ワイヤボンディング実装を利用する場合は、第１の工程（Ｉ）と第２の工程（II）を省く代わりに、第３の工程（III）及び第４の工程（IV）を経て、半導体チップ１を高弾性接着剤４と低弾性接着剤５を用いて実装基板２に接合した後に、図１０に示すように、半導体チップ１の電極１１と実装基板２の電極２１とをワイヤＷにより電気的に接続すれば良い。尚、フリップチップ実装の代わりにワイヤボンディング実装を利用する点は、上記実施形態１についても同様に行えることは勿論である。   On the other hand, in the present embodiment, the one using the flip chip mounting has been described. However, such a mounting method is not limited to the flip chip mounting, and the mounting structure of the present embodiment can also be achieved by wire bonding mounting. Obtainable. When using wire bonding mounting, instead of omitting the first step (I) and the second step (II), the semiconductor chip 1 is subjected to the third step (III) and the fourth step (IV). Are bonded to the mounting substrate 2 using the high elastic adhesive 4 and the low elastic adhesive 5, and then the electrode 11 of the semiconductor chip 1 and the electrode 21 of the mounting substrate 2 are electrically connected by the wire W as shown in FIG. Connect to. Needless to say, wire bonding mounting instead of flip chip mounting can also be performed in the first embodiment.

（実施形態３）
本実施形態の半導体チップの実装構造は、実装基板２の構成について特徴があり、その他の構成は上記実施形態２と同様であるので、同様の構成については同一の符号を付して説明を省略する。 (Embodiment 3)
The semiconductor chip mounting structure of the present embodiment is characterized by the configuration of the mounting substrate 2 and the other configurations are the same as those of the second embodiment. Therefore, the same configurations are denoted by the same reference numerals and description thereof is omitted. To do.

つまり、本実施形態においては、図１１（ａ）に示すように、実装基板２の表面に略直方体状の突起部２３を形成し、この突起部２３の表面に電極２１及びダミー電極２２をそれぞれ設けているのであり、このような突起部２３を形成した実装基板２に、上記実施形態２と同様にフリップチップ実装により半導体チップ１を実装することによって、本実施形態の半導体チップの実装構造が得られる。   That is, in the present embodiment, as shown in FIG. 11A, a substantially rectangular parallelepiped protrusion 23 is formed on the surface of the mounting substrate 2, and the electrode 21 and the dummy electrode 22 are formed on the surface of the protrusion 23, respectively. Since the semiconductor chip 1 is mounted on the mounting substrate 2 on which the protrusions 23 are formed by flip-chip mounting in the same manner as in the second embodiment, the semiconductor chip mounting structure of this embodiment can be obtained. can get.

本実施形態によれば、このように突起部２３を設けることによって半導体チップ１と実装基板２との間の距離を上記実施形態２の実装構造よりも広げているので、実装基板２の伸縮の影響が突起部２３によって緩和されることになり、これにより温度変化が生じた際に半導体チップ１と実装基板２の線膨張率の相違によって生じる応力の影響を上記実施形態２の実装構造よりも低減することができるようになる。   According to the present embodiment, the distance between the semiconductor chip 1 and the mounting substrate 2 is increased by providing the protrusions 23 as described above, so that the expansion and contraction of the mounting substrate 2 can be increased. The effect is mitigated by the protrusion 23, and the effect of stress caused by the difference in the linear expansion coefficient between the semiconductor chip 1 and the mounting substrate 2 when the temperature changes due to this is more than in the mounting structure of the second embodiment. Can be reduced.

尚、図１１（ａ）では、フリップチップ実装による本実施形態の実装構造の例を示しているが、本実施形態は上記実施形態１，２と同様にフリップチップ実装によるものに限られるものではなく、図１１（ｂ）に示すように、ワイヤボンディング実装としてもよく、この場合は、突起部２３上に電極２１やダミー電極２２を設けずに、単に突起部２３に半導体チップ１を接着剤４，５で接合した後に、半導体チップ１の電極１１と実装基板２の電極２１とをワイヤＷで電気的に接続すればよい。   FIG. 11A shows an example of the mounting structure of the present embodiment by flip chip mounting, but the present embodiment is not limited to the one by flip chip mounting as in the first and second embodiments. 11B, wire bonding mounting may be used. In this case, the electrode 21 and the dummy electrode 22 are not provided on the protrusion 23, and the semiconductor chip 1 is simply bonded to the protrusion 23. After bonding at 4 and 5, the electrode 11 of the semiconductor chip 1 and the electrode 21 of the mounting substrate 2 may be electrically connected by the wire W.

また、このような突起部２３を備えた実装基板２に半導体チップ１を接着剤４，５により接合する際には、図１２に示すように、接着剤４，５により突起部２３の両側面も覆うように接合すれば、半導体チップ１と実装基板２との接合面積が増加し、半導体チップ１と実装基板２とを強固に接合する（密着力を向上させる）ことができる。   Further, when the semiconductor chip 1 is bonded to the mounting substrate 2 having such a protruding portion 23 with the adhesives 4 and 5, both side surfaces of the protruding portion 23 are bonded with the adhesives 4 and 5, as shown in FIG. Further, the bonding area between the semiconductor chip 1 and the mounting substrate 2 is increased, and the semiconductor chip 1 and the mounting substrate 2 can be firmly bonded (adhesion force can be improved).

（実施形態４）
本実施形態の半導体チップの実装構造は、接着剤４，５と実装基板２との接合部位の構成に特徴があり、その他の構成は上記実施形態２と同様であるので、同様の構成については同一の符号を付して説明を省略する。 (Embodiment 4)
The semiconductor chip mounting structure of the present embodiment is characterized by the structure of the bonding portion between the adhesives 4 and 5 and the mounting substrate 2, and the other structures are the same as those of the second embodiment. The same reference numerals are given and description thereof is omitted.

本実施形態の半導体チップの実装構造では、上記実施形態２のように各接着剤４，５をそれぞれ半導体チップ１の一辺の長さ寸法程度の長尺状に実装基板２に塗布するのではなく、図１３（ｂ）に示すように、半導体チップ１の一辺側の両隅部に対応する実装基板２の部位にそれぞれ略円形状に高弾性接着剤４，４を塗布するとともに、半導体チップ１の他辺側の両隅部に対応する実装基板２の部位にそれぞれ略円形状に低弾性接着剤５，５を塗布して、半導体チップ１を四隅で実装基板２に接合するようにしている。尚、半導体チップの実装方法については上記実施形態２で述べたようにフリップチップ実装によって行っても良いし、ワイヤボンディング実装によるものでも良い。   In the semiconductor chip mounting structure of the present embodiment, the adhesives 4 and 5 are not applied to the mounting substrate 2 in the shape of the length of one side of the semiconductor chip 1 as in the second embodiment. As shown in FIG. 13B, the highly elastic adhesives 4 and 4 are applied in a substantially circular shape to portions of the mounting substrate 2 corresponding to both corners on one side of the semiconductor chip 1, and the semiconductor chip 1. The low-elastic adhesives 5 and 5 are applied in a substantially circular shape to portions of the mounting substrate 2 corresponding to both corners on the other side, so that the semiconductor chip 1 is bonded to the mounting substrate 2 at the four corners. . The semiconductor chip mounting method may be flip-chip mounting as described in the second embodiment or wire bonding mounting.

本実施形態の半導体チップの実装構造によれば、上記実施形態２のように、半導体チップ１の両辺側に、各辺の長さ寸法程度の長尺状に接着剤４，５を塗布するのではなく、半導体チップ１の両辺側の各隅部に略円形状に接着剤４，５を塗布、すなわち、接着剤４，５を２分割するようにして塗布しているので、半導体チップ１と実装基板２との間の接合面積、つまりは接着剤４，５の実装基板との接合部位の面積を小さくすることができる。そのため、温度変化した際に半導体チップ１と実装基板２の線膨張率の相違によって応力が生じたとしても、このような応力の影響を受ける部分が少なくなり、これにより、上記実施形態２の実装構造よりもさらに応力の影響を低減することができる。   According to the semiconductor chip mounting structure of the present embodiment, the adhesives 4 and 5 are applied on both sides of the semiconductor chip 1 in a long shape of about the length of each side as in the second embodiment. Instead, the adhesives 4 and 5 are applied in a substantially circular shape to the corners on both sides of the semiconductor chip 1, that is, the adhesives 4 and 5 are applied so as to be divided into two parts. The bonding area with the mounting substrate 2, that is, the area of the bonding portion of the adhesives 4 and 5 with the mounting substrate can be reduced. For this reason, even if stress is generated due to the difference in linear expansion coefficient between the semiconductor chip 1 and the mounting substrate 2 when the temperature changes, the portion affected by such stress is reduced. The effect of stress can be further reduced than the structure.

ところで、本実施形態では、接着剤４，５をそれぞれ２分割して、半導体チップ１を四隅で実装基板２に接合しているが、本実施形態はこのような形態に限られるものではなく、接着剤４，５をさらに複数に分割することとしてもよく、この場合、実施形態２に比べて半導体チップ１と実装基板２との接合面積が小さくなるように分割すればよい。   By the way, in this embodiment, each of the adhesives 4 and 5 is divided into two, and the semiconductor chip 1 is joined to the mounting substrate 2 at the four corners, but this embodiment is not limited to such a form. The adhesives 4 and 5 may be further divided into a plurality of parts. In this case, the adhesives 4 and 5 may be divided so that the bonding area between the semiconductor chip 1 and the mounting substrate 2 is smaller than that in the second embodiment.

（実施形態５）
上記実施形態４では、図１３に示すように、各一対の高弾性接着剤４，４及び低弾性接着剤５，５によって半導体チップ１の四隅を実装基板２に接合しているが、本実施形態では、図１４に示すように、半導体チップ１の四隅のうち１つのみを高弾性接着剤４で接合し、残る３つを低弾性接着剤５で接合しているものである。 (Embodiment 5)
In the fourth embodiment, as shown in FIG. 13, the four corners of the semiconductor chip 1 are joined to the mounting substrate 2 by each pair of high elastic adhesives 4 and 4 and low elastic adhesives 5 and 5. In the embodiment, as shown in FIG. 14, only one of the four corners of the semiconductor chip 1 is joined with the high elastic adhesive 4, and the remaining three are joined with the low elastic adhesive 5.

すなわち、本実施形態は、半導体チップ１と実装基板２の接合面積、つまりは接着剤４，５の実装基板２との接合部位の合計面積において、各接着剤４，５が占める割合を、高弾性接着剤４よりも低弾性接着剤５のほうが大きくなるようにしているのである。   That is, in the present embodiment, the ratio of the adhesives 4 and 5 to the bonding area of the semiconductor chip 1 and the mounting substrate 2, that is, the total area of the bonding sites of the adhesives 4 and 5 to the mounting substrate 2 is high. The low elastic adhesive 5 is made larger than the elastic adhesive 4.

本実施形態の半導体チップの実装構造によれば、温度変化が生じた際に半導体チップ１と実装基板２の線膨張率の相違によって応力が生じたとしても、低弾性接着剤５を用いていることによって、このような応力の影響を低減することができ、このとき、接着剤４，５の接合部位の合計面積において、応力の影響を低減できる低弾性接着剤５の占める割合を上記実施形態４の実装構造に比べて大きくしているので、さらなる応力の影響の低減を図ることができる。しかも、このように低弾性接着剤５の占める割合を増すことによって、耐衝撃性も向上することになる。   According to the semiconductor chip mounting structure of the present embodiment, the low elastic adhesive 5 is used even if a stress is generated due to the difference in linear expansion coefficient between the semiconductor chip 1 and the mounting substrate 2 when a temperature change occurs. Thus, the influence of such stress can be reduced. At this time, the ratio of the low elastic adhesive 5 that can reduce the influence of the stress to the total area of the joint portions of the adhesives 4 and 5 is the above embodiment. Since it is made larger than the mounting structure 4, the influence of stress can be further reduced. Moreover, the impact resistance is improved by increasing the proportion of the low elastic adhesive 5 in this way.

（ａ）は、本発明の実施形態１の半導体チップの実装構造の部分側面図であり、（ｂ）は、同上の部分上面図である。(A) is a partial side view of the mounting structure of the semiconductor chip of Embodiment 1 of this invention, (b) is a partial top view same as the above. 同上の実装方法の工程説明図である。It is process explanatory drawing of the mounting method same as the above. （ａ）は、同上の他の部分側面図であり、（ｂ）は、同上の他の部分上面図である。(A) is another partial side view of the above, (b) is another partial top view of the same. （ａ）は、同上のさらに他の部分側面図であり、（ｂ）は、同上のさらに他の部分上面図である。(A) is still another partial side view of the above, and (b) is still another partial top view of the same. （ａ）は、同上のさらに他の部分側面図であり、（ｂ）は、同上のさらに他の部分上面図である。(A) is still another partial side view of the above, and (b) is still another partial top view of the same. （ａ）は、同上のさらに他の部分側面図であり、（ｂ）は、同上のさらに他の部分上面図である。(A) is still another partial side view of the above, and (b) is still another partial top view of the same. （ａ）は、本発明の実施形態２の半導体チップの実装構造の部分側面図であり、（ｂ）は、同上の部分上面図である。(A) is a partial side view of the mounting structure of the semiconductor chip of Embodiment 2 of this invention, (b) is a partial top view same as the above. 同上の実装方法の工程説明図である。It is process explanatory drawing of the mounting method same as the above. （ａ）は、同上の他の部分側面図であり、（ｂ）は、同上の他の部分上面図である。(A) is another partial side view of the above, (b) is another partial top view of the same. 同上のさらに他の部分側面図である。It is another partial side view same as the above. （ａ）は、本発明の実施形態３の半導体チップの実装構造の部分側面図であり、（ｂ）は、同上の他の部分側面図である。(A) is a partial side view of the mounting structure of the semiconductor chip of Embodiment 3 of this invention, (b) is another partial side view of the same as the above. 同上のさらに他の要部の部分側面図である。It is a partial side view of other principal part same as the above. （ａ）は、本発明の実施形態４の半導体チップの実装構造の部分側面図であり、（ｂ）は、同上の部分上面図である。(A) is a partial side view of the mounting structure of the semiconductor chip of Embodiment 4 of this invention, (b) is a partial top view same as the above. （ａ）は、本発明の実施形態５の半導体チップの実装構造の部分側面図であり、（ｂ）は、同上の部分上面図である。(A) is a partial side view of the mounting structure of the semiconductor chip of Embodiment 5 of this invention, (b) is a partial top view same as the above.

符号の説明Explanation of symbols

１ 半導体チップ
２ 実装基板
４ 高弾性材料の接着剤
２０ 絶縁基板 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Mounting board 4 Adhesive of highly elastic material 20 Insulating board

Claims (5)

半導体チップと、該半導体チップの一辺側を高弾性材料の接着剤により接合する実装基板とからなることを特徴とする半導体チップの実装構造。   A semiconductor chip mounting structure comprising: a semiconductor chip; and a mounting substrate for bonding one side of the semiconductor chip with an adhesive made of a highly elastic material. 半導体チップは、少なくとも他辺側を低弾性材料の接着剤により実装基板に接合されていることを特徴とする請求項１に記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein at least the other side of the semiconductor chip is bonded to the mounting substrate with an adhesive made of a low elastic material. 実装基板の低弾性材料の接着剤が接合される部位に、スペーサを設けていることを特徴とする請求項２に記載の半導体チップの実装構造。   The semiconductor chip mounting structure according to claim 2, wherein a spacer is provided at a portion of the mounting substrate where the adhesive of the low elastic material is bonded. 半導体チップと実装基板との接合部位を分割していることを特徴とする請求項１乃至３のいずれか１項に記載の半導体チップの実装構造。   The semiconductor chip mounting structure according to any one of claims 1 to 3, wherein a bonding portion between the semiconductor chip and the mounting substrate is divided. 実装基板に、高弾性材料の接着剤、及び低弾性材料の接着剤を塗布する第１の工程と、第１の工程後に半導体チップの一辺側を高弾性材料の接着剤に重複させるとともに、少なくとも他辺側を低弾性材料の接着剤に重複させて、半導体チップを実装基板に配置する第２の工程と、第２の工程後に高弾性材料の接着剤を硬化させて半導体チップの一辺側を実装基板に接合する第３の工程と、第３の工程後に低弾性材料の接着剤を硬化させて半導体チップの少なくとも他辺側を実装基板に接合する第４の工程とを有していることを特徴とする半導体チップの実装方法。   A first step of applying a high-elasticity material adhesive and a low-elasticity material adhesive to the mounting substrate, and overlapping one side of the semiconductor chip with the high-elasticity material adhesive after the first step, and at least The second step of placing the semiconductor chip on the mounting substrate with the other side overlapped with the low-elasticity material adhesive, and curing the high-elasticity material adhesive after the second step, A third step of bonding to the mounting substrate; and a fourth step of bonding at least the other side of the semiconductor chip to the mounting substrate by curing the low elastic material adhesive after the third step. A semiconductor chip mounting method characterized by the above.
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JP2013021367A (en) * 2008-03-19 2013-01-31 Fujitsu Ltd Electronic part

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Publication number Priority date Publication date Assignee Title
JP2013021367A (en) * 2008-03-19 2013-01-31 Fujitsu Ltd Electronic part

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