JP2006202802A - Process for manufacturing semiconductor device - Google Patents
Process for manufacturing semiconductor device Download PDFInfo
- Publication number
- JP2006202802A JP2006202802A JP2005009871A JP2005009871A JP2006202802A JP 2006202802 A JP2006202802 A JP 2006202802A JP 2005009871 A JP2005009871 A JP 2005009871A JP 2005009871 A JP2005009871 A JP 2005009871A JP 2006202802 A JP2006202802 A JP 2006202802A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor substrate
- main surface
- semiconductor device
- adhesive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Dicing (AREA)
Abstract
Description
本発明は小型で且つ薄型の面実装タイプ半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a small and thin surface mount type semiconductor device.
従来の半導体装置の製造方法としては、誘電体分離基板を得るため、それぞれ鏡面研磨された半導体基板と絶縁性基板とを研磨面同士を直接接着して一体化する技術を用いる。即ち、鏡面研磨された基板同士を実質的に異物を含まない清浄な雰囲気中で密着させ、200℃以上の温度で熱処理すると強固な接着基板が得られる。絶縁性基板は半導体基板表面に絶縁膜を形成したもの、あるいは全体が誘電体からなるもの、いずれでもよい。このようにして縦方向に分離された基板に所望の素子を形成し、また素子の横方向分離を行なうために半導体基板側に溝を形成してこの溝に非晶質材料を充填するものがあった(例えば、特許文献1参照)。 As a conventional method for manufacturing a semiconductor device, a technique is used in which a mirror-polished semiconductor substrate and an insulating substrate are directly bonded to each other in order to obtain a dielectric separation substrate. That is, when the mirror-polished substrates are brought into close contact with each other in a clean atmosphere substantially free of foreign substances, and a heat treatment is performed at a temperature of 200 ° C. or higher, a strong bonded substrate can be obtained. The insulating substrate may be either a substrate in which an insulating film is formed on the surface of the semiconductor substrate or a substrate made entirely of a dielectric. In this way, a desired element is formed on the substrate separated in the vertical direction, and a groove is formed on the semiconductor substrate side and the groove is filled with an amorphous material in order to separate the elements in the horizontal direction. (For example, see Patent Document 1).
図2は、前記特許文献1に記載された従来の半導体装置の製造方法を示すものである。
FIG. 2 shows a conventional method of manufacturing a semiconductor device described in
図2(a)〜(e)において、101は第一のN型シリコン基板、102は高濃度N型層、103は第二のN型シリコン基板、104は第一の酸化膜、105は高濃度P型層、106は素子分離溝、107はパッシベーション・ガラス、108は第二の酸化膜を各々示していた。 2A to 2E, 101 is a first N-type silicon substrate, 102 is a high-concentration N-type layer, 103 is a second N-type silicon substrate, 104 is a first oxide film, and 105 is high. The concentration P-type layer, 106 is an element isolation trench, 107 is passivation glass, and 108 is a second oxide film.
図2(a)に示すように、第一のN型シリコン基板101の研磨面にはリンを拡散して高濃度N型層102を形成し、第二のN型シリコン基板103の研磨面にはウェット酸化により第一の酸化膜104を形成し、高濃度N型層102と第一の酸化膜104との各々表面の面粗さを500Å以下として、図2(b)に示すように、研磨面同士を直接接着した後、熱処理をして接着力を強くし、図2(c)に示すように、第一のN型シリコン基板101をラッピングして厚み調整の後、硼素を拡散して高濃度P型層105を形成し、図2(d)に示すように、全面を第二の酸化膜108で覆い、ダイヤモンド・ソーを用いて高濃度P型層105から高濃度N型層102の上面に達する素子分離溝106を形成して破砕層を除去し、図2(e)に示すように、電気泳動法により鉛系パッシベーション・ガラス107を素子分離溝106に充填して焼成する。
As shown in FIG. 2A, phosphorus is diffused on the polishing surface of the first N-type silicon substrate 101 to form a high-concentration N-
その後、コンタクトホール(図示せず)を開けてAl配線(図示せず)を施してダイオードアレイとしているものがあった。
しかしながら、前記従来の構成では、素子分離の前に誘電体分離基板となる接着面に第一の酸化膜104を有した第二のN型シリコン基板103を、第一のN型シリコン基板101の接着面に形成された高濃度N型層102に接着せねばならないがその際、第一の酸化膜104と高濃度N型層102との接着面の表面粗さは500Å以下の鏡面に研磨した上で面同士を合わせて熱処理を施す必要があり、煩雑で工数が掛る上に第二のN型シリコン基板103を必要とする事が素子完成品として薄型化を阻む要因であるという課題を有していた。
However, in the above-described conventional configuration, the second N-type silicon substrate 103 having the first oxide film 104 on the bonding surface that becomes the dielectric isolation substrate before element isolation is replaced with the first N-type silicon substrate 101. The high-concentration N-
本発明は、前記従来の課題を解決するもので、工程がシンプルで且つ半導体装置完成品として薄型化を阻まれる事の無い半導体装置の製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that has a simple process and does not hinder thinning as a completed semiconductor device.
前記従来の課題を解決するために、本発明の半導体装置の製造方法は、片側の面に電極を有する半導体装置において、半導体基板の第一主面側に複数の半導体素子形成領域を有し、該半導体基板の第一主面から半導体素子形成領域よりも深く縦横にハーフカットを施して各々の半導体素子形成領域間に素子分離溝を形成し、該素子分離溝と半導体素子形成領域とを含む半導体基板の第一主面に粘着フィルムを貼り付けて固定する素子分離工程と、半導体基板の第二主面側から研削して厚み調整し、該半導体基板の第二主面に素子分離溝を開口させて粘着フィルム上に半導体基板を完全分離して固定する研削工程と、該研削工程にて得た中間生成物をモールド型とモールド用樹脂とを用いて半導体基板の第二主面と素子分離溝とを含む粘着フィルム上を覆ったモールド樹脂を形成するモールド工程と、粘着フィルムを剥離除去し、半導体素子形成領域の外部コンタクト予定部上に電極を形成する電極形成工程と、モールド樹脂の第一主面から第二主面までをダイシングを施して縦横にダイシング間隙を設けて半導体素子形成領域と電極とを含んだ半導体基板の側面と第二主面とをモールド樹脂が覆った完成品として半導体装置に個別分離する完成分離工程とを含む半導体装置の製造方法とする。 In order to solve the above-described conventional problems, a semiconductor device manufacturing method of the present invention includes a plurality of semiconductor element formation regions on a first main surface side of a semiconductor substrate in a semiconductor device having an electrode on one side surface, Half-cut vertically and horizontally from the first main surface of the semiconductor substrate to form element isolation grooves between the respective semiconductor element formation areas, including the element isolation grooves and the semiconductor element formation areas An element separation step of attaching and fixing an adhesive film on the first main surface of the semiconductor substrate, adjusting the thickness by grinding from the second main surface side of the semiconductor substrate, and forming an element separation groove on the second main surface of the semiconductor substrate A grinding process for opening and completely separating and fixing the semiconductor substrate on the adhesive film, and an intermediate product obtained in the grinding process using a mold and a molding resin, and a second main surface of the semiconductor substrate and the element Adhesive film including separation groove A mold process for forming a mold resin covering the mold, an electrode forming process for peeling and removing the adhesive film to form an electrode on the external contact planned portion of the semiconductor element formation region, and a first main surface of the mold resin. Dicing up to two main surfaces and providing dicing gaps in the vertical and horizontal directions to separate the semiconductor device as a finished product in which the side surface of the semiconductor substrate including the semiconductor element formation region and electrodes and the second main surface are covered with mold resin. And a semiconductor device manufacturing method including a completed separation step.
本構成によって、事前に半導体基板をハーフカットして素子分離溝を形成した上で粘着フィルムにて固定して該粘着フィルムと対向する半導体基板の第二主面側を研削して分離するので、半導体基板と誘電体基板とを接着する等の工程が必要でなくシンプルで且つ半導体装置完成品として薄型化を阻まれる要因の無い半導体装置の製造方法とする事ができる。 With this configuration, the semiconductor substrate is half-cut in advance to form an element isolation groove, and then fixed with an adhesive film, and the second main surface side of the semiconductor substrate facing the adhesive film is ground and separated. A process for bonding the semiconductor substrate and the dielectric substrate is not required, and the manufacturing method of the semiconductor device can be simplified and can be a semiconductor device completed product without causing a factor to reduce the thickness.
以上のように、本発明の半導体装置の製造方法によれば、シンプルで且つ半導体装置完成品として薄型化を阻まれる要因の無い半導体装置の製造方法とする事ができる。 As described above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a method for manufacturing a semiconductor device that is simple and does not hinder thinning as a completed semiconductor device.
以下本発明の実施の形態について、図面を参照しながら説明する。 Embodiments of the present invention will be described below with reference to the drawings.
図1(a)〜(f)は、本発明の実施の形態における半導体装置の製造方法のフローに沿った断面図である。 1A to 1F are cross-sectional views along a flow of a method for manufacturing a semiconductor device in an embodiment of the present invention.
図1(a)〜(f)において、1は半導体基板、2は半導体素子形成領域、3は素子分離溝、4は粘着フィルム、5はモールド樹脂、6ははんだ電極、7はダイシング間隙、8は半導体装置を各々示している。 1A to 1F, 1 is a semiconductor substrate, 2 is a semiconductor element formation region, 3 is an element isolation groove, 4 is an adhesive film, 5 is a mold resin, 6 is a solder electrode, 7 is a dicing gap, 8 Indicates semiconductor devices, respectively.
図1(a)は、半導体基板1の第一主面側に半導体素子形成領域2を有した状態を示す断面である。
FIG. 1A is a cross section showing a state in which a semiconductor element formation region 2 is provided on the first main surface side of the
また、半導体基板1と半導体素子形成領域2とを含む表面は酸化膜等のパッシベーション膜(図示せず)で覆われ、半導体素子形成領域2の外部コンタクト予定部上のパッシベーション膜は除去されて窓(図示せず)が形成されている。
Further, the surface including the
図1(b)は、ダイヤモンドブレードによるダイシングソーにて図1(a)で示した半導体基板1の第一主面から半導体素子形成領域2の領域よりも深く縦横にハーフカットを施して各々半導体素子形成領域2と半導体素子形成領域2との間に素子分離溝3を形成し、半導体素子形成領域2と素子分離溝3とを含む半導体基板1の第一主面に粘着フィルム4を貼り付けて固定する素子分離工程の終了時点の断面を示している。
FIG. 1B shows a semiconductor device in which a half-cut is made vertically and horizontally from the first main surface of the
図1(c)は、図1(b)で示した半導体基板1の第二主面側からBG装置等で研削を施して厚み調整して、半導体基板1を所定の厚みとすると共に素子分離溝3を半導体基板1の第二主面に開口させて粘着フィルム4上に完全分離して固定する研削工程の終了時点の断面を示している。
In FIG. 1C, the
図1(d)は、図1(c)の示す研削工程の終了時点の中間生成物をモールド型(図示せず)内に閉塞して加熱し、エポキシを主成分とする半導体用熱硬化型のモールド用樹脂をモールド型(図示せず)に注入して硬化させた後にモールド型(図示せず)より取り出して、半導体基板1の第二主面と素子分離溝3とを含む粘着フィルム4上にモールド樹脂5を形成するモールド工程の終了時点の断面を示している。
FIG. 1 (d) shows a thermosetting type for semiconductors whose main component is epoxy, in which an intermediate product at the end of the grinding step shown in FIG. 1 (c) is closed and heated in a mold (not shown). A mold resin (not shown) is poured into a mold (not shown) and cured, and then taken out from the mold (not shown), and includes a second main surface of the
図1(e)は、図1(d)の示すモールド工程終了後に粘着フィルム4を剥離除去し、図(a)で記述した半導体素子形成領域2の外部コンタクト予定部上にめっき法又は、ディッピングにてはんだ電極6を形成する電極形成工程の終了時点の断面を示している。 In FIG. 1E, after the molding step shown in FIG. 1D is completed, the adhesive film 4 is peeled and removed, and a plating method or dipping is performed on the external contact planned portion of the semiconductor element formation region 2 described in FIG. The cross section at the time of completion | finish of the electrode formation process which forms the solder electrode 6 is shown.
図1(f)は、図1(e)の示す電極形成工程終了後にモールド樹脂5の第一主面から第二主面までをダイシングソー等にて各々半導体基板1同士の間を縦横にダイシングを施してダイシング間隙7を設けて半導体素子形成領域2とはんだ電極6とを含んだ半導体基板1の側面と第二主面とをモールド樹脂5が覆った完成品である半導体装置8に個別分離する完成分離工程の終了時点の断面を示している。
In FIG. 1F, after the electrode formation step shown in FIG. 1E is completed, the first principal surface to the second principal surface of the mold resin 5 are diced vertically and horizontally between the
かかる構成によれば、事前に半導体基板1をハーフカットして素子分離溝3を形成した上で粘着フィルム4にて固定して該粘着フィルム4と対向する半導体基板1の第二主面側を研削して分離するので、半導体基板と誘電体基板とを接着する等の煩雑な工程が必要でなくシンプルで且つ半導体装置完成品として薄型化を阻まれる要因の無い半導体装置の製造方法とする事ができる。
According to this configuration, the
なお、本実施の形態において、図1(f)に示す完成分離工程にて半導体素子の最小単位にダイシング間隙7で個別分離した半導体装置8としたがダイシング間隙7を設けて個別分離する単位を2つ以上の半導体素子を有する半導体装置8としても良い。
In the present embodiment, the
小型且つ薄型の半導体装置の製造方法として有用であり、特に面実装タイプの半導体装置に適している。 It is useful as a method for manufacturing a small and thin semiconductor device, and is particularly suitable for a surface mount type semiconductor device.
1 半導体基板
2 半導体素子形成領域
3、106 素子分離溝
4 粘着フィルム
5 モールド樹脂
6 はんだ電極
7 ダイシング間隙
8 半導体装置
101 第一のN型シリコン基板
102 高濃度N型層
103 第二のN型シリコン基板
104 第一の酸化膜
105 高濃度P型層
107 パッシベーション・ガラス
108 第二の酸化膜
DESCRIPTION OF
Claims (2)
半導体基板の第一主面側に複数の半導体素子形成領域を有し、該半導体基板の第一主面から前記半導体素子形成領域よりも深く縦横にハーフカットを施して各々の前記半導体素子形成領域間に素子分離溝を形成し、該素子分離溝と前記半導体素子形成領域とを含む前記半導体基板の第一主面に粘着フィルムを貼り付けて固定する素子分離工程と、
前記半導体基板の第二主面側から研削して厚み調整し、該半導体基板の第二主面に前記素子分離溝を開口させて前記粘着フィルム上に前記半導体基板を完全分離して固定する研削工程と、
前記研削工程にて得た中間生成物をモールド用樹脂を用いて前記半導体基板の第二主面と素子分離溝とを含む前記粘着フィルム上を覆ったモールド樹脂を形成するモールド工程と、
前記粘着フィルムを剥離除去し、前記半導体素子形成領域の外部コンタクト予定部上に電極を形成する電極形成工程と、
前記モールド樹脂の第一主面から第二主面までをダイシングを施して縦横にダイシング間隙を設けて前記半導体素子形成領域と前記電極とを含んだ前記半導体基板の側面と第二主面とを前記モールド樹脂が覆った完成品として半導体装置に個別分離する完成分離工程とを含む事を特徴とする半導体装置の製造方法。 In a semiconductor device having an electrode on one side,
Each of the semiconductor element forming regions has a plurality of semiconductor element forming regions on the first main surface side of the semiconductor substrate, and is subjected to a half-cut from the first main surface of the semiconductor substrate deeply and vertically to the semiconductor element forming region. An element separation step of forming an element isolation groove between the first and second semiconductor substrate including the element isolation groove and the semiconductor element formation region, and attaching and fixing an adhesive film on the first main surface;
Grinding from the second main surface side of the semiconductor substrate to adjust the thickness, and opening the element isolation groove on the second main surface of the semiconductor substrate to completely separate and fix the semiconductor substrate on the adhesive film Process,
A molding step of forming a molding resin that covers the adhesive film including the second main surface of the semiconductor substrate and the element isolation groove using the molding resin as an intermediate product obtained in the grinding step;
An electrode forming step of peeling off the adhesive film and forming an electrode on the external contact planned portion of the semiconductor element forming region;
Dicing from the first main surface to the second main surface of the mold resin to provide a dicing gap in the vertical and horizontal directions, the side surface of the semiconductor substrate including the semiconductor element formation region and the electrode, and the second main surface A method of manufacturing a semiconductor device, comprising: a complete separation step of individually separating the semiconductor device as a finished product covered with the mold resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005009871A JP4507889B2 (en) | 2005-01-18 | 2005-01-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005009871A JP4507889B2 (en) | 2005-01-18 | 2005-01-18 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006202802A true JP2006202802A (en) | 2006-08-03 |
JP4507889B2 JP4507889B2 (en) | 2010-07-21 |
Family
ID=36960564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005009871A Expired - Fee Related JP4507889B2 (en) | 2005-01-18 | 2005-01-18 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4507889B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141173A (en) * | 2008-12-12 | 2010-06-24 | Toshiba Corp | Semiconductor device, and method of manufacturing semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001093869A (en) * | 1999-09-22 | 2001-04-06 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
JP2003124392A (en) * | 2001-10-15 | 2003-04-25 | Sony Corp | Semiconductor device and manufacturing method therefor |
JP2003282486A (en) * | 2002-03-20 | 2003-10-03 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and semiconductor device manufacturing by using this method |
-
2005
- 2005-01-18 JP JP2005009871A patent/JP4507889B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001093869A (en) * | 1999-09-22 | 2001-04-06 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
JP2003124392A (en) * | 2001-10-15 | 2003-04-25 | Sony Corp | Semiconductor device and manufacturing method therefor |
JP2003282486A (en) * | 2002-03-20 | 2003-10-03 | Matsushita Electric Ind Co Ltd | Semiconductor device manufacturing method and semiconductor device manufacturing by using this method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141173A (en) * | 2008-12-12 | 2010-06-24 | Toshiba Corp | Semiconductor device, and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP4507889B2 (en) | 2010-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100692446B1 (en) | Solid-state imaging device and method for manufacturing the same | |
KR100688267B1 (en) | Solid-state imaging device and method for manufacturing the same | |
JP6004100B2 (en) | Manufacturing method of semiconductor device | |
US9287222B1 (en) | Integrated semiconductor device and method for fabricating the same | |
TWI566393B (en) | Wafer-level encapsulated semiconductor device, and method for fabricating same | |
KR20040033276A (en) | Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device | |
US20020031897A1 (en) | Method for manufacturing semiconductor device having element isolation structure | |
JP2003332271A (en) | Semiconductor wafer and method of manufacturing semiconductor device | |
CN1225499A (en) | Semiconductor substrate and method for mfg. the same | |
KR20020023105A (en) | Method for manufacturing semiconductor devices | |
JP2007305804A (en) | Semiconductor device, and manufacturing method thereof | |
US20100248450A1 (en) | Method of producing semiconductor device | |
JP2010016188A (en) | Method of manufacturing semiconductor device, and semiconductor device | |
TWI270183B (en) | Wafer-level chip package process | |
JP5542543B2 (en) | Manufacturing method of semiconductor device | |
JP6341554B2 (en) | Manufacturing method of semiconductor device | |
US20080233714A1 (en) | Method for fabricating semiconductor device | |
JP4507889B2 (en) | Manufacturing method of semiconductor device | |
JP2007059755A (en) | Solid-state imaging device and its manufacturing method | |
JP2017139266A (en) | Composite substrate, semiconductor device, and method of manufacturing them | |
JP5444648B2 (en) | Manufacturing method of semiconductor device | |
JP2004327708A (en) | Semiconductor device and its manufacturing method | |
JP4589536B2 (en) | Method for manufacturing thermoelectric element | |
JP2010073803A (en) | Manufacturing method for semiconductor device | |
JP2678218B2 (en) | Bonded substrate and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080116 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20080213 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091113 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091120 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091208 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100120 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100413 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100426 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |