JP2006202398A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which is improved in mounting area and does not cause delay in page read-out operation. <P>SOLUTION: In an outside address EAD<1:0> input part to which a signal is inputted through a page address input part P1, an initial stage buffer G21 of four stages series (G21 to G24) connection constitution receives the outside address EAD<1:0>, and an inversion control input receives an inside chip enable signal #ICE. Also, the inversion control input of the buffer G23 is fixed to "L". A latch part 51 is formed by inverters G24, G25, and an output of the inverter 24 becomes the inside address IAD<1:0>. In a multiplex part for which input/output is performed through a multiplex input/output part P2, an outside address EAD<17:2> and an outside data ED<15:0> are multiplexed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device in which at least a part of an address signal and a data signal are multiplexed.

  In a semiconductor memory device, a wide bus width (number of data bits) is generally required to keep a data transmission / reception rate high. On the other hand, in a portable electronic device typified by a cellular phone, the problem of the mounting area is as important as the data transfer rate.

  For this reason, in order to reduce the mounting area, a multiplex system that multiplexes at least a part of the data signal and the address signal has been proposed. By adopting the multiplex system, the address and data lines are substantially reduced. The mounting area can be reduced without reducing the number of wires. The multiplex system is disclosed in, for example, Patent Document 1 or Patent Document 2.

Japanese Patent Laid-Open No. 5-282882 JP-A-5-282246

  However, in the multiplex system, the data input / output and the address input to be multiplexed are in an exclusive relationship. Therefore, in the case of an access in which the data output and the address input are frequently switched like the page access, the multiplex There is a problem that an operation delay is inevitably required as compared with a non-multiplex type semiconductor memory device that does not employ the method.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor memory device that improves the mounting area and does not cause a delay in page access (page read) operation.

  According to a first aspect of the present invention, there is provided a semiconductor memory device for inputting an external address signal and inputting / outputting an external data signal, and the content of the external address signal needs to be changed when a page is read. A first address signal, and a second address signal that does not need to change the contents at the time of page reading, an input unit provided for inputting the first address signal, and a second address signal A multiplex input / output unit provided by multiplexing at least a partial input and at least a partial input / output of the external data signal; the first and second address signals input from the outside based on a control signal; and A latch operation for latching an external data signal is performed, and internal output data obtained from the inside is output as the external data signal. An address / data latch circuit for executing an operation, wherein the address / data latch circuit is a multiplex system in which at least a part of the input of the second address signal and at least a part of the input / output of the data signal do not compete with each other. A latch operation and the data output operation are performed.

  According to a first aspect of the present invention, there is provided an address / data latch circuit for latching and outputting data in a multiplexed manner in which at least part of the input of the second address signal and at least part of the input / output of the data signal do not conflict By performing the operation, the mounting area can be reduced.

  Further, since the multiplex method is not used for the first address signal that needs to be changed during page reading, there is no delay in the page reading operation.

<Embodiment 1>
(Constitution)
FIG. 1 is an explanatory diagram showing input / output of external signals in the semiconductor memory device according to the first embodiment of the present invention. As shown in the figure, the semiconductor chip 1 (256 Mb × 16 NOR type flash memory) is externally supplied with an external chip enable signal #ECE, an external effective address detection signal #EADV, an external write enable signal #EWE, and an external output enable signal #EOE. , External address EAD <1: 0>, external address EAD <17: 2> (external (input) data ED <15: 0>), and external address EAD <23:18>, respectively, and externally (output) Data ED <15: 0> is output.

  In the external address EAD <23: 0>, the external address EAD <1: 0> is an address signal (first address signal) whose contents need to be changed during page reading, and the external address EAD <23: 2> This is a signal (second address signal) whose contents do not need to be changed during page reading.

  In the first embodiment, a multiplex method is used in which external address EAD <17: 2>, which is part of external address EAD <23: 2>, and external data ED <15: 0> are multiplexed and shared. Adopted.

  FIG. 2 is an explanatory diagram showing a buffer portion of the external control signal in the semiconductor chip 1. As shown in the figure, the CE buffer 25, the OE buffer 26, the WE buffer 27, and the ADV buffer 28 are connected to the external chip enable signal #ECE, the external output enable signal #EOE, the external via the pads 15, 16, 17 and 18, respectively. A write enable signal #EWE and an external effective address detection signal #EADV are received.

  The CE buffer 25 buffers the external chip enable signal #ECE and outputs it as the internal chip enable signal #ICE. The OE buffer 26 buffers the external output enable signal #EOE under the control of the internal chip enable signal #ICE. The WE buffer 27 buffers the external write enable signal #EWE under the control of the internal chip enable signal #ICE and outputs it as the internal write enable signal #IWE. The ADV buffer 28 Under the control of the internal chip enable signal #ICE, the external effective address detection signal #EADV is buffered and output as the internal effective address detection signal #IADV.

  FIG. 3 is a circuit diagram showing the internal configuration of the address / data latch circuit in the semiconductor chip 1. In FIG. 3, for the sake of explanation, the pad is not shown, and only the reference numerals of the page address input unit P1, the multiplex input / output unit P2, and the address input unit P3 are shown instead. In FIG. 3, only the circuit configuration corresponding to the 1-bit signal is shown, but the portion for inputting the external address EAD <1: 0> actually has two illustrated 1-bit components (for two bits). The multiplexed portion for inputting the external address EAD <17: 2> and outputting the external data ED <15: 0> actually has 16 illustrated 1-bit components, and the external address EAD <23: 18> actually has six 1-bit components shown in the figure.

  As shown in FIG. 3, as control signals for the latch operation and data output operation of the address / data latch circuit 2, an internal chip enable signal #ICE, an internal write enable signal #IWE, an internal output enable signal #IOE, and an internal valid address detection Signal #IADV is input.

  First, the input part of the external address EAD <1: 0> input via the page address input part P1 will be described. The first stage buffer G21 in the four stages of inverters (buffers) G21 to G24 connected in series receives the external address EAD <1: 0> (any one of the signals). This buffer G21 receives the internal chip enable signal #ICE at its inversion control input. The inversion control input of the buffer G23 is fixed to “L”. The inverter G24 forms a latch unit 51 by forming a loop with the inverter G25, and the output of the inverter G24 becomes the internal address IAD <1: 0> (any one of them).

  Next, the multiplex part input / output via the multiplex input / output unit P2 will be described. The first-stage buffer G26 in the four-stage inverters (buffers) G26 to G29 has an external address EAD <17: 2> (any one of the signals) or external (input) data ED <15: 0>. (One of the signals). The buffer G26 receives the internal chip enable signal #ICE at the inversion control input, and the buffer G28 receives the internal write enable signal #IWE at the inversion control input. The inverter G29 forms a latch unit 54 by forming a loop with the inverter G30, and the output of the inverter G29 becomes the internal input data ID <15: 0> (any one of the signals).

  The output of the buffer G26 is also connected to the input of the first-stage inverter G31 in the inverters (buffers) G31 to G33 connected in series in three stages. The internal effective address detection signal #IADV is input to the inversion control input of the buffer G32. The inverter G33 forms a latch unit 52 by forming a loop with the inverter G34, and the output of the inverter G33 becomes the internal address IAD <17: 2> (any one of the signals).

  Further, the buffer G35 having the internal output enable signal #IOE as an inversion control input receives the internal output data OUTD <15: 0> (any one of them). The output of the buffer G35 becomes the external (output) data ED <15: 0>.

  Finally, the input part of the external address EAD <23:18> input via the address input unit P3 will be described. The first-stage buffer G36 in the inverters (buffers) G36 to G39 connected in series in four stages receives the external address EAD <23:18> (any one of the signals). This buffer G36 receives the internal chip enable signal #ICE at its inversion control input. Further, the internal effective address detection signal #IADV is received at the inversion control input of the buffer G38. The inverter G39 forms a loop with the inverter G40 to form the latch unit 53, and the output of the inverter G39 becomes the internal address IAD <23:18> (any one of the signals).

  In such a configuration, when the external address EAD <23: 0> is input, the internal chip enable signal #ICE is “L”, the internal valid address detection signal #IADV is “L”, and the internal write enable signal #IWE is “L”. Since the internal output enable signal #IOE is “H”, the external address EAD <1: 0> is the internal address IAD <1: 0>, and the external address EAD <17: 2> is the internal address IAD <17: 2>, a latch operation is performed in which the external address EAD <23:18> is fetched into the latch units 51 to 53 as the internal address IAD <23:18>.

  On the other hand, at the time of data input, the internal chip enable signal #ICE is “L”, the internal write enable signal #IWE is “L”, the internal effective address detection signal #IADV is “H”, and the internal output enable signal #IOE is “H”. Therefore, a latch operation is performed in which the external (input) data ED <15: 0> is taken into the latch unit 54 as the internal input data ID <15: 0>.

  When data is output (including page read), the internal chip enable signal #ICE is “L”, the internal write enable signal #IWE is “H”, the internal valid address detection signal #IADV is “H”, and the internal output Since the enable signal #IOE becomes “L”, the external address EAD <1: 0> is fetched as the internal address IAD <1: 0>, and the internal output data OUTD <15: 0> is external (output) data ED < A data output operation to be output to the outside as 15: 0> is performed.

  Accordingly, in the multiplexer portion, the latch operation and the data output operation can be performed so that the external address EAD <17: 2> and the external data ED <15: 0> do not compete at the time of address input, data input, and data output. .

  As described above, the address / data latch circuit 2 performs the latch operation on the external address EAD <1: 0> regardless of the internal valid address detection signal #IADV, thereby giving the external address EAD <23: 2>. A page read operation for changing only the external address EAD <1: 0> can be executed with relatively simple control contents without being changed.

(Page read operation)
FIG. 4 is a timing chart showing a page read operation of the semiconductor memory device of the first embodiment. The semiconductor memory device of the first embodiment performs the page read operation by changing the internal address IAD <1: 0>. Although not shown in FIG. 4, during a read operation, the internal chip enable signal #ICE is fixed at “L” and the internal write enable signal #IWE is fixed at “H”.

  Referring to the figure, before time t1, internal effective address detection signal #IADV and internal output enable signal #IOE are both "H", and internal effective address detection signal #IADV rises to "L" at time t1. When the time is lowered, the internal address IAD <1: 0>, the internal address IAD <17: 2>, and the internal address IAD <23:18> are determined within the setup time tAVVH from the time t1.

  When the internal valid address detection signal #IADV rises to “H” at time t2, the internal address IAD <17: 2> and the internal address IAD <23:18> hold the state from the time t2 until the hold time tVHAX elapses. . Since internal address IAD <1: 0> is not controlled by internal effective address detection signal #IADV, the state (A0) is held even after lapse of hold time tVHAX from time t2.

  Thereafter, the internal output enable signal #IOE falls to “L” at time t3, and at the subsequent time t5 (after data transition delay time tAVQV (random) after address transition from time t1), the internal address IAD <1: 0. > Is “A0” (internal address IAD <23: 2> is fixed in one page read operation), “D0” of internal output data OUTD <15: 0> is output.

  At this time t5, the address of the internal address IAD <1: 0> also changes from “A0” to “A1”, and the internal address IAD <1 after the data transition delay time tAVQV (page) after the address transition from time t5. : “D1” that is internal output data OUTD <15: 0> corresponding to “A1” of 0: 0> is output.

  Next, at time t6, the address of the internal address IAD <1: 0> changes from “A1” to “A2”, and after the elapse of the data determination delay time tAVQV (page) after the address transition from time t6, the internal address IAD “D2” that is internal output data OUTD <15: 0> corresponding to “A2” of <1: 0> is output.

  Similarly, at time t7, the address of the internal address IAD <1: 0> changes from “A2” to “A3”, and the internal address IAD after the data transition delay time tAVQV (page) after address transition from time t7. “D3” that is internal output data OUTD <15: 0> corresponding to “A3” of <1: 0> is output.

  The internal output enable signal #IOE rises to “H” at time t8, and the value of the internal output data OUTD <15: 0> becomes undefined at time t9 after the elapse of the data output end delay time tGHQZ from time t8.

  As described above, in the first embodiment, the internal address IAD <1: 0> portion whose value changes at the time of page reading is not assigned to the multiplex portion, and the internal address IAD <17 which does not need to be changed at the time of page reading. : 2> part is assigned to the multiplexed part with the external data ED <15: 0>.

  Therefore, the read time of the first data (D0) of the page read operation requires the post-address transition data determination delay time tAVQV (random) similar to the normal random access read, but the second and subsequent data (D1 to D3). As with the non-multiplex type memory, a short post-address transition data decision delay time tAVQV (page) is sufficient. In a general NOR type flash memory having an operating power supply of 1.8 V and a read time (including a sense amplifier read time) of about 100 ns, a page address input cycle time tRC of about 25 ns can be expected.

  Therefore, by setting the page address input cycle time tRC to be the same as the post-address transition data decision delay time tAVQV (page), a high-speed page read operation can be performed as in the non-multiplex system.

  As described above, the address / data latch circuit 2 performs the latch operation and the data output operation in a multiplexed manner in which the external address EAD <17: 2> and the external data ED <15: 0> do not compete with each other. Reduction can be achieved.

  Furthermore, since the multiplex method is not used for the external address EAD <1: 0> that needs to be changed at the time of page reading, there is no delay in the page reading operation.

(Examination of effect)
5 to 7 are explanatory diagrams showing the configuration and operation of the comparative semiconductor memory device for explaining the effect of the first embodiment. The comparative semiconductor memory device is shown as a general configuration example when a multiplex system is used.

  FIG. 5 is an explanatory diagram showing input / output of external signals of the comparative semiconductor memory device. As shown in the figure, the semiconductor chip 31 (256 Mb × 16 NOR flash memory) is externally supplied with an external chip enable signal #ECE, an external effective address detection signal #EADV, an external write enable signal #EWE, and an external output enable signal #EOE. , External address EAD <15: 0> (external (input) data ED <15: 0>) and external address EAD <23:16> are respectively received and external (output) data ED <15: 0> is output to the outside. To do.

  The comparative semiconductor memory device employs a multiplex system in which the external address EAD <15: 0> and the external data ED <15: 0> share a bus.

  The buffer portion of the external control signal in the semiconductor chip 31 is the same as that in the first embodiment shown in FIG.

  FIG. 6 is a circuit diagram showing the internal configuration of the address / data latch circuit in the semiconductor chip 31. As shown in FIG. In FIG. 6, for convenience of explanation, illustration of pads is omitted, and reference numerals of the multiplex input / output unit P12 and the address input unit P13 are shown instead. In FIG. 6, only the circuit configuration corresponding to the 1-bit signal is shown, but the external address EAD <15: 0> and the external data ED <15: 0> are output via the multiplex input / output unit P12. There are actually 16 1-bit components shown in the multiplex part to be performed, and the input part of the external address EAD <23:16> input via the address input unit P13 is actually the 1-bit component shown. There are 8 in.

  First, the multiplex part will be described. The first-stage buffer G46 in the four-stage inverters (buffers) G46 to G49 is connected to the external address EAD <15: 0> (one of the signals) or the external (input) data ED <15: 0>. (One of the signals). The buffer G46 receives the internal chip enable signal #ICE at the inversion control input, and the buffer G48 receives the internal write enable signal #IWE at the inversion control input. The inverter G49 forms a latch unit 55 by forming a loop with the inverter G50, and the output of the inverter G49 becomes the internal input data ID <15: 0> (any one of the signals).

  The output of the buffer G46 is also connected to the input of the first stage inverter G51 in the inverters (buffers) G51 to G53 connected in series in three stages. The internal effective address detection signal #IADV is input to the inversion control input of the buffer G52. The inverter G53 forms a latch unit 56 by forming a loop with the inverter G54, and the output of the inverter G53 becomes the internal address IAD <15: 0> (any one of the signals).

  Further, the buffer G55 having the internal output enable signal #IOE as an inversion control input receives the internal output data OUTD <15: 0> (any one of them). The output of the buffer G55 becomes the external (output) data ED <15: 0>.

  Next, the input part of the external address EAD <23:16> will be described. The first-stage buffer G56 in the four-stage inverters (buffers) G56 to G59 receives the external address EAD <23:16> (any one of the signals). This buffer G56 receives an internal chip enable signal #ICE at its inversion control input. Further, the internal effective address detection signal #IADV is received at the inversion control input of the buffer G58. The inverter G59 forms a latch unit 57 by forming a loop with the inverter G60, and the output of the inverter G59 becomes the internal address IAD <23:16> (any one of the signals).

  In such a configuration, when the external address EAD <23: 0> is input, the internal chip enable signal #ICE is “L”, the internal valid address detection signal #IADV is “L”, and the internal write enable signal #IWE is “H”. Since the internal output enable signal #IOE becomes “H”, the external address EAD <15: 0> is the internal address IAD <15: 0>, and the external address EAD <23:16> is the internal address IAD <23:16. >, Latch operations taken into the latch units 56 and 57 are executed.

  On the other hand, at the time of data input, the internal chip enable signal #ICE is “L”, the internal write enable signal #IWE is “L”, the internal effective address detection signal #IADV is “H”, and the internal output enable signal #IOE is “H”. Therefore, the latch operation is executed in which the external (input) data ED <15: 0> is taken into the latch unit 55 as the internal input data ID <15: 0>.

  When data is output (including page read), the internal chip enable signal #ICE is “L”, the internal write enable signal #IWE is “H”, the internal valid address detection signal #IADV is “H”, and the internal output Since the enable signal #IOE becomes “L”, the internal output data OUTD <15: 0> is output to the outside as external (output) data ED <15: 0>.

  FIG. 7 is a timing chart showing a page read operation of the semiconductor memory device of the comparative semiconductor memory device. The comparative semiconductor memory device performs the page read operation by the change of the internal address IAD <1: 0>, as in the first embodiment. Although not shown in FIG. 7, during a read operation, the internal chip enable signal #ICE is fixed at “L” and the internal write enable signal #IWE is fixed at “H”.

  In the comparative semiconductor memory device, the first data (D0) of the page read operation is the same as that of the semiconductor memory device of the first embodiment, and the times t1 ′ to t5 ′ in FIG. 7 are the times t1 to t5 in FIG. Corresponding to The second and subsequent data (D1 to D3) of the page read operation are different from the semiconductor memory device for comparison and the semiconductor memory device of the first embodiment.

  Referring to FIG. 7, internal output enable signal #IOE rises at time t6 ′, and internal address IAD <15: 0> becomes indefinite after data output end delay time tGHQZ has elapsed.

  Before time t11 (time t7 ′, etc.), internal effective address detection signal #IADV and internal output enable signal #IOE are both “H”, and internal effective address detection signal #IADV is set to “L” at time t11. Upon falling, the address “A1” defined by the internal address IAD <15: 0> and the internal address IAD <23:16> (not shown) is determined within the setup time tAVVH from the time t11. Hereinafter, the description of the internal address IAD <23:16> is omitted for convenience of description.

  When the internal valid address detection signal #IADV rises to “H” at time t12, the internal address IAD <15: 0> holds the state from the time t12 until the hold time tVHAX has elapsed.

  Thereafter, the internal output enable signal #IOE falls to “L” at time t13, and the data (D1) as the internal output data OUTD <15: 0> is received after the data output start delay time tGLQV (= t14) from time t13. appear.

  The internal output enable signal #IOE rises to “H” at time t14, and the content of the internal output data OUTD <15: 0> becomes indefinite after the data output end delay time tGHQZ (= t15) from time t14.

  Thereafter, the internal effective address detection signal #IADV becomes “L” at time t16, so that the internal address IAD <15: 0> (only the internal address IAD <1: 0> is changed) is “A1”. The read operation for the address “A2” designated by the internal address IAD <15: 0> is performed in the same manner as in the case of the address “A1”.

  As described above, in the comparative semiconductor memory device, the internal address IAD <1: 0> portion whose value changes when the page is read is used in the multiplex system.

  Therefore, the read time of the first data (D0) in the page read operation requires the post-address transition data determination delay time tAVQV (random) similar to the normal random access read, and the second and subsequent data are described in the embodiment. This requires a post-address transition data decision delay time tAVQV (page) (= tAVVH + tVHAX + tGLQV) different from that of one semiconductor memory device, that is, the non-multiplex system. When the comparative semiconductor memory device having such a configuration is realized using a general NOR flash memory having a standard in which the operating power supply is 1.8 V and the post-address transition data decision delay time tAVQV (random) is about 100 ns, The post-address transition data decision delay time tAVQV (page) is estimated to be about 45 (= 10 + 10 + 25) ns.

  Further, it is necessary to determine the page address input cycle time tRC in consideration of the data output end delay time tGHQZ, that is, it is necessary to determine the page address input cycle time tRC that satisfies {tRC ≧ tAVVH + tVHAX + tGLQV + tGHQZ}. Therefore, when applied to the above-described general NOR flash memory, it is estimated that the page address input cycle time tRC needs to be at least about 65 (= 10 + 10 + 25 + 20) ns.

  As described above, the comparison semiconductor memory device requires the page address input cycle time tRC to be longer than the post-address transition data decision delay time tAVQV (page) + the data output end delay time tGHQZ, and therefore, compared with the first embodiment. It is obvious that the page read operation is slow.

  Therefore, in a general multiplex semiconductor memory device represented by the comparative semiconductor memory device, the mounting area reduction (reduction in the number of input / output pins) is the same as that in the first embodiment. As shown in FIG. 1, a high-speed page read operation is impossible. That is, the semiconductor memory device according to the first embodiment has an advantage that a high-speed page read operation can be performed as compared with a general multiplex semiconductor memory device represented by the comparative semiconductor memory device.

<Embodiment 2>
When adopting a multiplex system of address signals and data signals, a chip pad provided on a semiconductor chip and an external connection pad electrically connected to the chip pad via an external wiring are in a one-to-one relationship. There is no need. This point is taken into consideration in the semiconductor memory device of the second embodiment.

  FIG. 8 is an explanatory diagram showing a pad configuration of the semiconductor memory device according to the second embodiment of the present invention. As shown in the figure, in the semiconductor chip internal region 3 which means the region in the semiconductor chip 1, the chip pad 11 for inputting the external address EAD <1: 0> is provided in the same manner as each non-multiplex type pad. , External address EAD <17: 2> input chip pad 12, external address EAD <23:18> input chip pad 13, and external data ED <15: 0> input / output chip pad 14. Is provided. These chip pads 11 to 14 are provided independently.

  On the other hand, an external area 4 outside the semiconductor chip 1 is an external connection pad 21 for external address EAD <1: 0> input, external address EAD <17: 2> input and external data ED. An external connection pad 22 for both <15: 0> input / output and an external connection pad 23 for input of an external address EAD <23:18> are provided. These external connection pads 21 to 23 are provided independently.

  The semiconductor chip outer region 4 means, for example, a region such as an external pin forming region of a package that houses the semiconductor chip 1. Note that only one of these pads 11 to 14 and 21 to 23 is shown for convenience of explanation, but actually, the number of necessary bits is provided.

  As shown in FIG. 8, the external connection pad 21 is electrically connected to the external connection pad 21 via a signal line 41. The external connection pad 22 is electrically connected to the chip pad 12 via the signal line 42 and is also electrically connected to the chip pad 14 via the signal line 44. The external connection pad 23 is electrically connected to the chip pad 13 through the signal line 43. Note that a frame, a wire, or the like is conceivable as the signal lines 41 to 44.

  The buffer portion of the external control signal in the semiconductor chip internal region 3 is the same as that of the first embodiment shown in FIG.

  FIG. 9 is a circuit diagram showing an internal configuration of an address / data latch circuit in the semiconductor memory device of the second embodiment. The address / data latch circuit 5 is formed in the region 3 in the semiconductor chip.

  External address EAD <1: 0> input part via page address input part P1 (corresponding to chip pad 11), external address EAD <23:18> via address input part P3 (corresponding to chip pad 13) The input portion is the same as that of the address / data latch circuit 2 of the first embodiment shown in FIG.

  The external data ED <15: 0> input / output portion input / output via the data input / output unit P4 (corresponding to the chip pad 14) will be described. The first-stage buffer G26 in the four-stage inverters (buffers) G26 to G29 receives external (input) data ED <15: 0> (any one of the signals). The buffer G26 receives the internal chip enable signal #ICE at the inversion control input, and the buffer G28 receives the internal write enable signal #IWE at the inversion control input. The inverter G29 forms a latch unit 52 by forming a loop with the inverter G30, and the output of the inverter G29 becomes the internal input data ID <15: 0> (any one of the signals).

  Further, the buffer G35 having the internal output enable signal #IOE as an inversion control input receives the internal output data OUTD <15: 0> (any one of them). The output of the buffer G35 becomes the external (output) data ED <15: 0>.

  Next, an input portion of the external address EAD <17: 2> input through the address input unit P5 (corresponding to the chip pad 12) will be described. The buffer G41 connected in series in four stages and the first stage buffer G41 in the inverters (buffers) G31 to G33 receive the external address EAD <17: 2>. The buffer G32 receives the internal effective address detection signal #IADV as an inversion control input. The inverter G33 forms a latch section 54 by forming a loop with the inverter G34, and the output of the inverter G33 becomes the internal address IAD <17: 2> (any one of the signals).

  In such a configuration, as shown in FIG. 8, the external connection pads 22 are electrically connected to the chip pads 12 and the chip pads 14, so that the address data The latch circuit 5 has an equivalent configuration to the address / data latch circuit 2 of the first embodiment shown in FIG. That is, when viewed from the entire device including the semiconductor chip inner region 3 and the semiconductor chip outer region 4, a multiplex system in which the external address EAD <15: 0> and the external address EAD <17: 2> are multiplexed is realized. ing.

  As a result, when the external address EAD <23: 0> is input, data is input, and data is output (including page read), the address / data latch circuit 5 is the address / data latch circuit of the first embodiment. The same operation as 2 can be performed.

  Therefore, in the semiconductor chip outer region 4, the mounting area (the number of external connection pins in the semiconductor chip outer region 4 etc.) can be reduced as in the first embodiment, and as fast as the non-multiplex system. A page read operation can be performed.

  Further, the semiconductor chip internal region 3 can be realized with a configuration equivalent to an existing non-multiplex type semiconductor memory device.

It is explanatory drawing which shows the input / output of the external signal of the semiconductor memory device which is Embodiment 1 of this invention. 4 is an explanatory diagram illustrating a buffer portion of an external control signal in the semiconductor chip according to the first embodiment. FIG. 2 is a circuit diagram showing an internal configuration of an address / data latch circuit in a semiconductor chip of a semiconductor chip 1; FIG. FIG. 3 is a timing chart showing a page read operation of the semiconductor memory device in the first embodiment. FIG. 6 is an explanatory diagram showing a configuration (part 1) of a comparative semiconductor memory device for explaining the effect of the first embodiment; FIG. 6 is an explanatory diagram showing a configuration (part 2) of the comparative semiconductor memory device for explaining the effect of the first embodiment; FIG. 6 is an explanatory diagram showing an operation of a comparative semiconductor memory device for explaining the effect of the first embodiment; It is explanatory drawing which shows the pad connection condition between the chip | tip inside and outside of the semiconductor memory device which is Embodiment 2 of this invention. FIG. 6 is a circuit diagram showing an internal configuration of an address / data latch circuit in the semiconductor memory device of the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 2, 5 Address data latch circuit, 3 Area | region inside semiconductor chip, 4 Area | region outside semiconductor chip.

Claims (3)

A semiconductor memory device for inputting an external address signal and inputting / outputting an external data signal, wherein the external address signal changes in content when a page is read and a first address signal whose content needs to be changed when the page is read A second address signal that does not need to be
An input unit provided for inputting the first address signal;
A multiplex input / output unit provided by multiplexing at least a partial input of the second address signal and at least a partial input / output of the external data signal;
Based on the control signal, the first and second address signals inputted from the outside and the latch operation for latching the external data signal are executed, and the internal output data obtained from the inside is outputted as the external data signal. An address / data latch circuit for executing data output operation,
The address / data latch circuit performs the latch operation and the data output operation in a multiplexed manner in which at least part of the input of the second address signal and at least part of the input / output of the data signal do not compete.
Semiconductor memory device. The semiconductor memory device according to claim 1,
The control signal includes an effective address detection signal,
The address / data latch circuit includes:
The latch operation is performed on the second address signal under the control of the effective address detection signal, and the latch operation is performed on the first address signal regardless of the effective address detection signal.
Semiconductor memory device. A semiconductor memory device according to claim 1 or 2,
The semiconductor memory device includes a semiconductor chip that includes the address / data latch circuit and performs an actual operation, and a semiconductor chip outside region portion provided in a region outside the semiconductor chip,
The semiconductor chip is
A first internal input section for inputting the first address signal;
A second internal input unit for inputting at least a part of the second address signal;
An internal input / output unit for at least partial input / output of the data signal, and the first and second internal input units and the internal input / output unit are provided independently,
The area outside the chip is
An external input unit for inputting the first address signal;
An external input / output unit that inputs and outputs at least a part of the second address signal and at least a part of the external data signal, and the external input unit and the external input / output unit are independent of each other. Provided,
The external input unit is electrically connected to the first internal input unit via a first signal line,
The external input / output unit is electrically connected to the second internal input unit via a second signal line and electrically connected to the internal input / output unit via a third signal line. ,
The input unit includes the external input unit, and the multiple input / output unit includes the external input / output unit.
Semiconductor memory device.

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