JP2006202167A - Redundant apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a redundant apparatus capable of acquiring measured data without reducing the abnormality detection ratio of a circuit or the like, capable of efficiently utilizing time and being inexpensively constituted without using complicated time sharing processing or the like for a program. <P>SOLUTION: In the redundant apparatus constituted of a plurality of CPUs and an A/D converter common to these CPUs, either one of the CPUs acts as a master CPU to control the drive of the A/D converter and receive data to be converted and outputted from the A/D converter, and the other CPU acts as a slave CPU to receive the same data as the data inputted to the master CPU from the common A/D converter. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a redundancy device, and more particularly to improvement of a device in which CPUs are made redundant.

  For example, in a system including a CPU, in order to prevent the system from becoming inoperable due to a failure of the CPU, a system is constructed by incorporating a plurality of CPUs. When a system is operated as a slave and the master CPU fails, it is widely performed to switch the master authority to another CPU and continuously operate the system.

  In general, a process control system used in various industrial plants is configured to convert an analog input signal such as a voltage of 1 to 5 V or a current of 10 to 20 mA into a digital signal by an A / D converter and input it to a CPU. ing.

JP-A-6-165257

  In FIG. 6 of Patent Document 1, a smart sensor that collects data only when necessary is provided, and the configuration of a measurement data collection device that is made redundant by two systems of a normal system analog input card and a standby system analog input card is commonly used. The system is indicated with a suffix a, and the standby system is indicated with a suffix b. An A / D converter and a CPU are mounted on the regular analog input card and the standby analog input card, respectively.

FIG. 4 is a block diagram of a conventional example. In FIG. 4, the A / D converters 3 and 4 are individually provided in the two redundant CPUs 1 and 2, respectively, and these A / D converters 3 and 4 have a common analog input signal S _in. Is entered. The CPUs 1 and 2 are connected so that they can communicate with each other, and recognize the mutual master / slave relationship. Then, control signals S _c1 and S _c2 for controlling the start of A / D conversion operation and the start of data output to the corresponding A / D converters 3 and 4 by any one of the CPUs 1 and 2 having the master authority, The A / D converters ₃ and ₄ selectively input the digital signals D ₃ and D ₄ converted in response to the access to any of the CPUs 1 and 2 having the master authority.

FIG. 5 is a block diagram of another conventional example. Also in FIG. 5, the two redundant CPUs 5 and 6 are connected so that they can communicate with each other, and recognize the mutual master-slave relationship. Then, any one of the CPUs 5 and 6 having the master authority individually controls the start of A / D conversion operation and the start of data output via the OR gate 8 with respect to the common A / D converter 7. _c5, accessed by providing the S _c6, a / D converter 7 is selectively inputting a digital signal D ₇ converted in response to the access CPU5,6 one having master authority.

  However, according to the configuration of FIG. 4, since the two A / D converters 3 and 4 are provided, the cost is increased accordingly.

On the other hand, according to the configuration of FIG. 5, since two CPUs ₅ and ₆ access one A / D converter 7, when the control signals S _c5 and S _c6 are given to the A / D converter 7, It is necessary to input via the OR gate 8.

  Since it is also necessary to divide (time sharing) the time for each CPU 5 and 6 to access the A / D converter 7 and control it, the temporal performance will be reduced. The software program becomes complicated.

  In any case, since the timing at which measurement data is acquired between the CPUs 1, 2, 5, 6 is different, the measurement data acquired by the CPUs 1, 2, 5, 6 are different.

  As a result, even if the CPU 1, 2, 5, or 6 exchanges the measurement data acquired and tries to compare and collate with each other, it is not possible to confirm the coincidence of the measurement data as it is. It is necessary to perform processing such as in-range diagnosis and selection of valid measurement data.

  The present invention solves these conventional problems, and its purpose is to obtain measurement data without lowering the abnormality detection rate of a circuit or the like and to use time efficiently, and is complicated in terms of programs. An object of the present invention is to provide a redundant apparatus that can be configured at low cost without using time sharing processing or the like.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A redundancy device comprising a plurality of CPUs and an A / D converter common to the plurality of CPUs,
One of the CPUs controls the drive of the A / D converter as a master CPU and captures data converted and output from the A / D converter, and the other CPUs as slave CPUs share the same data as the master CPU with a common A / D It takes in from D converter, It is characterized by the above-mentioned.

The invention according to claim 2 is the redundancy apparatus according to claim 1,
The plurality of CPUs transfer data fetched from the A / D converter to each other, compare and collate each other data, and from each branch point of the output system of the A / D converter, a data receiving unit of each CPU It is characterized in that an abnormality in the part leading to is judged.

The invention according to claim 3 is the redundancy apparatus according to claim 1,
A known reference analog input signal is inputted to the A / D converter and the converted data is taken into the master CPU, and the master CPU compares and compares the converted data with a known value to determine an abnormality of the common part which is not made redundant. It is characterized by doing.

The invention according to claim 4 is the redundancy apparatus according to any one of claims 1 to 3,
A plurality of slave CPUs are connected.

  According to the present invention, measurement data can be acquired efficiently without lowering the abnormality detection rate of circuits, etc., and time can be used efficiently. On the program side, redundancy is achieved at low cost without using complicated time sharing processing. A device can be realized.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a specific example of the present invention, and FIG. 2 is a block diagram in which FIG. 1 is divided into a common part and a redundant part by function. In these figures, two redundant CPUs 9 and 10 are connected so that they can communicate with each other by, for example, a UART (Universal Asynchronous Receiver Transmitter), and recognize the mutual master / slave relationship. Then, the CPU 9 having the master authority accesses the common A / D converter 11 by giving a control signal _Sc9 for controlling the start of A / D conversion operation and the start of data output.

A / D converter 11 in response to the access of the CPU 9, and inputs the same time digital signal D ₁₁ which converts an analog input signal _{S in} to CPU9,10 two systems. That is, exactly the same data is input to the two CPUs 9 and 10.

  The two systems of CPUs 9 and 10 transfer the inputted and fetched data to each other, and compare and collate their own data with the other party's data. Here, since the two systems of CPUs 9 and 10 have acquired exactly the same data, the comparison / collation results match if all are normal. Therefore, when the comparison / collation result does not match, it can be determined that the part from the branch point of the output system of the A / D converter 11 to each receiving unit is abnormal.

By the way, by making one A / D converter, the control signal _Sc9 output from the CPU 9 having the master authority, the branch point of the output system of the A / D converter 11 and the A / D converter 11 are reached. Thus, there is a common circuit portion that is not made redundant, and the abnormality detection rate of these common circuit portions is lower than that of the conventional configuration in which the A / D converter shown in FIG. 4 has two systems.

  For this, a common reference analog input signal is inputted to the A / D converter 11 to obtain conversion data, and an abnormality of the common circuit can be found by comparing and comparing the conversion data with a known value.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the example of FIG. 3, the CPU 12 functioning as a slave is added to make the CPU three systems, and the three systems of CPUs 9, 10, 12 are connected to communicate with each other. A / D converter 11 in response to the access of the CPU 9, and inputs the same time digital signal D ₁₁ which converts an analog input signal _{S in} the three systems of CPU9,10,12. That is, the same data is input to the three systems of CPUs 9, 10, and 12.

  The three systems of CPUs 9, 10, and 12 transfer the input and captured data to each other, and compare and collate their own data with the other party's data. Here, since the three systems of CPUs 9, 10, and 12 have acquired exactly the same data, if all are normal, the comparison and collation results match. Therefore, when the comparison / collation results do not match, by appropriately changing the combination of these CPUs 9, 10 and 12, any CPU system from the branch point of the output system of the A / D converter 11 to each receiving unit Can be judged abnormal.

  As described above, according to the present invention, the time sharing control as in the conventional circuit is not required, so that the temporal performance can be improved and the program configuration is simplified.

  In addition, since the circuit configuration is simplified, the cost of the circuit can be reduced.

  Further, since each CPU acquires the same conversion data from the A / D converter, it is possible to diagnose a redundant circuit portion provided in a plurality of systems.

  Further, by inputting a known reference analog input signal to the A / D converter and taking in the converted data to the master CPU, the master CPU compares and compares the converted data with a known value for a common portion that is not made redundant. Abnormalities can be determined, and the detection rate of abnormalities does not decrease compared to the case where each CPU is provided with an A / D converter.

  Furthermore, in the case of a system in which the CPU and the A / D converter are insulated, it is effective because the presence or absence of abnormality can be diagnosed with respect to the insulating element between the insulations.

It is a block diagram which shows the specific example of the redundancy apparatus based on this invention. It is the block diagram which divided FIG. 1 into the common part and the redundancy part according to the function. It is a block diagram which shows the other Example of this invention. It is a block diagram of a prior art example. It is a block diagram of another prior art example.

Explanation of symbols

9 CPU (Master)
10 CPU (Master)
11 A / D converter 12 CPU (master)

Claims (4)

A redundancy device comprising a plurality of CPUs and an A / D converter common to the plurality of CPUs,
One of the CPUs controls the drive of the A / D converter as a master CPU and captures data converted and output from the A / D converter, and the other CPUs as slave CPUs share the same data as the master CPU with a common A / D A redundancy device, wherein the redundancy device is fetched from a D converter.   The plurality of CPUs transfer data fetched from the A / D converter to each other, compare and collate each other data, and from each branch point of the output system of the A / D converter, a data receiving unit of each CPU The redundancy apparatus according to claim 1, wherein an abnormality in a portion leading to is determined.   A known reference analog input signal is inputted to the A / D converter and the converted data is taken into the master CPU, and the master CPU compares and compares the converted data with a known value to determine an abnormality of the common part which is not made redundant. The redundancy apparatus according to claim 1, wherein: 4. The redundancy apparatus according to claim 1, wherein a plurality of slave CPUs are connected.

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