JP2006196790A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit comprising a macro cell in which dropping of power source potential due to the current flowing constantly or momentary or delay fluctuation of each macro cell due to rising of a ground potential never occurs. <P>SOLUTION: A semiconductor integrated circuit 1 comprises macro cells 3a-3m. It comprises an n-channel field effect transistor 11 connected to the macro cells 3a-3m, and supplies a power supply potential to the macro cells 3a-3m through the n-channel field effect transistor 11. It also comprises a p-channel field effect transistor 21 connected to the macro cells 3a-3m, and supplies a ground potential to the macro cells 3a-3m through the p-channel field effect transistor 21. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit including macrocells such as standard cells and gate arrays.

  In recent years, semiconductor integrated circuits such as standard cells and gate arrays have become lower in power supply voltage and increased in current consumption due to higher integration. As the current consumption increases, the power supply potential decreases and the ground potential increases during circuit operation due to the resistance components of the power supply potential wiring and ground potential wiring.

Many of these semiconductor integrated circuits are provided with macrocells (see, for example, Patent Document 1).
A macro cell used in a standard cell, a gate array, or the like is configured such that a cell delay is set on the assumption that it is used under the same conditions, and its operation is confirmed by circuit simulation.
However, when a block with a large current consumption and a block with a small current consumption are generated in the semiconductor integrated circuit, the degree of decrease in the power supply potential and the degree of increase in the ground potential differ between the two blocks. In such a case, even in a circuit assumed by simulation so that the cell delays are equal, a difference in cell delay occurs, resulting in a malfunction of the circuit operation.

In order to solve such a problem, Patent Document 2, Patent Document 3, and the like disclose a technique of providing a capacitor between a power supply (Vcc) and a ground (GND).
Patent Document 4 discloses a technique for providing a capacitor between a power supply (Vcc) and a ground (GND) in a macro cell.

Japanese Patent Laid-Open No. 10-144794 Japanese Patent Laid-Open No. 2003-92350 JP 2003-152090 A JP 2001-68552 A

  As described above, in the conventional semiconductor integrated circuit, the power supply potential is lowered or the ground potential is raised, and the delay variation of each macro cell may occur.

FIG. 12 is a diagram showing an example of a conventional semiconductor integrated circuit provided with a plurality of macro cells.
A semiconductor integrated circuit is provided with a low resistance metal wiring and a high resistance metal wiring. In general, the rise time of the macro cell is delayed as the power supply potential (Vcc) decreases.

  The operation of the flip-flop K in the circuit of FIG. 12 is as follows. As shown in FIG. It has been simulated to output. Here, for example, when the H circuit is not operating and the C, D, and E circuits operate at high speed and the current consumption increases, one power supply potential wiring is caused by the resistance component of the Vcc / GND metal wiring. Compared with (Vcc wiring V2), the potential of the other power supply potential wiring (Vcc wiring V1) is significantly lowered. In addition, the potential of the other ground potential wiring (GND wiring G1) is significantly higher than that of one ground potential wiring (GND wiring G2).

  The A, B, F, and G circuits are connected to the same GND wiring. However, the A and B circuits are supplied with the power supply potential from the Vcc wiring V1, and the F and G circuits are supplied with the power supply potential from the Vcc wiring V2. Has been. Therefore, only the rise delay of the A and B circuits is extremely increased. As a result, as shown in FIG. 13B, the rising edge of the CK of the flip-flop that has passed through the circuits A and B from the input 1 is delayed and a malfunction occurs.

  On the other hand, in Patent Document 2, Patent Document 3, Patent Document 4, and the like described above, since a capacitor is provided between Vcc / GND, the effect of reducing potential fluctuation with respect to the current flowing through the circuit instantaneously. Can be expected to some extent. However, it cannot be expected to suppress the decrease in power supply potential and the increase in ground potential caused by the current flowing through the circuit constantly.

  The present invention has been made to solve the above-described problems. In a semiconductor integrated circuit including a macro cell, each macro cell has a decrease in power supply potential or ground potential due to a steady or instantaneous current flowing. An object of the present invention is to provide a semiconductor integrated circuit in which delay variation does not occur.

  A semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit including a macro cell, comprising an N-channel field effect transistor connected to the macro cell, wherein the N-channel field effect transistor is Thus, the power supply potential is supplied to the macro cell.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the gate of the N-channel field effect transistor is connected to the first power supply potential wiring, and the source is the second. Are connected to the power supply potential wiring, and the drain is connected to the macro cell.

  A semiconductor integrated circuit according to a third aspect of the present invention is the semiconductor integrated circuit according to the second aspect, comprising a plurality of the N-channel field effect transistors respectively connected to the plurality of microcells. In the N-channel field effect transistor, each gate is connected to the first power supply potential wiring, and each source is connected to the second power supply potential wiring.

  A semiconductor integrated circuit according to a fourth aspect of the present invention is the semiconductor integrated circuit according to the second or third aspect, wherein the first power supply potential wiring and the second power supply potential wiring are provided in the macro cell. It is not connected.

  A semiconductor integrated circuit according to a fifth aspect of the present invention is the semiconductor integrated circuit according to any one of the first to fourth aspects, further comprising a P-channel field effect transistor connected to the macro cell. A ground potential is supplied to the macro cell via a channel field effect transistor.

  According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the gate of the P-channel field effect transistor is connected to the first ground potential wiring, and the source is the second. Are connected to the ground potential wiring, and the drain is connected to the macro cell.

  A semiconductor integrated circuit according to a seventh aspect of the present invention is the semiconductor integrated circuit according to the sixth aspect, comprising a plurality of the P-channel field effect transistors respectively connected to the plurality of microcells. In the P-channel field effect transistor, each gate is connected to the first ground potential wiring, and each source is connected to the second ground potential wiring.

  The semiconductor integrated circuit according to an eighth aspect of the present invention is the semiconductor integrated circuit according to the sixth or seventh aspect, wherein the first ground potential wiring and the second ground potential wiring are provided in the macro cell. It is not connected.

  According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a macro cell, comprising a P channel field effect transistor connected to the macro cell, wherein the P channel field effect type is provided. A ground potential is supplied to the macro cell via a transistor.

  According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, the gate of the P-channel field effect transistor is connected to the first ground potential wiring and the source is the second. Are connected to the ground potential wiring, and the drain is connected to the macro cell.

  According to an eleventh aspect of the present invention, there is provided a semiconductor integrated circuit according to the tenth aspect of the present invention, comprising the plurality of P-channel field effect transistors respectively connected to the plurality of microcells. In the P-channel field effect transistor, each gate is connected to the first ground potential wiring, and each source is connected to the second ground potential wiring.

  A semiconductor integrated circuit according to a twelfth aspect of the invention is the semiconductor integrated circuit according to the tenth or eleventh aspect of the invention, wherein the first ground potential wiring and the second ground potential wiring are within the macro cell. It is not connected.

  According to the present invention, in a semiconductor integrated circuit including a macro cell, a power supply potential is supplied to the macro cell via an N-channel field effect transistor, or a ground potential is supplied to the macro cell via a P-channel field effect transistor. As a result, it is possible to provide a semiconductor integrated circuit in which delay variation of each macro cell does not occur due to a decrease in power supply potential or a ground potential increase due to a current that flows constantly or instantaneously.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the part which is the same or it corresponds, The duplication description is simplified or abbreviate | omitted suitably.

Embodiment 1 FIG.
The first embodiment of the present invention will be described in detail with reference to FIG.
FIG. 1 is a circuit diagram showing a semiconductor integrated circuit 1 according to the first embodiment. As shown in FIG. 1, a plurality of macro cells 3 a to 3 m such as NOR, NAND, flip-flop, and the like are provided in the semiconductor integrated circuit 1. Specifically, the first macrocell group 2A (block) is provided with five macrocells 3a, 3b, 3c, 3d, and 3e, and the second macrocell group 2B is provided with three macrocells 3f, 3g, and 3h. The third macro cell group 2C is provided with three macro cells 3j, 3k, and 3m.

  Each of the macro cells 3a to 3m is connected to an Nch auxiliary transistor 11 as an N channel field effect transistor (NchFET) and a Pch auxiliary transistor 21 as a P channel field effect transistor (PchFET). With such a configuration, each of the macro cells 3 a to 3 m is supplied with the power supply potential via the Nch auxiliary transistor 11 and supplied with the ground potential via the Pch auxiliary transistor 21.

  Specifically, in the Nch auxiliary transistor 11, the gate (G) is connected to the first power supply potential wiring 6 (first power supply potential wiring), and the source (S) is the second power supply potential wiring 5A, 5B (second power supply). The drain (D) is connected to the macro cells 3a to 3m.

  Here, the source of the Nch auxiliary transistor 11 of the first Nch auxiliary transistor group 10A connected to each of the macrocells 3a to 3e of the first macrocell group 2A is connected in parallel to the common second power supply potential wiring 5A. Has been. Further, the source of the Nch auxiliary transistor 11 in the second Nch auxiliary transistor group 10B and the source of the Nch auxiliary transistor 11 in the third Nch auxiliary transistor group 10C are connected in parallel to the common first power supply potential wiring 5B. Has been. Each of the second power supply potential wirings 5A and 5B provided in block units is not directly connected to the microcells 3a to 3m, but is connected to the power supply (Vcc) through a low resistance metal wiring. Has been.

  On the other hand, in the Pch auxiliary transistor 21, the gate (G) is connected to the first ground potential wiring 9 (first ground potential wiring), and the source (S) is the second ground potential wiring 8A, 8B (second ground potential). The drain (D) is connected to the macro cells 3a to 3m.

  Here, the source of the Pch auxiliary transistor 21 of the third Pch auxiliary transistor group 20C connected to each macro cell 3j, 3k, 3m of the third macro cell group 2C is connected in parallel to the common second ground potential wiring 8B. It is connected to the. Further, the source of the Pch auxiliary transistor 21 of the first Pch auxiliary transistor group 20A and the source of the Pch auxiliary transistor 21 of the second Pch auxiliary transistor group 20B are connected in parallel to the common first ground potential wiring 8A. Has been. Each of the second ground potential wirings 8A and 8B provided in block units is not connected in the microcells 3a to 3m, but is grounded (GND) through a low resistance metal wiring.

  With the above configuration, no current flows through the gate of the Nch auxiliary transistor 11, so that the power supply potential is not lowered due to the influence of the resistance, and is fixed at the potential of Vcc.

Here, the source potential of the Nch auxiliary transistor 11 that drops due to the influence of another circuit (macro cell) is Vcc1, the gate potential of the Nch auxiliary transistor 11 fixed to the Vcc potential is Vcc2, and the threshold voltage at the gate is NVth. Then, the power supply potential supplied to each of the macro cells 3a to 3m via the Nch auxiliary transistor 11 is as follows.
(1) When Vcc2-NVth ≦ Vcc1, Vcc2-NVth
(2) When Vcc2-NVth> Vcc1, Vcc1
Therefore, in the first embodiment, the fluctuation of the power supply potential corresponding to the NVth voltage of the Nch auxiliary transistor 11 is allowed.

  In addition, since no current flows through the gate of the Pch auxiliary transistor 21, the ground potential does not increase due to the influence of the resistance, and is fixed to the GND potential.

Here, the source potential of the Pch auxiliary transistor 21 that rises due to the influence of another circuit (macro cell) is GND1, the gate potential of the Pch auxiliary transistor 21 fixed to the GND potential is GND2, and the threshold voltage at the gate is PVth. Then, the ground potential supplied to each of the macro cells 3a to 3m via the Pch auxiliary transistor 21 is as follows.
(1) When GND2-PVth ≧ GND1, GND2-PVth
(2) If GND2-PVth <GND1, GND1
Therefore, in the first embodiment, the variation of the ground potential corresponding to the PVth voltage of the Pch auxiliary transistor 21 is allowed.

  As described above, in the first embodiment, the power supply potential is supplied to the macro cells 3a to 3m via the Nch auxiliary transistor 11 in the semiconductor integrated circuit 1 including the macro cells 3a to 3m. It is possible to reduce the variation of the cell delay due to the variation of. Further, since the ground potential is supplied to the macro cells 3a to 3m via the Pch auxiliary transistor 21, the variation in cell delay due to the variation in the ground potential can be reduced. That is, it is possible to provide the semiconductor integrated circuit 1 in which the delay variation of each of the macrocells 3a to 3m does not occur due to a decrease in the power supply potential due to a current that flows constantly or instantaneously or an increase in the ground potential.

Embodiment 2. FIG.
A second embodiment of the present invention will be described in detail with reference to FIGS.
FIG. 2 is a circuit diagram showing the semiconductor integrated circuit 1 according to the second embodiment. In the semiconductor integrated circuit 1 of the second embodiment, the Nch auxiliary transistor 11 and the Pch auxiliary transistor 21 are connected to the macro cell of the inverter circuit.

  As shown in FIG. 2, an Nch auxiliary transistor 11 and a Pch auxiliary transistor 21 are connected to the macro cell 3 of the semiconductor integrated circuit 1. With such a configuration, the macro cell 3 is supplied with the power supply potential via the Nch auxiliary transistor 11 and supplied with the ground potential via the Pch auxiliary transistor 21.

Specifically, in the Nch auxiliary transistor 11, the gate potential (G) connected to the first power supply potential wiring 6 becomes Vcc2, the source potential (S) connected to the second power supply potential wiring 5 becomes Vcc1, and the back gate potential. (BG) becomes GND4, and the power supply potential is supplied from the drain (D) to the macro cell 3.
In the Pch auxiliary transistor 21, the gate potential (G) connected to the first ground potential wiring 9 is GND2, the source potential (S) connected to the second ground potential wiring 8 is GND1, and the back gate potential ( BG) becomes Vcc4, and the ground potential is supplied from the drain (D) to the macro cell 3.
Note that the back gate potential of the PchFET constituting the circuit of the macro cell 3 is Vcc3, and the back gate potential of the NchFET is GND3.

Here, the potential supply to the back gates of the Nch auxiliary transistor 11, the Pch auxiliary transistor 21, the PchFET, and the NchFET is also connected to the power supply potential wiring and the ground potential wiring by metal wiring for each block unit (macrocell group) composed of a plurality of macrocells. To do.
With the configuration as described above, the potential is maintained with almost no current flowing through Vcc2, Vcc3, Vcc4, GND2, GND3, and GND4.

  Here, the potential of Vcc1 to Vcc4 is set to 1.2V, the potential of GND1 to GND4 is set to 0V, and the threshold voltage Vth of each PchFET (the Pch auxiliary transistor 21 and the one in the macro cell) is set to −0.2V. When the threshold voltage Vth of each NchFET (Nch auxiliary transistor 11 and the one in the macro cell) is 0.2 V, the V point potential is 1.0 V and the G point potential is 0.2 V.

  As shown in FIG. 3, the semiconductor integrated circuit 1 according to the second embodiment has an H level output of 1.0 V and an L level output of 0.2 V, and operates in the range of 0.2 to 1.0 V. To do. A waveform S2 in FIG. 3 is obtained when the potential of Vcc1 is 1.2V, and a waveform S1 is obtained when the potential of Vcc1 is changed to 1.0V. Referring to FIG. 3, in the semiconductor integrated circuit 1 according to the second embodiment, Vcc1 varies from 1.2V to 1.0V or the potential of GND1 varies from 0V to 0.2V due to the influence of other macrocells. Even in this case, the gate potential of each Nch FET and each Pch FET does not change, and the transistor characteristics can be maintained substantially equal. Further, the V point potential is 1.0 V, the G point potential is 0.2 V, and the output delay of the inverter circuit hardly varies.

FIG. 4 is a diagram showing a layout of the semiconductor integrated device 1 according to the second embodiment.
4A is a layout view seen from the main surface of the semiconductor integrated device 1, FIG. 4B is a cross-sectional view at position B in FIG. 4A, and FIG. 4C is FIG. It is sectional drawing in the C position in (A), FIG.4 (D) is sectional drawing in the D position in FIG. 4 (A). 4A to 4D, 12a to 12d are N + fields, 15a and 15b are N-wells, 22a to 22d are P + fields, 31a to 31c are polysilicon, 32 is a contact, and 33a to 33e are metal wirings. Indicates.

  The semiconductor integrated circuit 1 according to the second embodiment is formed on a P-substrate. 4A to 4D, an Nch auxiliary transistor group 10A is formed on the P-well. The Nch auxiliary transistor 11 of the Nch auxiliary transistor group 10A has a source connected to the metal wiring 33a and a gate connected to Vcc2. The power supply potential is supplied from the drain of the Nch auxiliary transistor 11 to the PChFET 27 of the inverter circuit via the metal wiring 33b.

  The back gate of the Nch auxiliary transistor 11 is connected to the GND 4 by the P + field 22a. The back gate of the PChFET 27 is connected to Vcc3 by the N + field 12b on the N-well 15a in which the PChFET 27 is formed. An NchFET 17 is formed on the P-well, and a back gate of the NchFET 17 is connected to GND3 by a P + field 22c on the P-well.

  A Pch auxiliary transistor group 20A is formed on the N-well 15b. The back gate of the Pch auxiliary transistor 21 of the Pch auxiliary transistor group 20A is connected to Vcc4 by the N + field 12d. The Pch auxiliary transistor 21 has a source connected to the metal wiring 33e of GND1 and a gate connected to GND2. The ground potential is supplied from the drain of the Pch auxiliary transistor 21 to the NchFET 17 of the inverter circuit through the metal wiring 33d.

  As described above, in the second embodiment, since the power supply potential is supplied to the macro cell 3 via the Nch auxiliary transistor 11 in the semiconductor integrated circuit 1 including the macro cell 3, the cell due to the fluctuation of the power supply potential is used. Variations in delay can be reduced. Furthermore, since the ground potential is supplied to the macro cell 3 via the Pch auxiliary transistor 21, the fluctuation of the cell delay due to the fluctuation of the ground potential can be reduced.

Embodiment 3 FIG.
A third embodiment of the present invention will be described in detail with reference to FIG.
FIG. 5 is a circuit diagram showing the semiconductor integrated circuit 1 according to the third embodiment. The semiconductor integrated circuit 1 of the third embodiment is different from that of the second embodiment in that the Nch auxiliary transistor 11 is connected to the macro cell of the inverter circuit and the Pch auxiliary transistor 21 is not connected.

As shown in FIG. 5, an Nch auxiliary transistor 11 is connected to the macro cell 3 of the semiconductor integrated circuit 1. With such a configuration, the power supply potential is supplied to the macro cell 3 via the Nch auxiliary transistor 11.
Specifically, in the Nch auxiliary transistor 11, the gate potential connected to the first power supply potential wiring 6 becomes Vcc2, the source potential connected to the second power supply potential wiring 5 becomes Vcc1, the back gate potential becomes GND4, and from the drain. A power supply potential is supplied to the macro cell 3.
Note that GND 1 is connected to the back gate and source of the NchFET constituting the macro cell 3.

  Such a configuration is effective when the resistance of the metal wiring connected to GND in the semiconductor integrated circuit 1 is sufficiently low and the ground potential hardly increases. In such a case, even if the installation of the Pch auxiliary transistor 21 in the second embodiment is omitted, the variation in cell delay due to the variation in the power supply potential and the ground potential can be sufficiently reduced. Since the installation of the Pch auxiliary transistor 21 is omitted, the cell area in the semiconductor integrated circuit 1 can be made relatively small.

  As described above, in the third embodiment, since the power supply potential is supplied to the macrocell 3 via the Nch auxiliary transistor 11 in the semiconductor integrated circuit 1 including the macrocell 3, the cell due to the fluctuation of the power supply potential is used. Variations in delay can be reduced.

Embodiment 4 FIG.
A fourth embodiment of the present invention will be described in detail with reference to FIG.
FIG. 6 is a circuit diagram showing the semiconductor integrated circuit 1 according to the fourth embodiment. The semiconductor integrated circuit 1 of the fourth embodiment is different from that of the second embodiment in that the Pch auxiliary transistor 21 is connected to the macro cell of the inverter circuit and the Nch auxiliary transistor 11 is not connected.

As shown in FIG. 6, a Pch auxiliary transistor 21 is connected to the macro cell 3 of the semiconductor integrated circuit 1. With such a configuration, the macro cell 3 is supplied with the ground potential via the Pch auxiliary transistor 21.
Specifically, in the Pch auxiliary transistor 21, the gate potential connected to the first ground potential wiring 9 is GND2, the source potential connected to the second ground potential wiring 8 is GND1, the back gate potential is Vcc4, and from the drain A ground potential is supplied to the macro cell 3.
Note that Vcc1 is connected to the back gate and source of the PchFET constituting the macro cell 3.

  Such a configuration is effective when the resistance of the metal wiring connected to Vcc in the semiconductor integrated circuit 1 is sufficiently low and the power supply potential hardly drops. In such a case, even if the installation of the Nch auxiliary transistor 11 in the second embodiment is omitted, the variation in cell delay due to the variation in the power supply potential and the ground potential can be sufficiently reduced. Since the installation of the Nch auxiliary transistor 11 is omitted, the cell area in the semiconductor integrated circuit 1 can be made relatively small.

  As described above, in the fourth embodiment, since the ground potential is supplied to the macro cell 3 through the Pch auxiliary transistor 21 in the semiconductor integrated circuit 1 including the macro cell 3, the cell due to the fluctuation of the ground potential is used. Variations in delay can be reduced.

Embodiment 5. FIG.
A fifth embodiment of the present invention will be described in detail with reference to FIG.
FIG. 7A is a circuit diagram showing the semiconductor integrated circuit 1 in the fifth embodiment. In the semiconductor integrated circuit 1 of the fifth embodiment, the configuration of the macro cell 3 is different from those of the respective embodiments. FIG. 7B is a circuit diagram showing a semiconductor integrated circuit 1 having a conventional macro cell.

  As shown in FIG. 7A, an Nch auxiliary transistor 11 and a Pch auxiliary transistor 21 are connected to a conventional semiconductor integrated circuit 1 (shown in FIG. 7B). Specifically, the Nch auxiliary transistor 11 and the Pch auxiliary transistor 21 are connected to the macro cell 3 constituting the three-input NAND. With such a configuration, the macro cell 3 is supplied with the power supply potential via the Nch auxiliary transistor 11 and supplied with the ground potential via the Pch auxiliary transistor 21.

  As described above, also in the fifth embodiment, the power supply potential is supplied to the macro cell 3 through the Nch auxiliary transistor 11 in the semiconductor integrated circuit 1 including the macro cell 3 as in the first embodiment. Since the ground potential is supplied to the macro cell 3 via the Pch auxiliary transistor 21, fluctuations in cell delay due to fluctuations in the power supply potential and ground potential can be reduced.

Embodiment 6 FIG.
A sixth embodiment of the present invention will be described in detail with reference to FIGS.
FIG. 8 is a layout diagram showing the semiconductor integrated circuit 1 according to the sixth embodiment, and FIG. 9 is a circuit diagram thereof. The semiconductor integrated circuit 1 of the sixth embodiment is different from those of the above-described embodiments in that a plurality of macro cells 3A to 3D are arranged in the row direction.

  As shown in FIG. 9, in the semiconductor integrated circuit 1, macro cells 3B and 3D constituting an inverter circuit and macro cells 3A and 3C constituting a three-input NAND circuit are arranged in the row direction. Referring to FIG. 8, in semiconductor integrated circuit 1, a power supply potential is supplied to Vcc1 to Vcc4 and a ground potential is supplied to GND1 to GND4 via low-resistance metal wiring 33.

  Further, an Nch auxiliary transistor 11 and a Pch auxiliary transistor 21 are connected to each of the macro cells 3A to 3D. With such a configuration, each of the macro cells 3 </ b> A to 3 </ b> D is supplied with the power supply potential via the Nch auxiliary transistor 11 and supplied with the ground potential via the Pch auxiliary transistor 21.

In the sixth embodiment, the macrocells 3A to 3D are arranged at the same height in the row direction, and the Nch auxiliary transistor 11 and the Pch auxiliary transistor 21 are arranged there, so that the macrocells 3A to 3D are shared. Can be connected to Vcc1 to Vcc4 and GND1 to GND4.
In the sixth embodiment, the Nch auxiliary transistor 11 and the Pch auxiliary transistor 21 are connected to all the macrocells 3A to 3D. However, the Nch auxiliary transistor is used only for a specific macrocell among the plurality of macrocells 3A to 3D. 11 and the Pch auxiliary transistor 21 can also be connected.

  As described above, in the sixth embodiment as well, in the semiconductor integrated circuit 1 including the macro cell 3, the power supply potential is supplied to the macro cell 3 through the Nch auxiliary transistor 11 as in the first embodiment. Since the ground potential is supplied to the macro cell 3 via the Pch auxiliary transistor 21, fluctuations in cell delay due to fluctuations in the power supply potential and ground potential can be reduced.

Embodiment 7 FIG.
A seventh embodiment of the present invention will be described in detail with reference to FIGS.
FIG. 10 is a layout diagram showing the semiconductor integrated circuit 1 according to the seventh embodiment. In the semiconductor integrated circuit 1 of the seventh embodiment, a plurality of macro cells 3A to 3D having a large cell size, such as a gate array, are arranged in the row direction. A plurality of macro cells such as standard macro cells are arranged in the row direction. This is different from that of the sixth embodiment.

  Referring to FIG. 10, in semiconductor integrated circuit 1, macro cells 3A to 3D serving as basic cells used in a gate array or the like are arranged in the row direction. The macro cells 3A to 3D serving as basic cells are configured with the same cell size and the same transistor arrangement. The user changes the metal wiring and forms the desired semiconductor integrated circuit 1.

Also in the seventh embodiment, the Nch auxiliary transistor 11 and the Pch auxiliary transistor 21 are connected to the macro cells 3A to 3D (basic cells), respectively. That is, the semiconductor integrated circuit 1 includes an Nch auxiliary transistor group 10A in which a plurality of Nch auxiliary transistors 11 are arranged in the row direction, and a Pch auxiliary transistor group 20A in which a plurality of Pch auxiliary transistors 21 are arranged in the row direction. , Is provided.
With such a configuration, it becomes possible to supply the power supply potential to each of the macro cells 3 </ b> A to 3 </ b> D via the Nch auxiliary transistor 11 and supply the ground potential via the Pch auxiliary transistor 21.

  FIG. 11 is a circuit diagram when a three-input NAND is formed using two macro cells 3 (basic cells) among the four macro cells 3A to 3D (basic cells). As shown in FIG. 11, the same number of Nch auxiliary transistors 11 and Pch auxiliary transistors 21 as the number of microcells 3 (basic cells) used are used. That is, when forming a circuit using two microcells 3 (basic cells) as shown in FIG. 11 from the gate array of FIG. 10, two Nch auxiliary transistors 11 and two Pch auxiliary transistors 21 are used.

  As described above, in the seventh embodiment as well, in the semiconductor integrated circuit 1 including the macro cell 3, the power supply potential is supplied to the macro cell 3 via the Nch auxiliary transistor 11 as in the first embodiment. Since the ground potential is supplied to the macro cell 3 via the Pch auxiliary transistor 21, fluctuations in cell delay due to fluctuations in the power supply potential and ground potential can be reduced.

  It should be noted that the present invention is not limited to the above-described embodiments, and within the scope of the technical idea of the present invention, the embodiments can be modified as appropriate in addition to those suggested in the embodiments. Is clear. In addition, the number, position, shape, and the like of the constituent members are not limited to the above embodiments, and can be set to a number, position, shape, and the like that are suitable for carrying out the present invention.

1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 2 of this invention. 3 is a graph showing an output waveform in the semiconductor integrated circuit of FIG. 2. FIG. 3 is a layout diagram illustrating the semiconductor integrated circuit of FIG. 2. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 3 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 4 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 5 of this invention. FIG. 10 is a layout diagram illustrating a semiconductor integrated circuit according to a sixth embodiment of the present invention. FIG. 9 is a circuit diagram showing the semiconductor integrated circuit of FIG. 8. FIG. 10 is a layout diagram illustrating a semiconductor integrated circuit according to a seventh embodiment of the present invention. FIG. 11 is a circuit diagram showing the semiconductor integrated circuit of FIG. 10. It is a circuit diagram which shows the conventional semiconductor integrated circuit. 13 is a timing chart showing control performed in the semiconductor integrated circuit of FIG.

Explanation of symbols

1 Semiconductor integrated circuit,
2A-2C macrocell group,
3, 3A-3D, 3a-3m macrocell,
5, 5A, 5B Second power supply potential wiring (second power supply potential wiring),
6 first power supply potential wiring (first power supply potential wiring),
8, 8A, 8B Second ground potential wiring (second ground potential wiring),
9 First ground potential wiring (first ground potential wiring),
10A-10C Nch auxiliary transistor group,
11 Nch auxiliary transistor (N-channel field effect transistor),
20A-20C Pch auxiliary transistor group,
21 Pch auxiliary transistor (P-channel field effect transistor),
31, 31a-31c polysilicon, 32 contacts,
33, 33a to 33e Metal wiring.

Claims (12)

A semiconductor integrated circuit having a macro cell,
Comprising an N-channel field effect transistor connected to the macrocell;
A semiconductor integrated circuit, wherein a power supply potential is supplied to the macro cell via the N-channel field effect transistor. 2. The N-channel field effect transistor according to claim 1, wherein a gate is connected to a first power supply potential wiring, a source is connected to a second power supply potential wiring, and a drain is connected to the macro cell. The semiconductor integrated circuit as described. A plurality of N-channel field effect transistors respectively connected to the plurality of microcells;
3. The plurality of N-channel field effect transistors each having a gate connected to the first power supply potential wiring and a source connected to the second power supply potential wiring. The semiconductor integrated circuit as described. 4. The semiconductor integrated circuit according to claim 2, wherein the first power supply potential wiring and the second power supply potential wiring are not connected in the macro cell. 5. A P-channel field effect transistor connected to the macro cell;
5. The semiconductor integrated circuit according to claim 1, wherein a ground potential is supplied to the macro cell via the P-channel field effect transistor. 6. The P-channel field effect transistor according to claim 5, wherein a gate is connected to a first ground potential wiring, a source is connected to a second ground potential wiring, and a drain is connected to the macro cell. The semiconductor integrated circuit as described. A plurality of the P-channel field effect transistors respectively connected to the plurality of microcells;
7. The plurality of P-channel field effect transistors each having a gate connected to the first ground potential wiring and a source connected to the second ground potential wiring. The semiconductor integrated circuit as described. 8. The semiconductor integrated circuit according to claim 6, wherein the first ground potential wiring and the second ground potential wiring are not connected in the macro cell. A semiconductor integrated circuit having a macro cell,
A P-channel field effect transistor connected to the macrocell;
A semiconductor integrated circuit characterized in that a ground potential is supplied to the macro cell via the P-channel field effect transistor. 10. The P-channel field effect transistor according to claim 9, wherein a gate is connected to the first ground potential wiring, a source is connected to the second ground potential wiring, and a drain is connected to the macro cell. The semiconductor integrated circuit as described. A plurality of the P-channel field effect transistors respectively connected to the plurality of microcells;
11. The plurality of P-channel field effect transistors, wherein each gate is connected to the first ground potential wiring and each source is connected to the second ground potential wiring. The semiconductor integrated circuit as described. 12. The semiconductor integrated circuit according to claim 10, wherein the first ground potential wiring and the second ground potential wiring are not connected in the macro cell.

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