JP2006189946A - Random number generation circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a random number generation circuit and a semiconductor integrated circuit capable of realizing speedup and reduction in size at the same time. <P>SOLUTION: This random number generation circuit 1 is provided with a noise generation source 2 generating a noise signal, a filter 3 extracting a part of a frequency band of the noise signal, and a comparator 4 amplifying a signal difference between a part of the noise signal frequency band and a reference signal for generating a random number signal. The random number generation circuit 1 is installed on a base board for the semiconductor integrated circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a random number generation circuit and a semiconductor integrated circuit, and more particularly to a random number generation circuit that generates a random number signal based on a physical phenomenon and a semiconductor integrated circuit including the random number generation circuit.

  Random numbers are widely used in fields such as information communication encryption and computer simulation. A commonly used random number is an arithmetic random number obtained by simulation based on a certain algorithm. In this arithmetic random number, although the generation circuit can be made small and simple, if the initial value (seed) used for calculation is constant, the output random number is always the same value.

  On the other hand, a physical random number generated by digitizing a physical fluctuation phenomenon different from an arithmetic random number is known. In the physical random number, unlike the arithmetic random number, an initial value can be generated based on a physical phenomenon. Therefore, there is no fixed initial value, and the output random number value is completely random.

  As a physical random number generation method, Patent Literature 1 below discloses a method of generating a random number using noise existing in an apparatus. According to this method, a very good quality random number can be generated.

The following non-patent document reports an element capable of generating a large noise signal when randomizing.
JP-A-11-85472 R. Ohba et al., Tech. Dig. IEDM 2003, p.745.

  However, in the random number generation method disclosed in Patent Document 1, a good quality random number can be generated. However, a signal output from a noise source is small, and a large amplification is required for the output signal. For this reason, no consideration has been given in that the scale of the amplification circuit of the random number generation circuit is increased, and the degree of integration of the semiconductor integrated circuit on which the random number generation circuit is further reduced.

  In order to solve such a technical problem, it is effective to apply the element reported in Non-Patent Document 1. However, since this type of element has a 1 / f characteristic, when applied to the random number generation method disclosed in Patent Document 1, it is necessary to adjust the offset in the analog-to-digital conversion process after amplification. Become. That is, it is necessary to add a feedback circuit to the random number generation circuit, which increases the scale of the random number generation circuit. As a result, in a semiconductor integrated circuit equipped with a random number generation circuit, the degree of integration decreases. In addition, as a result of providing the feedback circuit in the random number generation circuit, the output speed of the random number becomes slow, and it is difficult to realize an increase in the operation speed of the semiconductor integrated circuit.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a random number generation circuit capable of increasing the generation speed of random numbers while realizing downsizing. is there.

  Furthermore, an object of the present invention is to provide a semiconductor integrated circuit that can realize a reduction in size and increase in speed of a random number generation circuit, and increase in operating speed while improving the degree of integration. is there.

  A first feature according to an embodiment of the present invention is that, in a random number generation circuit, a noise generation source that generates a noise signal, a filter that extracts a part of the frequency band of the noise signal, and a frequency band of the noise signal And a comparator that generates a random number signal obtained by amplifying the signal difference between the unit and the reference signal.

  A second feature according to the embodiment of the present invention is that, in the random number generation circuit, a noise generation source that generates a noise signal, a low-pass filter that extracts a low frequency band of the frequency band of the noise signal, and a low frequency of the noise signal A comparator that generates a random number signal obtained by amplifying the signal difference between the band and the noise signal.

  A third feature according to the embodiment of the present invention is that, in the random number generation circuit, a noise generation source that generates a noise signal, a high-pass filter that extracts a high frequency band of the noise signal, and a high frequency of the noise signal A comparator that generates a random number signal obtained by amplifying the signal difference between the band and the reference signal.

  A fourth feature according to the embodiment of the present invention is that, in the random number generation circuit, a noise generation source that generates a noise signal, a high-pass filter that extracts a high frequency band of the noise signal, and a high frequency of the noise signal A delay circuit that generates a reference signal having a delayed band; and a comparator that generates a random number signal obtained by amplifying a signal difference between the high frequency band of the noise signal and the reference signal.

  A fifth feature according to the embodiment of the present invention is that in a semiconductor integrated circuit, a noise generation source that generates a noise signal, a filter that extracts a part of the frequency band of the noise signal, and a frequency band of the noise signal are provided. A random number generation circuit including a comparator that generates a random number signal obtained by amplifying a signal difference between the unit and the reference signal, and a substrate on which the random number generation circuit is mounted.

  According to the present invention, it is possible to provide a random number generation circuit capable of realizing a reduction in size and increasing a random number generation speed.

  Furthermore, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of realizing a reduction in size and an increase in speed of a random number generation circuit and an increase in operation speed while improving an integration degree. it can.

  Hereinafter, a random number generation circuit and a semiconductor integrated circuit according to embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
[Configuration of random number generator]
As shown in FIG. 1, a random number generation circuit 1 according to a first embodiment of the present invention includes a noise generation source 2 that generates a noise signal, a filter that extracts a part of the frequency band of the noise signal, And a comparator 4 for generating a random number signal obtained by amplifying a signal difference between a part of the frequency band of the signal and the reference signal. In the first embodiment, a low-pass filter 3 that extracts a low frequency band of a noise signal is used as a filter.

  When a noise signal is generated in the noise generation source 2 of the random number generation circuit 1, this noise signal is output, and the noise signal is divided into two systems immediately after output. In one system, the noise signal is directly input to the input terminal of the comparator 4 as a reference signal. In the other system, the noise signal is input to the input terminal of the comparator 4 through the low-pass filter 3.

  FIG. 2 shows the relationship between the output waveform (symbol A) of the noise signal output from the noise source 2 and the output waveform (symbol B) of the low-pass filter 3. In FIG. 2, the horizontal axis represents time, and the vertical axis represents voltage or current. The high frequency component of the noise signal output from the noise generation source 2 is removed by passing through the low pass filter 3. In the low-pass filter 3, the cutoff frequency is appropriately selected, and a noise signal having a voltage value or current value near the center of the noise signal output from the noise generation source 2 can be generated. .

  In the comparator 4 shown in FIG. 1, when the noise signal output from the noise generation source 2 is input as a reference signal and the noise signal output from the low-pass filter 3 is input, the magnitudes of both signals are compared. The signal difference is amplified, and a digital signal corresponding to the signal difference or a signal close thereto is output as a random number signal. The comparator 4 outputs one of the binary voltages “high level” and “low level” depending on the magnitude of both signals.

  If the noise signal generated in the noise generation source 2 is random, the noise signal output from the noise generation source 2 is randomly distributed between the high time and the low time with respect to the noise signal output from the low-pass filter 3. Therefore, the “high level” time and the “low level” time of the random number signal output from the comparator 4 fluctuate randomly. A 1-bit random number output can be obtained by latching the random number signal output from the comparator 4 with an appropriate clock signal in a latch circuit provided inside or outside the random number generating circuit 1 (not shown).

[Configuration of noise source]
As shown in FIG. 3, the noise generation source 2 of the random number generation circuit 1 includes a resistance element 23 having one end connected to the first power supply terminal 21, one end connected to the other end of the resistance element 23, and the other end A noise element 24 connected to the second voltage terminal, and an output terminal 25 connected to the other end of the resistance element 23 and one end of the noise element 24 are provided. That is, the noise generation source 2 includes a resistance element 23 and a noise element 24 that are electrically connected in series between the first power supply terminal 21 and the second power supply terminal 22. The output terminal 25 is connected to an intermediate node between the output terminals 25 and 24. The voltage value or the current value supplied from the first power supply terminal 21 is different from the voltage value or the current value supplied from the second power supply terminal 22, and one of them is small or larger than the other. May be.

  In the first embodiment, a large fluctuation can be given to the noise signal output from the noise source 2. Here, “fluctuation” is used in the sense that when a constant voltage or a constant current is applied to the noise element 24, the noise signal (voltage value or current value) output from the output terminal 25 varies greatly. The noise generation source 2 generates a noise signal having a fluctuation of 0.1% or more in a desired sampling time with respect to the average current or average voltage value of the output frequency of the random number signal output from the random number generation circuit 1. It is preferable. Here, the desired sampling time depends on the output bit rate of the random number generation circuit 1 and is the reciprocal of the frequency of the output bit rate.

  As shown in FIG. 4, the noise element 24 includes a nanoscale fine electron channel 241 and an electron trap 242 that is disposed near the electron channel 241 and generates a noise signal. The noise element 24 is, for example, an insulated gate field effect transistor (hereinafter simply referred to as “IGFET”). The electron channel 241 is a channel between the source region and the drain region, and the electron trap 242 is an electron trap in the gate insulating film.

  When the electron e is captured by the electron trap 242, the electron e passing through the electron channel 241 is affected by the Coulomb field generated by the electron e, and the conductivity of the electron channel 241 changes. Capture or emission of the electrons e in the electron trap 242 is performed between the electron channel 241 and an energy barrier existing between the electron channel 241 and the electron trap 242. Since the capture or emission of the electrons e is randomly generated thermally, the conductivity of the electron channel 241 fluctuates randomly. As a result, even if a constant current or a constant voltage is supplied to the electronic channel 241, a noise signal in which the current value or the voltage value fluctuates randomly in the electronic channel 241 can be generated.

  Further, as shown in FIG. 5, the noise element 24 is disposed on the first electrode 245, the first electrode 245, the insulating film 246 that generates a noise signal by pseudo breakdown, and the insulating film 246. A second electrode 247 can also be provided. The noise element 24 is a capacitor, for example, and has a structure in which an insulating film 246 is sandwiched between the first electrode 245 and the second electrode 247. In the capacitor, when electrical stress is applied to the insulating film 246, the conductivity of the insulating film 246 is slightly increased. At this time, when a constant current or a constant voltage is supplied to the insulating film 246 (between the first electrode 245 and the second electrode 247), electrons e are randomly generated between the electron traps in the insulating film 246 by a tunnel phenomenon. The current value or voltage value which moves and fluctuates greatly is obtained. A noise signal can be generated by the fluctuation of the current value or the voltage value.

  Each of the first electrode 245 and the second electrode 247 is formed of a conductive material such as single crystal silicon, polycrystalline silicon, amorphous silicon, or metal. The insulating film 246 is made of an insulating material such as a single layer film such as a silicon oxide film or a silicon nitride film, or a composite film obtained by stacking them.

[Configuration of low-pass filter]
As shown in FIG. 6, the low-pass filter 3 of the random number generation circuit 1 has a resistance element 33 having one end connected to the input terminal 31 and the other end connected to the output terminal 32, and the other end of the resistance element 33. A first electrode 341 is connected between the output terminal 32 and a capacitor 35 having a reference power source (for example, ground potential) 35 and a second electrode 342 connected thereto.

  In the low-pass filter 3, the cut-off frequency at which the noise signal output from the output terminal 32 decreases by about 3 dB can be obtained by approximately 1 / (2πCR). Therefore, in the low-pass filter 3, the intensity of the noise signal input to the comparator 4 can be adjusted by adjusting the resistance value R of the resistance element 33 and the capacitance value C of the capacitor 34.

  In this low-pass filter 3, a node at the other end of the resistance element 33 having one end connected to the input terminal 31 is connected to the output terminal 32, and a capacitor 34 is inserted between this node and the reference power supply 35. Noise generated in the reference power supply 35 is not added to the noise signal. That is, the low-pass filter 3 is a one-line signal input that receives a noise signal from the input terminal 31.

[Comparator configuration]
As shown in FIG. 7, the comparator 4 of the random number generation circuit 1 is connected to a power supply terminal 41 and a reference power supply 42, and has two first input terminals 43 and second input terminals 44, and one output terminal. 47, first channel conductivity type IGFETs 451 to 454, and second channel conductivity type IGFETs 461 to 464. In the first embodiment, the IGFET is used to mean both a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The first channel conductivity type is a p-channel conductivity type, and the second channel conductivity type is an n-channel conductivity type.

  The source region of the first channel conductivity type IGFET 451 is connected to the power supply terminal 41, the drain region is connected to the drain region of the second channel conductivity type IGFET 461, and the gate electrode is connected to the gate electrode of the second channel conductivity type IGFET 452. Has been. The source region of the first channel conductivity type IGFET 452 is connected to the power supply terminal 41, and the drain region is connected to the drain region of the second channel conductivity type IGFET 462.

  The source region of the second channel conductivity type IGFET 461 is connected to the reference power supply 42, and the gate electrode is connected to the first input terminal 43. The source region of the second channel conductivity type IGFET 462 is connected to the reference power supply 42, and the gate electrode is connected to the second input terminal 44.

  The source region of the first channel conductivity type IGFET 453 is connected to the power supply terminal 41, the drain region is connected to the drain region and the gate electrode of the second channel conductivity type IGFET 463, and the gate electrode is the gate of the first channel conductivity type IGFET 451. The electrode and drain regions are connected to the gate electrode of the first channel conductivity type IGFET 452. The source region of the second channel conductivity type IGFET 463 is connected to the reference power source 42.

  The source region of the first channel conductivity type IGFET 454 is connected to the power supply terminal 41, the drain region is connected to the drain region of the second channel conductivity type IGFET 464, and the gate electrode is connected to the drain region of the first channel conductivity type IGFET 452. Has been. The source region of the second channel conductivity type IGFET 464 is connected to the reference power source 42, and the gate electrode is connected to the gate electrode of the second channel conductivity type IGFET 463.

  The output terminal 47 is connected to the drain region of the first channel conductivity type IGFET 454 and the drain region of the second channel conductivity type IGFET 464.

  In the comparator 4 having such a configuration, when the signal (voltage) input to the first input terminal 43 is higher than the signal (voltage) input to the second input terminal 44, the output terminal 47 Is output at a low level (or close to it). Conversely, when the signal input to the first input terminal 43 is lower than the signal input to the second input terminal 44, a high level voltage (or a voltage close thereto) is output to the output terminal 47. .

[Configuration of semiconductor integrated circuit]
As shown in FIG. 8, the random number generation circuit 1 is mounted on a substrate 11 to construct a semiconductor integrated circuit 10. As the substrate 11, a semiconductor substrate such as a single crystal silicon substrate or a semi-insulating substrate, an insulating substrate having a semiconductor active layer on the surface, or the like can be used practically.

  The semiconductor integrated circuit 10 can be mounted in various circuits depending on the application, but in the first embodiment, in addition to the random number generation circuit 1, a memory circuit (RAM) 13 capable of sequentially reading and writing, and a read-only memory A circuit (ROM) 14, an electrical nonvolatile memory circuit (EEPROM) 15, a cryptographic processing auxiliary calculation unit 16 and a calculation unit 17 are mounted. These circuits are connected to each other through the data bus 12.

  Further, a power supply circuit 181, a reference power supply circuit 182, a reset circuit 183, a clock signal generation circuit 184, and an input / output interface circuit 185 are connected to the calculation unit 17. Note that these power supply circuits 181 and the like do not necessarily have to be mounted as a circuit on the substrate 11, and may be input from the outside as power supplies or signals.

  The semiconductor integrated circuit 10 is incorporated in an IC card, a mobile phone, a computer, etc., and performs cryptographic processing. Furthermore, since the random number output from the random number generation circuit 1 according to the first embodiment is a true random number, for hacking such as measuring the power consumption of the semiconductor integrated circuit 10 and reading the internal encryption key, It can be used for applications that disturb power consumption.

  As described above, in the random number generation circuit 1 according to the first embodiment, one of the noise signals output from the noise generation source 2 is directly input to the comparator 4 and the other is input to the comparator 4 through the low-pass filter 3. Since the noise signal is amplified based on the signal difference in the comparator 4 based on the signal difference, an amplifier circuit having a complicated structure that repeatedly amplifies a minute noise signal can be eliminated. Therefore, it is possible to provide the random number generation circuit 1 capable of realizing a reduction in size and an increase in the random number generation speed.

  Furthermore, since the random number generation circuit 1 can be reduced in size and increased in speed, it is possible to provide the semiconductor integrated circuit 10 capable of increasing the operation speed while improving the degree of integration.

(Second Embodiment)
The second embodiment of the present invention describes an example in which an input circuit is added to the random number generation circuit 1 according to the first embodiment.

[Configuration of input circuit]
As shown in FIG. 9, the random number generation circuit 1 according to the second embodiment includes an input circuit 5 between a noise generation source 2, a low-pass filter 3, and a comparator 4. When the noise source 2 and the low-pass filter 3 and the comparator 4 are directly connected, there is a possibility that a sufficient noise signal cannot be obtained from the noise source 2 due to the influence of the low-pass filter 3 and the comparator 4. The input circuit 5 can prevent such a phenomenon.

  As shown in FIG. 10, in the input circuit 5, the noise signal output from the noise generation source 2 is input to the control electrode through the input terminal 53, the first main electrode is connected to the power supply terminal 51, and the second main A transistor 55 having an electrode connected to the low-pass filter 3 and the comparator 4 through the output terminal 54 and a resistance element 56 having one end connected to the second main electrode of the transistor 55 and the other end connected to the reference power source 52 are provided. A series circuit of a transistor 55 and a resistance element 56 is used. In the second embodiment, the transistor 55 is a first channel conductivity type IGFET, that is, a p-channel conductivity type IGFET. Therefore, the control electrode is a gate electrode, the first main electrode is a source region, and the second main electrode is a drain region.

  In the random number generation circuit 1 and the semiconductor integrated circuit 10 according to the second embodiment, since the noise element 24 that generates a large noise signal is used for the noise generation source 2, the gain of the input circuit 5 is not necessary. The input circuit 5 can be reduced in size, and a sufficient noise signal can be generated from the noise generation source 2.

[Modification of input circuit]
As shown in FIG. 11, in the input circuit 5, the noise signal output from the noise generating source 2 is input to the control electrode through the input terminal 53, the first main electrode is connected to the reference terminal 52, and the second main A transistor 57 having an electrode connected to the low-pass filter 3 and the comparator 4 through the output terminal 54 and a resistance element 56 having one end connected to the second main electrode of the transistor 57 and the other end connected to the power supply terminal 51 are provided. The transistor 57 and the resistance element 56 are configured in series. In the modification of the second embodiment, the transistor 57 uses a second channel conductivity type IGFET, that is, an n channel conductivity type IGFET. Therefore, the control electrode is a gate electrode, the first main electrode is a source region, and the second main electrode is a drain region.

(Third embodiment)
The third embodiment of the present invention describes an example in which a buffer is added to the random number generation circuit 1 according to the second embodiment.

[Buffer configuration]
As shown in FIG. 12, the random number generation circuit 1 according to the third embodiment includes a buffer 6 having an input terminal connected to the output terminal (47) of the comparator 4. In the comparator 4 shown in FIG. 6 described above, when there is not so much voltage difference between the signals input to the first input terminal 43 and the second input terminal 44, the voltage is distributed around the weak circuit sensitivity. The output voltage does not completely reach the high level or the low level. The buffer 6 can correct such a phenomenon.

  As shown in FIG. 13, the buffer 6 is configured by an inverter having an input terminal 63 and an output terminal 64. The inverter is configured by a series circuit of a first channel conductivity type IGFET 65 and a second channel conductivity type IGFET 66 disposed between a power supply terminal 61 and a reference power supply 62. The first channel conductivity type IGFET 65 is a p-channel conductivity type IGFET, and the second channel conductivity type IGFET 66 is an n-channel conductivity type IGFET.

  In the buffer 6 constituted by the inverter, the signal waveform of the random number signal input to the input terminal 63 can be shaped, and the random number signal can be extracted from the output terminal 64 as a digital signal.

(Fourth embodiment)
The fourth embodiment of the present invention describes an example in which the random number generation circuit 1 according to the second embodiment includes a high-pass filter instead of the low-pass filter 3.

[Configuration of random number generator]
As shown in FIG. 14, the random number generation circuit 1 according to the fourth embodiment includes a noise generation source 2 that generates a noise signal, an input circuit 5, and a filter that extracts a part of the frequency band of the noise signal. And a comparator 4 for generating a random number signal obtained by amplifying a signal difference between a part of the frequency band of the noise signal and the reference signal. In the first embodiment, a high-pass filter 7 that extracts a high frequency band of a noise signal is used as the filter.

  When a noise signal is generated in the noise generation source 2 of the random number generation circuit 1, this noise signal is output. The noise signal is input to the high pass filter 7 through the input circuit 5, and the low frequency band of the noise signal is increased in the high pass filter 7. This noise signal is input to the input terminal of the comparator 4. In the fourth embodiment, the random number generation circuit 1 further includes a reference voltage generation circuit 8, and the reference voltage output from the reference voltage generation circuit 8 is input to the input terminal of the comparator 4.

  A reference power supply (ground potential) can be used for the reference voltage output from the reference voltage generation circuit 8, but depending on the type of the operational amplifier used as the comparator 4, there is no sensitivity with respect to the magnitude of the voltage around the reference power supply. If the sensitivity is to be obtained, the circuit scale of the comparator 4 increases. In the fourth embodiment, the reference voltage output from the reference voltage generation circuit 8 and used in the high-pass filter 7 and the comparator 4 is set to a value in the vicinity of the most sensitive voltage value of the comparator 4 for reference. The circuit scale of the voltage generation circuit 8 is reduced.

  FIG. 15 shows the relationship between the output waveform (symbol C) of the noise signal output from the high-pass filter 7 and the output waveform (symbol D) of the reference voltage output from the reference voltage generation circuit 8. In FIG. 15, the horizontal axis represents time, and the vertical axis represents voltage or current. The low frequency component of the noise signal output from the noise generation source 2 is removed by passing through the high pass filter 7. The noise signal that has passed through the high-pass filter 7 becomes a noise signal that fluctuates around the reference voltage by appropriately selecting the cutoff frequency.

  By comparing the noise signal that has passed through the high-pass filter 7 and the reference voltage in the comparator 4, the comparator 4 can output a random signal composed of a digital signal amplified in accordance with the voltage difference between the signals or a signal close thereto. it can. If the noise signal output from the noise generation source 2 is random, the time when the voltage of the noise signal that has passed through the high-pass filter 7 is high is randomly distributed with respect to the reference voltage, and the time when the voltage is low is relative to the reference voltage. Distributed randomly. Therefore, the high level time and low level time of the random number signal output from the comparator 4 both have random fluctuations. As described above, this random number signal is latched at an appropriate clock to obtain a 1-bit random number output.

  Actually, the center voltage of the noise signal after passing through the high-pass filter 7 may fluctuate around a voltage value slightly deviated from the reference voltage due to characteristics of the random number generation circuit 1 and external influences. In such a case, it can be avoided by adjusting the reference voltage input to the comparator 7 to an appropriate value.

  Further, when the voltage swing of the random number signal output from the comparator 4 cannot be obtained sufficiently, the same buffer 6 as the buffer 6 provided in the random number generation circuit 1 according to the third embodiment is used as the comparator 4. May be disposed in the output stage.

[Configuration of high-pass filter]
As shown in FIG. 16, the high-pass filter 7 has a capacitor 73 in which the first electrode 731 is connected to the input terminal 71 and the second electrode 732 is connected to the output terminal 72, and a second of the capacitor 73. A resistor element 74 having one end connected between the electrode 732 and the output terminal 72 and having the other end connected to a power supply terminal (output terminal of the reference voltage generation circuit 8) 75 is provided.

  In the high-pass filter 7, the cut-off frequency at which the noise signal output from the output terminal 72 decreases by about 3 dB can be obtained by approximately 1 / (2πCR). Therefore, in the high-pass filter 7, the intensity of the noise signal input to the comparator 4 can be adjusted by adjusting the resistance value R of the resistance element 74 and the capacitance value C of the capacitor 73.

  In the random number generation circuit 1 and the semiconductor integrated circuit 10 according to the fourth embodiment configured as described above, the same effects as those obtained by the random number generation circuit 1 and the semiconductor integrated circuit 10 according to the second embodiment are obtained. An effect can be obtained.

(Fifth embodiment)
The fifth embodiment of the present invention describes an example in which a reference voltage is generated by a delay circuit in the random number generation circuit 1 according to the fourth embodiment.

[Configuration of random number generator]
As shown in FIG. 17, the random number generation circuit 1 according to the fifth embodiment includes a noise generation source 2 that generates a noise signal, a high-pass filter 7 that extracts a high frequency band of the noise signal, and noise. A delay circuit 9 that generates a reference signal obtained by delaying the high frequency band of the signal, and a comparator 4 that generates a random number signal obtained by amplifying a signal difference between the high frequency band of the noise signal and the reference signal are provided.

  When a noise signal is generated in the noise generation source 2 of the random number generation circuit 1, this noise signal is output. The noise signal is divided into two systems after passing through the input circuit 5 and the high-pass filter 7. In one system, the noise signal is directly input to the input terminal of the comparator 4. In the other system, the noise signal is input to the input terminal of the comparator 4 as a reference voltage through the delay circuit 9.

  FIG. 18 shows the relationship between the output waveform (symbol E) of the noise signal output from the high pass filter 7 and the output waveform (symbol F) of the delay circuit 9. In FIG. 18, the horizontal axis represents time, and the vertical axis represents voltage or current.

  In the comparator 4, when the noise signal output from the high-pass filter 7 is input and the reference voltage output from the delay circuit 9 is input, the magnitudes of both signals are compared, and the signal difference is amplified. A digital signal corresponding to the signal difference or a signal close thereto is output as a random number signal. A 1-bit random number output can be obtained by latching the random number signal output from the comparator 4 with an appropriate clock signal.

  In the random number generation circuit 1 and the semiconductor integrated circuit 10 according to the fifth embodiment configured as described above, the same effect as that obtained by the random number generation circuit 1 and the semiconductor integrated circuit 10 according to the second embodiment is obtained. An effect can be obtained.

  The present invention is not limited to the embodiment described above. For example, the low-pass filter 3 and the high-pass filter 7 constituting the random number generation circuit 1 are examples of circuit configurations, and the present invention is not particularly limited as long as it has a similar function. Absent. Further, according to the present invention, a resistor element, a capacitor, or the like is not particularly manufactured as an element, but a resistor element or a capacitor may be manufactured using a parasitic resistance or a parasitic capacitor of a wiring arranged on the semiconductor integrated circuit 10.

1 is a circuit block diagram of a random number generation circuit according to a first embodiment of the present invention. It is a figure which shows the output waveform of the noise generation source and low-pass filter of the random number generation circuit shown in FIG. It is a circuit diagram of the noise generation source of the random number generation circuit shown in FIG. It is a block diagram which shows an example of the noise element of the noise generation source shown in FIG. It is a block diagram which shows another example of the noise element of the noise generation source shown in FIG. FIG. 2 is a circuit diagram of a low pass filter of the random number generation circuit shown in FIG. 1. FIG. 2 is a circuit diagram of a comparator of the random number generation circuit shown in FIG. 1. It is a functional circuit block diagram of the semiconductor integrated circuit carrying the random number generation circuit shown in FIG. It is a circuit block diagram of the random number generation circuit which concerns on the 2nd Embodiment of this invention. FIG. 10 is a circuit diagram of an input circuit of the random number generation circuit shown in FIG. 9. FIG. 10 is a circuit diagram of an input circuit showing another example of the random number generation circuit shown in FIG. 9. It is a circuit block diagram of the random number generation circuit which concerns on the 3rd Embodiment of this invention. FIG. 13 is a circuit diagram of a buffer of the random number generation circuit shown in FIG. 12. It is a circuit block diagram of the random number generation circuit which concerns on the 4th Embodiment of this invention. FIG. 15 is a diagram illustrating output waveforms of a high-pass filter and a reference voltage generation circuit of the random number generation circuit illustrated in FIG. 14. It is a circuit diagram of the high pass filter of the random number generation circuit shown in FIG. It is a circuit block diagram of the random number generation circuit which concerns on the 5th Embodiment of this invention. It is a figure which shows the output waveform of the high-pass filter and delay circuit of the random number generation circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Random number generation circuit 2 Noise generation source 21 1st power supply terminal 22 2nd power supply terminal 23, 33, 56, 74 Resistance element 24 Noise element 25, 32, 47, 54, 64, 72 Output terminal 241 Electronic channel 242 Electron Traps 245, 341 First electrode 246 Insulating film 247, 342 Second electrode 3 Low pass filter 31, 53, 63, 71 Input terminal 34, 73 Capacitor 35, 42, 52, 62 Reference power supply 4 Comparator 41, 51, 61 Power supply terminal 43 First input terminal 44 Second input terminal 451 to 454, 65 First channel conductivity type IGFET
461-464, 66 Second channel conductivity type IGFET
DESCRIPTION OF SYMBOLS 5 Input circuit 55, 57 Transistor 6 Buffer 7 High pass filter 8 Reference voltage generation circuit 9 Delay circuit 10 Semiconductor integrated circuit 11 Substrate 13-15 Memory circuit 16 Auxiliary operation part for encryption processing 17 Operation part

Claims (14)

A noise source that generates a noise signal;
A filter for extracting a part of the frequency band of the noise signal;
A comparator that generates a random number signal obtained by amplifying a signal difference between a part of the frequency band of the noise signal and a reference signal;
A random number generation circuit comprising: A noise source that generates a noise signal;
A low-pass filter for extracting a low frequency band of the noise signal;
A comparator that generates a random number signal obtained by amplifying a signal difference between a low frequency band of the noise signal and the noise signal;
A random number generation circuit comprising: A noise source that generates a noise signal;
A high-pass filter that extracts a high frequency band of the noise signal;
A comparator for generating a random signal obtained by amplifying a signal difference between a high frequency band of the noise signal and a reference signal;
A random number generation circuit comprising: A noise source that generates a noise signal;
A high-pass filter that extracts a high frequency band of the noise signal;
A delay circuit for generating a reference signal obtained by delaying a high frequency band of the noise signal;
A comparator that generates a random number signal obtained by amplifying a signal difference between a high frequency band of the noise signal and the reference signal;
A random number generation circuit comprising: A noise signal output from the noise generation source is input to a control electrode, a first main electrode is connected to a first power source, a second main electrode is connected to the filter and the comparator, and the transistor 5. The circuit according to claim 1, further comprising an input circuit in which one end is connected to the second main electrode of the transistor and a resistance element having the other end connected to the second power source is connected in series. The random number generation circuit according to any one of the above. The random number generation circuit according to claim 1, further comprising a buffer having an input terminal connected to an output terminal of the comparator. The said noise generation source is provided with the electronic channel and the electronic trap which is arrange | positioned in the vicinity of the said electronic channel, and generate | occur | produces the said noise signal. The random number generation circuit described. The noise generation source includes a first electrode, an insulating film disposed on the first electrode and generating a noise signal by pseudo breakdown, and a second electrode on the insulating film. The random number generation circuit according to claim 1, wherein: The noise generation source generates a noise signal having a fluctuation of 0.1% or more with respect to an average current value or an average voltage value of an output frequency of the random number signal. The random number generation circuit described in 1. The low-pass filter has a resistance element having one end connected to the input terminal and the other end connected to the output terminal, and a first electrode connected between the other end of the resistance element and the output terminal, 10. The random number generation circuit according to claim 2, further comprising a capacitor having a second electrode connected to a power source. The high-pass filter has a first electrode connected to an input terminal thereof, a capacitor having a second electrode connected to an output terminal thereof, and one end connected between the second electrode of the capacitor and the output terminal. The random number generation circuit according to claim 3, further comprising: a resistance element having the other end connected to a power source. 12. The differential amplifier comprising a first channel conduction type insulated gate field effect transistor and a second channel conduction type insulated gate field effect transistor. The random number generation circuit according to any one of the above. 13. The inverter according to claim 1, wherein the buffer is an inverter including a first channel conductivity type insulated gate field effect transistor and a second channel conductivity type insulated gate field effect transistor. The random number generation circuit described in the above. A noise source that generates a noise signal;
A filter for extracting a part of the frequency band of the noise signal;
A random number generation circuit comprising: a comparator that generates a random number signal obtained by amplifying a signal difference between a part of a frequency band of the noise signal and a reference signal;
A board on which the random number generation circuit is mounted;
A semiconductor integrated circuit comprising:

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