JP2006185030A - Clock modulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock modulation circuit which realizes reduction of electromagnetic wave noise while its circuit scale is kept small. <P>SOLUTION: A control circuit 15 temporally changes the input point of a clock REF to a delay line 12 in a predetermined direction where the frequency of a clock MOD to be outputted from the delay line 12 can be made smaller than the frequency of the clock REF, and when the matching of the phases of the clock REF and the clock MOD is detected by a phase detecting circuit 14, the control circuit 15 stops the input of the clock REF to the delay line 12 only in one cycle of the clock REF, then resumes the input of the clock REF from the identical phase point in a direction opposite to the transitional predetermined direction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock modulation circuit that modulates a clock frequency by temporally changing a clock input point to a delay line or a clock output point from the delay line.

  In recent years, with the further miniaturization of semiconductor integrated circuits, the frequency of the basic clock of the semiconductor integrated circuits tends to increase more and more. For this reason, the switching speed of the transistors constituting the semiconductor integrated circuit is also increased, and the switching noise generated therewith tends to increase. Accordingly, electromagnetic noise (EMI (Electro Magnetic Interference) noise) radiated from a device on which such a semiconductor integrated circuit is mounted also tends to increase.

  Here, as means for suppressing electromagnetic wave noise, a frequency spread type clock generator (Spectrum Spread Clock Generator) is known. Frequency spreading refers to periodically changing the frequency of a basic clock generated by a crystal resonator or the like with a predetermined profile (referred to as a frequency modulation profile). Since the frequency of the electromagnetic noise is dispersed by the diffusion, the peak level of the electromagnetic noise can be kept small.

  As the frequency modulation profile, a so-called center spread method or down spread method is known.

  FIG. 3 is a diagram showing an example of a frequency modulation profile by the center spread method.

  The center spread method is a method of modulating the frequency up and down around the fundamental frequency. FIG. 3 shows an example in which the frequency is modulated with the modulation period T symmetrically with respect to the fundamental frequency. Here, the phase difference between the basic clock having the basic frequency and the modulation clock having the modulated frequency coincides with every modulation period T.

  FIG. 4 is a diagram illustrating an example of a frequency modulation profile by a down spread method.

  The down spread method is a method of modulating the frequency so as to be lower than the fundamental frequency. FIG. 4 shows an example in which the frequency is modulated with the modulation period T so as to be lower than the fundamental frequency. In the downspread method, the frequency of the modulation clock is always kept lower than the frequency of the base clock (the modulation clock is always kept behind the base clock), so the phase difference between the base clock and the modulation clock. Is relatively large.

  Here, the above-described frequency modulation profile by the center spread method can be realized by a clock modulation circuit using a PLL (Phase Locked Loop) technique or a clock modulation circuit using a delay element.

  However, a clock modulation circuit using PLL technology requires a phase / frequency comparison circuit, a charge pump, a low-pass filter, a frequency divider, a voltage control circuit, and the like. For this reason, there is a problem that the circuit scale is large. In addition, this clock modulation circuit also has a problem that modulation profile distortion and overshoot due to filter characteristics occur.

On the other hand, a clock modulation circuit using a delay element does not have the above-described problem. For example, as a clock modulation circuit using such a delay element, an input clock signal can be transmitted by a plurality of delay elements for different times. A plurality of delayed clocks are generated by delaying, and the plurality of delayed clock signals are selected according to a control signal based on a predetermined frequency modulation profile, thereby increasing or decreasing the period of the output clock signal. A technique for changing the frequency has been proposed (see Patent Document 1).
Japanese Patent Publication No. 2000-845246

  Since the technique proposed in Patent Document 1 described above uses a frequency modulation profile by a center spread method, a clock having a frequency higher than the frequency of the basic clock is generated. Therefore, the semiconductor integrated circuit operates with a clock having a frequency higher than that of the basic clock. However, if the semiconductor integrated circuit is operated with such a high frequency clock, it is difficult to guarantee the operation timing of the semiconductor integrated circuit, and power consumption also increases.

  Here, when a clock modulation circuit using a frequency modulation profile by a down spread method that modulates the frequency so as to be lower than the frequency of the basic clock is adopted, the above-described problems are solved. By the way, if this clock modulation circuit is realized by using the PLL technology, problems such as a large circuit scale as described above are caused.

  Therefore, it is conceivable to realize a frequency modulation profile by a down spread method using a delay element. However, in the downspread method, the phase difference between the modulation clock and the basic clock is relatively large, so that there is a problem that a large number of delay elements are required to implement this frequency modulation profile using the delay elements. To do.

  In view of the above circumstances, an object of the present invention is to provide a clock modulation circuit capable of reducing electromagnetic noise while keeping the circuit scale small.

The clock modulation circuit of the present invention that achieves the above object is a clock modulation circuit that modulates the clock frequency by temporally changing the clock input point to the delay line or the clock output point from the delay line.
A phase detection circuit for detecting a phase of an input clock to the delay line and an output clock from the delay line;
The clock input point to the delay line or the clock output point from the delay line is set in a predetermined direction in which the frequency of the clock output from the delay line is reduced below the frequency of the clock input to the delay line. When the phase detection circuit detects that the phase of the input clock to the delay line matches the phase of the output clock from the delay line, the input point of the clock to the delay line or And a control circuit for transitioning a clock output point from the delay line to a point having the same phase in a direction opposite to the predetermined direction.

  In the clock modulation circuit of the present invention, the clock input point to the delay line or the clock output point from the delay line is set so that the frequency of the clock output from the delay line is higher than the frequency of the clock input to the delay line. The frequency modulation profile by the so-called down spread method that modulates the frequency so as to be lower than the frequency of the basic clock in order to keep the peak level of the electromagnetic wave noise small because it is time-varying in a predetermined direction to be reduced. Will be used. Therefore, the semiconductor integrated circuit is not operated with a clock having a frequency higher than the frequency of the basic clock, and the operation timing of the semiconductor integrated circuit can be reliably ensured and the power consumption can be reduced. Furthermore, in response to the detection of the phase match between the input clock to the delay line and the output clock from the delay line, the clock input point to the delay line or the clock output point from the delay line is Since the transition is made to the point of the same phase in the direction opposite to the predetermined direction, a small circuit scale is sufficient as compared with a clock modulation circuit that uses a large number of delay elements to realize a frequency modulation profile by a down spread method.

  Here, the control circuit transitions the clock input point of the delay line, and the phase detection circuit detects the coincidence of the phase of the input clock to the delay line and the output clock from the delay line. In this case, after the clock input to the delay line is stopped for one clock cycle, the clock input from the point of the same phase in the direction opposite to the predetermined direction after the transition is resumed. .

  In this way, it is not necessary to provide a complex circuit such as a multiplexer for switching the clock from the transitioned output point as compared with the case of transitioning the clock output point, and the clock from the transitioned input point is input. A gate circuit may be provided in the delay line. Therefore, the circuit scale can be further reduced.

  According to the clock modulation circuit of the present invention, it is possible to reduce electromagnetic noise while keeping the circuit scale small.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a clock modulation circuit according to an embodiment of the present invention.

  The clock modulation circuit 10 shown in FIG. 1 includes an input buffer 11, a delay line 12, an output buffer 13, a phase detection circuit 14, and a control circuit 15, and an input point of the clock REF to the delay line 12. Is a clock modulation circuit that modulates the frequency of the clock REF by temporally changing.

  The clock IN is input to the input buffer 11 constituting the clock modulation circuit 10. The input buffer 11 generates a clock REF from the input clock IN, and outputs the generated clock REF to the delay line 12, the phase detection circuit 14, and the control circuit 15.

  The delay line 12 delays the input clock REF in accordance with a control signal based on a predetermined frequency modulation profile from the control circuit 15 and outputs it as an output clock MOD toward the output buffer 13 and the phase detection circuit 14. .

  The output buffer 13 receives the output clock MOD from the delay line 12 and outputs the same as the clock OUT.

  The phase detection circuit 14 receives the input clock REF to the delay line 12 and the output clock MOD from the delay line 12, detects the phase between the input clock REF and the output clock MOD, and uses the result as the phase detection signal K. Output to the control circuit 15.

  The control circuit 15 sets the input point of the clock REF to the delay line 12 in a predetermined direction in which the frequency of the clock MOD output from the delay line 12 is lower than the frequency of the clock REF input to the delay line 12. Change. Specifically, the control circuit 15 generates control signals C1, C2, C3, and C4 based on a predetermined frequency modulation profile, and the delay line 12 has the generated control signals C1, C2, C3, and C4. By controlling the delay clocks from the plurality of delay elements, the frequency of the clock MOD is changed temporally in a predetermined direction in which the frequency of the clock MOD is reduced from the frequency of the clock REF.

  Further, the control circuit 15 receives the detection of the phase coincidence between the input clock REF to the delay line 12 and the output clock MOD from the delay line 12 by the phase detection circuit 14, that is, the phase detection signal K is inputted. At this point, the input point of the clock REF to the delay line 12 is shifted to a point having the same phase in the direction opposite to the predetermined direction.

  Further, the control circuit 15 changes the input point of the clock REF of the delay line 12 as described above, and the input clock REF to the delay line 12 and the output clock from the delay line 12 by the phase detection circuit 14. When the coincidence of the MOD phases is detected (the phase detection signal K is input), the input of the clock REF from the transitioned input point is stopped after the input of the clock REF to the delay line 12 is stopped for one clock cycle. Resume input. Hereinafter, a description will be given with reference to FIG.

  FIG. 2 is a timing chart in the clock modulation circuit shown in FIG.

  FIG. 2 shows an input clock IN input to the input buffer 11 shown in FIG. FIG. 2 shows a clock REF generated by the input buffer 11. This clock REF is input to the delay line 12. As described above, in the delay line 12, the delay amount is controlled according to the control signals C1, C2, C3, and C4 based on the predetermined frequency modulation profile from the control circuit 15. Specifically, in the delay line 12, the amount of delay is controlled so that the period increases every cycle of the input clock REF.

  First, a pulse R1 of the first cycle of the clock REF corresponding to the pulse P1 of the first cycle of the input clock IN is input to the delay line 12. The pulse R1 in the first cycle is delayed by a very small amount and output as a pulse M1 in the first cycle of the clock MOD, and further output as a pulse O1 in the first cycle of the clock OUT via the output buffer 13. The

  Next, the pulse R2 of the second cycle is input to the delay line 12. The pulse R2 is delayed by a predetermined amount and output as a pulse M2 in the second cycle.

  Further, the delay line 12 receives the pulse R3 of the third cycle. This pulse R3 is delayed by a larger delay amount than the pulse R2, and is output as a pulse M4 in the third cycle. Similarly, the seventh cycle pulse R7 is input, and the seventh cycle pulse M7 delayed by the maximum delay amount is output. By controlling in this way, the phase difference between the clock REF and the clock MOD is gradually reduced.

  Next, the pulse R8 of the eighth cycle is input. At this time, as indicated by a circle in FIG. 2, the phase difference between the clock REF and the clock MOD becomes zero. Then, the phase detection signal K is output from the phase detection circuit 14 toward the control circuit 15. In response to this, the control circuit 15 stops the input of the pulse REF of the clock REF (for one clock cycle). Note that a pulse M8 in the eighth cycle corresponding to the input pulse R8 in the eighth cycle is output. Thereafter, a pulse R10 in the 10th cycle is input, and a pulse M10 corresponding to the pulse R10 is added by a predetermined delay amount to the pulse M8 and output. By controlling the delay line 12 in this way, the delay amount of the delay line 12 is controlled to be accelerated by the period of the input clock IN which is the basic clock. In other words, control is performed to return the delay amount for one cycle. Thereafter, in the delay line 12, the delay amount is controlled based on a predetermined frequency modulation profile from the control circuit 15 as described above.

  Since the clock modulation circuit 10 includes the control circuit 15 described above, a so-called down spread method is used in which the frequency is modulated to be lower than the frequency of the basic clock in order to suppress the peak level of electromagnetic noise. A frequency modulation profile will be used. Therefore, the semiconductor integrated circuit is not operated with a clock having a frequency higher than the frequency of the basic clock, and the operation timing of the semiconductor integrated circuit can be reliably ensured and the power consumption can be reduced. In addition, the circuit scale can be reduced compared to a clock modulation circuit that uses a large number of delay elements to realize a frequency modulation profile by a down spread method.

  In the clock modulation circuit 10, the control circuit 15 changes the input point of the clock REF of the delay line 12, and the phase detection circuit 14 detects the coincidence of the phases of the clock REF and the clock MOD. After the input of the clock REF is stopped for one clock cycle, the input of the clock REF from the transitioned input point is resumed. Therefore, it is not necessary to provide a complicated circuit such as a multiplexer for switching the clock from the transitioned output point as compared with the case of transitioning the output point of the clock MOD, and a gate for inputting the clock from the transitioned input point A circuit may be provided in the delay line 12. Therefore, the circuit scale is further reduced.

  The clock output point from the delay line is temporally changed in a predetermined direction in which the frequency of the clock output from the delay line is lower than the frequency of the clock input to the delay line, and In response to the detection of the coincidence of the phases of the input clock and the output clock from the delay line, the clock output point from the delay line is shifted to a point having the same phase in the direction opposite to the predetermined direction. You may control to. By controlling in this way, in order to keep the peak level of the electromagnetic wave noise small, a frequency modulation profile by a down spread method that modulates the frequency to be lower than the frequency of the basic clock is used. Therefore, the operation timing of the semiconductor integrated circuit can be reliably guaranteed and the power consumption can be kept small. Further, it can be realized with a small circuit scale as compared with a clock modulation circuit that uses a large number of delay elements to realize a frequency modulation profile by a down spread method.

It is a figure which shows the structure of the clock modulation circuit of one Embodiment of this invention. 3 is a timing chart in the clock modulation circuit shown in FIG. 1. It is a figure which shows an example of the frequency modulation profile by a center spread system. It is a figure which shows an example of the frequency modulation profile by a down spread system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Clock modulation circuit 11 Input buffer 12 Delay line 13 Output buffer 14 Phase detection circuit 15 Control circuit

Claims (2)

In a clock modulation circuit that modulates the clock frequency by temporally changing the clock input point to the delay line or the clock output point from the delay line,
A phase detection circuit for detecting a phase of an input clock to the delay line and an output clock from the delay line;
The clock input point to the delay line or the clock output point from the delay line is set in a predetermined direction in which the frequency of the clock output from the delay line is lower than the frequency of the clock input to the delay line. In response to the fact that the phase detection circuit detects that the phase of the input clock to the delay line and the output clock from the delay line coincide with each other, the input point of the clock to the delay line or A clock modulation circuit comprising: a control circuit that causes a clock output point from the delay line to transition to a point having the same phase in a direction opposite to the predetermined direction.   When the control circuit transitions the clock input point of the delay line, and the phase detection circuit detects that the phase of the input clock to the delay line and the phase of the output clock from the delay line are detected. After the clock input to the delay line is stopped for one clock cycle, the clock input from the point of the same phase in the direction opposite to the predetermined direction after the transition is resumed. Item 2. The clock modulation circuit according to Item 1.

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