JP2006179728A - Solid state image sensor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of suppressing a characteristic variation caused by penetration of ion at the time of ion implantation of transfer gate and manufacturing a suitable solid state image sensor for microfabrication. <P>SOLUTION: An insulating film 13 is formed on a p-type well 12, and a transfer gate electrode 17 is formed on the insulating film 13. Furthermore, a semiconductor substrate 11 is prepared in which a mask auxiliary film 31 is formed on the transfer gate electrode 17. A first conductivity type ion is poured into the p-type well 12 with the transfer gate electrode 17 and the mask auxiliary film 31 as at least the parts of the mask, so that a depletion preventive region 15 is formed in a self-alignment manner to the transfer gate electrode 17. Before or after it, a second conductivity type ion is implanted in the p-type well 12 with the transfer gate electrode 17 and a mask auxiliary film 31 as some masks at least, so that a charge storage region 14 is formed in a self-aligning manner to the transfer gate electrode 17. Then, the mask auxiliary film 31 is removed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device having an embedded photodiode and a manufacturing method thereof.

  In recent years, video cameras and electronic cameras have been widely used. In these cameras, a CCD solid-state image sensor or an amplifying solid-state image sensor such as a CMOS type is used. In such a solid-state imaging device, a plurality of pixels having a light receiving portion are arranged in a matrix, and light incident on each pixel is photoelectrically converted by the light receiving portion to generate a signal charge. An embedded photodiode is used as the light receiving unit (for example, Patent Documents 1 and 2 below). The signal charge generated by the light receiving unit or the electric signal amplified in accordance with the signal charge is output to the outside via the CCD or signal line. In these solid-state image pickup devices, a predetermined region (for example, a CCD channel region in the case of a CCD solid-state image pickup device, a signal amplification unit such as a transistor in the case of an amplification-type solid-state image pickup device) A transfer gate electrode for controlling charge transfer to the region is provided (Patent Documents 1 and 2). In the case of a CCD solid-state imaging device, generally, the transfer gate electrode is also used as a predetermined CCD electrode (Patent Document 1).

  When manufacturing such a solid-state imaging device, in order to reduce variation in device characteristics, polysilicon is formed on the substrate in order to reduce variation in the position of the charge accumulation region and depletion prevention region of the embedded photodiode with respect to the transfer gate electrode. A charge gate region and a depletion prevention region are formed in a self-aligned manner with respect to the transfer gate electrode by forming a transfer gate electrode made of the like and performing ion implantation using this as a mask (Patent Document 2).

In such a conventional method for manufacturing a solid-state imaging device, ion implantation for forming a charge accumulation region and a depletion prevention region is performed using only the transfer gate electrode as a mask. On the other hand, in order to form the charge storage portion, a high acceleration voltage is used to reach ions deeply. Therefore, the transfer gate electrode functions sufficiently as a mask for ion implantation in order to prevent the device characteristics from being impaired by ions being implanted into the lower region and the like through the transfer gate electrode. The transfer gate electrode was relatively thick. For example, the thickness of the transfer gate electrode has been set to about 400 nm or more.
JP-A-5-206434 Japanese Patent Laid-Open No. 11-126893

  However, it has been found that the conventional technology described above has various disadvantages as described below due to the thick transfer gate electrode.

  First, it is difficult to increase the number of pixels per area. This will be described below. When the transfer gate electrode is thick, it is difficult to reduce the dimension in the planar direction of the transfer gate electrode itself when patterning the transfer gate electrode by etching. Therefore, from this point, it is difficult to reduce the area occupied by the pixels. In addition, an interlayer insulating film is generally formed on the transfer gate electrode and is flattened by the interlayer insulating film, and a wiring pattern and the like are further formed on the interlayer insulating layer. For this reason, the interlayer insulating film must be thick. Therefore, when the contact hole for connecting the upper wiring pattern to the transfer gate electrode or the like is formed in the interlayer insulating film, the depth of the contact hole is increased. In order to form a deep contact hole by etching, it is difficult to reduce the dimension of the contact hole in the planar direction, and thus the contact hole cannot be reduced. As described above, when the transfer gate electrode is thick, the contact hole for connecting the transfer gate electrode and the like cannot be made small. From this point, it is difficult to reduce the area occupied by the pixel. For the above reasons, if the transfer gate electrode is thick, it is difficult to increase the number of pixels per area because the occupied area of the pixels cannot be reduced.

  Secondly, if the transfer gate electrode is thick, the distance between the light receiving portion and the microlens increases, which increases shading and crosstalk. Generally, in a solid-state imaging device, a microlens that collects incident light on a light receiving unit is disposed on-chip in order to improve a light collection rate. When the transfer gate electrode is thick, not only the distance between the light receiving portion and the microlens is increased by the thick transfer gate electrode, but also the interlayer insulating film is thickened as described above. This also increases the distance between the microlenses.

  Third, if the transfer gate electrode is thick, the occupied area of the peripheral circuit region other than the pixel region increases, thereby increasing the occupied area of the entire solid-state imaging device, and thus solid-state imaging obtained from one wafer. The number of elements decreases, leading to an increase in cost. As described above, when the transfer gate electrode is thick, the interlayer insulating film becomes thick and the contact hole formed in the interlayer insulating film cannot be reduced. Similarly, since the contact hole cannot be reduced in the peripheral circuit region, the area occupied by the peripheral circuit region increases.

  The present invention has been made in view of such circumstances, increasing the number of pixels per same area, reducing the interval between the light receiving unit and the microlens to reduce shading and crosstalk, An object of the present invention is to provide a solid-state imaging device capable of reducing the cost by reducing the area occupied by the entire imaging device, and a manufacturing method thereof.

  In order to solve the above problems, a solid-state imaging device according to a first aspect of the present invention includes a second conductivity type charge accumulation region provided in a first conductivity type semiconductor region, the charge accumulation region, and the semiconductor region. A buried photodiode having a first conductivity type depletion prevention region which is provided between the surface and appears on the surface of the semiconductor region; and charge accumulated in the charge accumulation region from the charge accumulation region to the predetermined region A transfer gate electrode for controlling transfer, and the thickness of the transfer gate electrode is 100 nm or less.

  Increase the number of pixels per area, reduce the distance between the light receiving unit and the microlens to reduce shading and crosstalk, and reduce the total area of the solid-state image sensor to reduce costs Therefore, the thinner the transfer gate electrode, the better. Therefore, in the first aspect, the thickness of the transfer gate electrode is more preferably 80 nm or less, and further preferably 50 nm or less. This is the same for the third aspect described later.

  According to a second aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device comprising: a second conductivity type charge accumulation region provided in a first conductivity type semiconductor region; and the charge accumulation region and the surface of the semiconductor region. A buried photodiode having a depletion prevention region of the first conductivity type that is provided in between and appears on the surface of the semiconductor region, and a transfer that controls transfer of charges accumulated in the charge accumulation region from the charge accumulation region to a predetermined region A method of manufacturing a solid-state imaging device including a gate electrode, wherein (i) an insulating film is formed on the semiconductor region, and a patterned conductive film to form the transfer gate electrode is formed on the insulating film. A step of preparing a semiconductor substrate having a mask auxiliary film formed of one or more layers on the conductive film; and (ii) the depletion prevention region is self-aligned with respect to the transfer gate electrode. A first ion implantation step of implanting ions of a first conductivity type into the semiconductor region using the conductive film and the mask auxiliary film as at least part of a mask so as to be formed; and (iii) the first Before or after the ion implantation step, the conductive film and the mask auxiliary film are used as at least part of a mask so that the charge storage region is formed in a self-aligned manner with respect to the transfer gate electrode. A second ion implantation step of implanting ions of the second conductivity type; and (iv) removing the entire mask auxiliary film after the first and second ion implantation steps, or the mask auxiliary film Removing a part of the mask auxiliary film in the thickness direction so that the mask auxiliary film becomes thin, and the mask auxiliary film assists the mask function of the conductive film with respect to ion implantation, and It is a film that enhances the function.

  In the second aspect, the conductive film may include a polysilicon layer. In this case, the conductive film may be composed of only one layer of a polysilicon layer. However, in order to reduce the electrical resistance value, the conductive film is formed of, for example, a polysilicon layer and a tungsten silicide film formed thereon. You may comprise by the 2 layer film | membrane which consists of.

  The manufacturing method of the solid-state imaging device according to the third aspect of the present invention is the method according to the second aspect, wherein the film thickness of the conductive film is 100 nm or less.

  In the method for manufacturing a solid-state imaging device according to the fourth aspect of the present invention, in the second or third aspect, the mask auxiliary film includes a layer made of a material other than silicon oxide.

  In the solid-state imaging device manufacturing method according to the fifth aspect of the present invention, in the fourth aspect, the layer made of a material other than silicon oxide is an etching mask resist layer used for patterning the conductive film. Is.

  In the method for manufacturing a solid-state imaging device according to the sixth aspect of the present invention, in the fourth aspect, the layer made of a material other than silicon oxide is a silicon nitride film.

  According to a seventh aspect of the present invention, in the solid-state imaging device manufacturing method according to any one of the second to sixth aspects, the mask auxiliary film includes two or more layers, and the mask auxiliary film is closest to the conductive film. The step of preparing the semiconductor substrate includes a silicon oxide film forming step of forming the silicon oxide film on the conductive film, and the removing step of the silicon oxide film. This is a step of removing other layers of the mask auxiliary film so that at least a part of the thickness direction remains. In the seventh aspect, in the silicon oxide film forming step, the silicon oxide film may be formed on the conductive film by a CVD method.

  The manufacturing method of a solid-state imaging device according to an eighth aspect of the present invention is the method according to the seventh aspect, wherein the silicon oxide film formed in the silicon oxide film forming step has a thickness of 1 nm or more.

  According to a ninth aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device according to the seventh or eighth aspect, wherein the silicon oxide film formed in the silicon oxide film forming step has a thickness of 10 nm or less. is there.

  In the solid-state imaging device according to the present invention, since the thickness of the transfer gate electrode is as thin as 100 nm or less, the number of pixels per the same area is increased, or the interval between the light receiving unit and the microlens is reduced to perform shading and crosstalk. The cost can be reduced by reducing the area occupied by the entire solid-state imaging device.

  In the method for manufacturing a solid-state imaging device according to the present invention, since the mask auxiliary film is used, the depletion prevention region and the charge storage region of the embedded photodiode are formed in a self-aligned manner with respect to the transfer gate electrode. For example, the transfer gate electrode is made thin so that it does not function as a mask for ion implantation if the transfer gate electrode alone is prevented, while preventing the situation that ions are implanted into the lower region through the transfer gate electrode. be able to. Therefore, according to the method for manufacturing a solid-state imaging device according to the present invention, the transfer gate electrode is thinned, thereby increasing the number of pixels per same area or reducing the interval between the light receiving unit and the microlens for shading. In addition, it is possible to manufacture a solid-state imaging device that can reduce crosstalk and reduce the area occupied by the entire solid-state imaging device to reduce the cost.

  Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic plan view schematically showing the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the A-A ′ portion in FIG. 1. FIG. 3 is a schematic cross-sectional view of the B-B ′ portion in FIG. 1. 2 is greatly simplified, and FIG. 3 shows only the vicinity of the embedded photodiode 2 and the first polysilicon electrode 17.

  As shown in FIG. 1, the solid-state imaging device 1 according to the present embodiment is configured as a CCD type solid-state imaging device, and transfers an embedded photodiode 2 as a light receiving unit and a signal charge generated by the embedded photodiode 2. A vertical CCD 3 and a horizontal CCD 4 and an output amplifier 5 are provided. The pixel 6 has an embedded photodiode 2 and a part of the vertical CCD 3, and a plurality of pixels 6 are arranged two-dimensionally. The electrodes of the vertical CCD 3 (electrodes for controlling charge transfer) are a first polysilicon electrode 17 (see FIG. 3) and a second polysilicon electrode (see FIG. 3), as in a general CCD type solid-state imaging device. (Not shown). The solid-state imaging device 1 also has a peripheral circuit for generating a drive pulse and the like, but the illustration thereof is omitted.

  As shown in FIG. 3, a P-type well 12, which is a first conductivity type semiconductor region, is provided on an N-type silicon substrate 11. A silicon oxide film 13 having a thickness of 100 nm or less is disposed as an insulating film over the entire surface of the P-type well 12. The buried photodiode 2 is provided in an N-type charge storage region 14 of the second conductivity type provided in the P-type well 12 and between the charge storage region 14 and the surface of the P-type well 12. And a P-type depletion prevention region 15 which is the first conductivity type appearing on the surface of 12. An N-type channel region 16 constituting the vertical CCD 3 is provided in the P-type well 12.

  In the present embodiment, the first polysilicon electrode 17 is also used as a transfer gate electrode for controlling charge transfer from the charge accumulation region 14 of the embedded photodiode 2 to the channel region 16 of the vertical CCD 3 as shown in FIG. , Have been combined. In other words, the first polysilicon electrode 17 functions as an electrode of the vertical CCD 3 and also functions as the transfer gate electrode.

  The first polysilicon electrode 17 is formed on the silicon oxide film 13. The first polysilicon electrode 17 is covered with a silicon oxide film 18. Although not shown in the drawing, the second polysilicon electrode is formed mainly on the silicon oxide film 13 and partially overlaps the first polysilicon electrode 17 via the silicon oxide film 18. The silicon oxide film 18 electrically insulates the first polysilicon electrode 17 from the second polysilicon electrode.

  In the present embodiment, the electrode 17 is composed of only one polysilicon layer. However, the present invention is not limited to this. For example, in order to lower the electric resistance value, the polysilicon layer and the upper layer are formed thereon. You may comprise with the two-layer film which consists of the formed tungsten silicide film | membrane.

  Light incident on the embedded photodiode 2 is photoelectrically converted, and signal charges generated thereby are accumulated in the charge accumulation region 14. When a predetermined pulse voltage is applied to the first polysilicon electrode 17, the charge accumulated in the charge accumulation region 14 is transferred to the channel region 16. Then, a predetermined pulse voltage is applied to the first polysilicon electrode 17 and the second polysilicon electrode, and charges are transferred in the channel region 16.

  Although not shown in FIG. 3, an interlayer insulating film 20 (see FIG. 2) is formed on the silicon oxide film 18 and the silicon oxide film 13. As shown in FIG. 2, a light shielding film 21 having an opening 21 a corresponding to the embedded photodiode 2 is provided on the interlayer insulating film 20. The light shielding film 21 is covered with an interlayer insulating film 22. Although not shown in FIG. 2, a contact hole is formed in the interlayer insulating film 20 at a predetermined location, and the light shielding film 21 that also serves as a wiring pattern is electrically connected to a predetermined portion of the CCD electrode and the peripheral circuit by the contact hole. Connected.

  As shown in FIG. 2, any of the RGB color filter layers 23 R, 23 G, and 23 B is disposed on-chip via the interlayer insulating film 22 on each embedded photodiode 2. In FIG. 2, a green color filter layer 23G and a blue color filter layer 23B are shown. As an arrangement of the color filter layers 23R, 23G, and 23B, for example, a Bayer arrangement is adopted. A planarizing film 24 is laminated on the color filter layers 23R, 23G, and 23B, and a microlens 25 is disposed on the planarizing film 24. The microlens 25 is disposed on-chip corresponding to the embedded photodiode 2 and condenses incident light on the embedded photodiode 2.

  In the solid-state imaging device 1 according to the present embodiment, the thickness of the first polysilicon electrode 17 is set to 100 nm or less. Therefore, the thickness of the first polysilicon electrode 17 is considerably thinner than the thickness of about 400 nm in the prior art described above. For this reason, the dimension of the first polysilicon electrode 17 itself in the planar direction can be reduced, and the interlayer insulating film 20 can also be thinned. Therefore, the contact hole (here, the contact hole provided in the region of the pixel 6) ) Can be reduced, and the area occupied by the pixel 6 can be reduced by these. Therefore, according to this embodiment, the number of pixels per area can be increased.

  In addition, according to the present embodiment, since the first polysilicon electrode 17 is thin, the first polysilicon electrode 17 is thin and the interlayer insulating film 20 is also thin as described above. The interval between the embedded photodiode 2 and the microlens 25 is narrowed. As a result, according to the present embodiment, shading and crosstalk can be reduced.

  Furthermore, according to the present embodiment, since the first polysilicon electrode 17 is thin, the interlayer insulating film 20 can also be thinned. Therefore, the contact hole (here, the contact hole provided in the peripheral circuit region) is formed. Can be small. Therefore, according to the present embodiment, the area occupied by the peripheral circuit region other than the pixel region can be reduced, and as a result, the number of solid-state imaging devices obtained from one wafer increases, thereby reducing the cost. be able to.

  In order to further increase these advantages, the thinner the first polysilicon electrode 17 is, the better. Therefore, the thickness of the first polysilicon electrode 17 is more preferably 80 nm or less, and still more preferably 50 nm or less.

  [Second Embodiment]

FIG. 4 is a schematic cross-sectional view schematically showing each step of the solid-state imaging device manufacturing method according to the second embodiment of the present invention, and corresponds to FIG.
The manufacturing method according to the present embodiment is a method for manufacturing the solid-state imaging device 1 according to the first embodiment. In the following description, the manufacturing process of the portion shown in FIG. 3 will be mainly described.

  First, a P-type well 12 is formed on an N-type silicon substrate 11 by epitaxial growth. Next, a silicon oxide film 13 having a thickness of, for example, 80 nm is formed over the entire surface of the P-type well 12.

  Thereafter, various diffusions of the channel region 16 and peripheral circuits (not shown) are performed, and then a polysilicon film as a conductive film is formed on the entire surface. This polysilicon film will later become the first polysilicon electrode 17, and here the film thickness is, for example, 100 nm.

  Next, a first resist pattern 31 is formed using a known photolithography technique, and the polysilicon film is etched using the first resist pattern 31 as an etching mask to form a first polysilicon electrode 17.

  Next, the first resist pattern 31 is left as it is on the first polysilicon electrode 17 as a mask auxiliary film (a film that enhances the mask function by assisting the mask function of the polysilicon electrode 17 with respect to ion implantation). First ion implantation is performed using resist pattern 31 and first polysilicon electrode 17 as a mask. However, before this first ion implantation, a second region for a mask for ion implantation is provided in another region where the first ion implantation is not required (for example, a region where the second polysilicon electrode is formed). A resist pattern (not shown) is formed.

  Here, as the first ion implantation, boron ions are implanted from an oblique direction, and the surface depletion prevention region 15 is formed in a self-aligned manner with respect to the first polysilicon electrode 17. FIG. 4A shows this state. The reason why the ions are implanted from the oblique direction in this way is to expose the portion of the charge storage region 14 adjacent to the first polysilicon electrode 17 on the surface of the P-type well 12. However, a similar structure can be formed without using oblique ion implantation, for example, by controlling the heat treatment time after ion implantation.

Here, the conditions for the first ion implantation are, for example, an acceleration voltage of 40 KeV and a dose of 3 × 10 ¹² cm ⁻² . Since the first polysilicon electrode 17 is thin, only the first polysilicon electrode 17 does not prevent ion implantation, and ions penetrate and are implanted into the lower region of the first polysilicon electrode 17 and the like. There is a fear. However, since the first resist pattern 31 is disposed on the first polysilicon electrode 17 as a mask auxiliary film, ions do not penetrate the first polysilicon electrode 17.

  Next, leaving the first resist pattern 31 and the second resist pattern as they are, a third resist pattern 33 is formed so as to cover a part of the embedded photodiode 2 (FIG. 4B).

Then, second ion implantation is performed using the first polysilicon electrode 17, the first and third resist patterns 31, 33, and the second resist pattern as a mask. Here, as the second ion implantation, phosphorus ions are implanted from approximately the vertical direction, and the charge accumulation region 14 is formed in a self-aligned manner with respect to the first polysilicon electrode 17 (FIG. 4C). The ion implantation conditions here are, for example, an acceleration voltage of 300 KeV and a dose amount of 3 × 10 ¹² cm ⁻² . Also in the case of the second ion implantation, since the first resist pattern 31 is disposed on the first polysilicon electrode 17 as a mask auxiliary film, ions do not penetrate the first polysilicon electrode 17.

  Next, the first and third resist patterns 31, 33 and the second resist pattern are removed (FIG. 4D).

  Thereafter, a silicon oxide film 18 (see FIG. 3) is formed so as to cover the first polysilicon electrode 17 by thermal oxidation, and further, the second polysilicon electrode, the interlayer insulating film 20, the light shielding film 21, and the interlayer Through the formation process of the insulating film 22, the color filter layers 23R, 23G, and 23B, the planarization film 24, the microlens 25, and the like, the solid-state imaging device 1 according to the first embodiment is completed.

  According to the present embodiment, as described above, since the first resist pattern 31 is used as the mask auxiliary film during the first and second ion implantations, the buried photodiode 2 is depleted. The first polysilicon electrode 17 is made thin while the prevention region 15 and the charge storage region 14 are formed in a self-aligned manner with respect to the first polysilicon electrode 17 (particularly, the portion 17a corresponding to the transfer gate electrode). Nevertheless, it is possible to prevent ions from penetrating the polysilicon electrode 17. Therefore, according to the present embodiment, the thin first polysilicon electrode 17 is formed while having both the effect of reducing variations in device characteristics due to such self-alignment and the effect of preventing deterioration of device characteristics due to prevention of ion penetration. The solid-state imaging device 1 having various advantages due to the holding can be manufactured.

  In this embodiment, since the first resist pattern 31 used for patterning the first polysilicon electrode 17 is used as the mask auxiliary film, a mask auxiliary film is formed separately from the etching mask. Compared with the case, the advantage that manufacture becomes easy is also acquired.

  [Comparative example]

  Here, a solid-state imaging device 100 according to a comparative example compared with the solid-state imaging device 1 according to the first embodiment is shown in FIG. FIG. 5 is a schematic cross-sectional view schematically showing a main part of the solid-state imaging device 100, and corresponds to FIG. 5, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device 100 is different from the solid-state imaging device 1 according to the first embodiment in that the thickness of the first polysilicon electrode 17 is as thick as about 400 nm, and FIG. The thickness of the interlayer insulating film (not shown) corresponding to the interlayer insulating film 20 in the middle is only thicker than that in the first embodiment.

  As can be seen from the above description, in this solid-state imaging device 100, since the first polysilicon electrode 17 is thicker than in the solid-state imaging device 1, (i) it is difficult to increase the number of pixels per same area. Yes, (ii) shading and crosstalk are large, (iii) the area occupied by peripheral circuit regions other than the pixel region is increased, and cost increases cannot be avoided.

  Next, a solid-state imaging device manufacturing method according to a comparative example compared with the solid-state imaging device manufacturing method according to the second embodiment will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view schematically showing each step of the solid-state imaging device manufacturing method according to this comparative example, and corresponds to FIG. 6A to 6D correspond to FIGS. 4A to 4D, respectively. 6, elements that are the same as or correspond to those in FIG. 4 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The manufacturing method according to the comparative example shown in FIG. 6 is a method for manufacturing the solid-state imaging device 100 shown in FIG.

  The manufacturing method according to the comparative example shown in FIG. 6 is different from the manufacturing method according to the second embodiment shown in FIG. 4 in the following points. In this comparative example, the first resist pattern 31 used for the patterning of the first polysilicon electrode 17 is removed before the first ion implantation, and a mask for the first ion implantation (here, depletion is performed). As a mask for forming the prevention region 15 in a self-aligned manner with respect to the first polysilicon electrode 17, only the first polysilicon electrode 17 is used, and the mask auxiliary film is not used. In this comparative example, the first polysilicon is used as a mask for the second ion implantation (here, a mask for forming the charge storage region 14 in a self-aligned manner with respect to the first polysilicon electrode 17). Only the electrode 17 is used, and the mask auxiliary film is not used.

  Therefore, in this comparative example, the thickness of the first polysilicon electrode 17 is 400 nm in order to sufficiently prevent the penetration of ions with respect to the first and second ion implantations using only the first polysilicon electrode 17. Being thick with a degree.

  Thus, according to the manufacturing method according to this comparative example, unlike the manufacturing method according to the second embodiment, the mask auxiliary film is not used, so the depletion prevention region 15 for the first polysilicon electrode 17 is not used. When the solid-state imaging device 100 having both the effect of reducing the variation in device characteristics due to self-alignment of the charge storage region 14 and the effect of preventing the deterioration of device characteristics due to the prevention of ion penetration is manufactured, the first polysilicon electrode 17 The thickness must be increased.

  [Third Embodiment]

FIG. 7 is a schematic sectional view schematically showing each step of the solid-state imaging device manufacturing method according to the third embodiment of the present invention, and corresponds to FIG.
The manufacturing method according to the present embodiment is also a method for manufacturing the solid-state imaging device 1 according to the first embodiment, similarly to the second embodiment.

  This embodiment differs from the second embodiment mainly in that a silicon nitride film 41 is used instead of the first resist pattern 31 as the mask auxiliary film, and the depletion prevention region 15 is used. The charge storage region 14 is formed in the reverse order.

  Also in the present embodiment, the silicon oxide film 13 is formed on the entire surface of the P-type well 12, and the steps up to the row of various diffusions of the channel region 16 and the peripheral circuit (not shown) are performed in the second embodiment. Since it is the same as that of a form, the description is abbreviate | omitted.

  In the present embodiment, next, for example, a polysilicon film having a thickness of 80 nm and a silicon nitride film having a thickness of 200 nm, for example, are continuously stacked on the entire surface, and these are patterned to form a first film A polysilicon electrode 17 and a patterned silicon nitride film 41 as the mask auxiliary film are formed. The first resist pattern (not shown) for the etching mask used for this patterning is removed.

  Thereafter, a second resist pattern 42 is formed so as to cover a part of the embedded photodiode 2 (FIG. 7A). The second resist pattern 42 is also formed in another region where the following first ion implantation is not required (for example, a region where the second polysilicon electrode is formed).

Subsequently, first ion implantation is performed using the first polysilicon electrode 17, the silicon nitride film 41 as the mask auxiliary film, and the second resist pattern 42 as a mask. Here, as the first ion implantation, phosphorus ions are implanted from a substantially vertical direction, and the charge accumulation region 14 is formed in a self-aligned manner with respect to the first polysilicon electrode 17. FIG. 7B shows this state. The ion implantation conditions here are, for example, an acceleration voltage of 300 KeV and a dose of 3 × 10 ¹² cm ⁻² . Since the first polysilicon electrode 17 is thin, only the first polysilicon electrode 17 does not block the ion implantation, and ions penetrate and are implanted into the lower region of the first polysilicon electrode 17 and the like. There is a fear. However, since the silicon nitride film 41 is disposed on the first polysilicon electrode 17 as a mask auxiliary film, ions do not penetrate the first polysilicon electrode 17.

  Next, after removing the second resist pattern 42, second ion implantation is performed using the first polysilicon electrode 17 and the silicon nitride film 41 as the mask auxiliary film as a mask. However, before the second ion implantation, a third region for a mask for ion implantation is provided in another region where the second ion implantation is not required (for example, a region where the second polysilicon electrode is formed). A resist pattern (not shown) is formed.

Here, as the second ion implantation, boron ions are implanted from an oblique direction, and the surface depletion prevention region 15 is formed in a self-aligned manner with respect to the first polysilicon electrode 17. FIG. 7C shows this state. The ion implantation conditions here are, for example, an acceleration voltage of 40 KeV and a dose of 3 × 10 ¹² cm ⁻² . Also in the case of the second ion implantation, since the silicon nitride film 41 is disposed on the first polysilicon electrode 17 as a mask auxiliary film, ions do not penetrate the first polysilicon electrode 17.

  Further, after removing the third resist pattern, the silicon nitride film 41 is removed (FIG. 7D). The removal of the silicon nitride film 41 may be dry etching or wet etching with phosphoric acid. However, wet etching is preferable in that the surface of the silicon oxide film 13 on the photodiode 2 is less damaged. The silicon oxide film has a high selectivity with respect to the wet etching of the silicon nitride film, and the amount to be etched is extremely small. Therefore, if the silicon nitride film 41 is removed by wet etching, the possibility that the silicon oxide film 13 on the light receiving surface is etched and damaged is extremely small.

  Thereafter, as in the second embodiment, after the silicon oxide film 18 (see FIG. 3) is formed so as to cover the first polysilicon electrode 17 by thermal oxidation, the second polysilicon electrode is further formed. The solid-state imaging according to the first embodiment is performed through the formation process of the interlayer insulating film 20, the light shielding film 21, the interlayer insulating film 22, the color filter layers 23R, 23G, and 23B, the planarizing film 24, the microlens 25, and the like. Element 1 is completed.

  Also in this embodiment, since the mask auxiliary film is used, the same advantages as those in the first embodiment can be obtained.

  Even in the case where the mask auxiliary film and the silicon nitride film 41 are used as in the present embodiment, the formation order of the depletion prevention region 15 and the charge storage region 14 is made the same as in the second embodiment. Good.

  [Fourth Embodiment]

  FIG. 8 is a schematic cross-sectional view schematically showing each step of the solid-state imaging device manufacturing method according to the fourth embodiment of the present invention, and corresponds to FIG. 8A to 8D correspond to FIGS. 7A to 7D, respectively. 8, elements that are the same as or correspond to those in FIG. 7 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment differs from the third embodiment in that a silicon oxide film 51 of, eg, a 10 nm thickness is provided between the first polysilicon electrode 17 and the silicon nitride film 41. That is, in the third embodiment, the mask auxiliary film is composed of one layer of the silicon nitride film 41, whereas in this embodiment, the mask auxiliary film is formed of the silicon nitride film 41 and the silicon oxide film. The film 51 is composed of two layers.

  In the third embodiment, in the process from FIG. 7C to FIG. 7D, the silicon nitride film 41 is removed by wet etching. At this time, the surface of the first polysilicon electrode 17 may be slightly damaged. On the other hand, in this embodiment, since the silicon oxide film 51 is formed between the first polysilicon electrode 17 and the silicon oxide film 41, the silicon nitride film 41 is removed by wet etching. If wet etching is performed so that at least part of the thickness direction of the silicon oxide film 51 remains, there is no possibility that the surface of the first polysilicon electrode 17 is damaged.

  In order to obtain the above-described surface protection effect of the first polysilicon electrode 17 relatively remarkably, the thickness when the silicon oxide film 51 is formed is preferably 1 nm or more. If the thickness of the silicon oxide film 51 is too large, the remaining thickness of the silicon oxide film 51 after the removal of the silicon nitride film 41 by wet etching is increased, and the first polysilicon electrode 17 is formed. This is not preferable because the above-described advantages of thinning are reduced. Therefore, the thickness when forming the silicon oxide film 51 is preferably 10 nm or less.

  The silicon oxide film 51 may be formed by thermally oxidizing the polysilicon film after forming a polysilicon film to be the first polysilicon electrode 17, or may be formed by a CVD method or the like. Good.

  In addition, the process after FIG.8 (d) in this Embodiment is the same as the process after FIG.7 (d) in the said 3rd Embodiment.

  According to the present embodiment, the same advantages as those of the third embodiment can be obtained, and the surface protection effect of the first polysilicon electrode 17 can be obtained as described above.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, each of the above-described embodiments is an example in which the present invention is applied to a CCD solid-state imaging device and a method for manufacturing the same. The method can also be applied.

  In an amplification type solid-state imaging device such as a CMOS type, an amplification unit (pixel amplifier) is disposed in each pixel, and vertical signal lines and horizontal signal lines are provided in place of the CCDs 3 and 4. The signal charge generated in the light receiving part is transferred to the amplifying part by the transfer gate electrode. The electric signal amplified corresponding to the signal charge is output from each pixel.

  For example, Patent Document 2 discloses an amplification type solid-state imaging device having a buried photodiode as a light receiving portion, and a transfer gate electrode and a JFET (junction field effect transistor) as an amplification portion provided in a pixel. . In this example, the charge storage region, the depletion prevention region, and the conductivity type of the semiconductor region in which these are provided are opposite to those of the CCD solid-state imaging device according to each of the above-described embodiments.

  The present invention can also be applied to, for example, an amplification type solid-state imaging device disclosed in Patent Document 2 and a method for manufacturing the same. In this case, the P-type well is an N-type epitaxial layer, the charge storage region is a P-type, and the depletion prevention region is an N-type. When the present invention is applied to such an amplification type solid-state imaging device manufacturing method, formation of a resist pattern corresponding to the second resist pattern in the second embodiment, or the third embodiment Formation of a resist pattern corresponding to the third resist pattern in the embodiment is not always necessary.

1 is a schematic plan view schematically showing a solid-state imaging device according to a first embodiment of the present invention. It is a schematic sectional drawing of the A-A 'part in FIG. It is a schematic sectional drawing of the B-B 'part in FIG. It is a schematic sectional drawing which shows each process of the solid-state image sensor manufacturing method by the 2nd Embodiment of this invention typically, respectively. It is a schematic sectional drawing which shows typically the principal part of the solid-state image sensor by a comparative example. It is a schematic sectional drawing which shows each process of the solid-state image sensor manufacturing method by a comparative example typically, respectively. It is a schematic sectional drawing which shows typically each process of a solid imaging device manufacturing method by a 3rd embodiment of the present invention, respectively. It is a schematic sectional drawing which shows each process of the solid-state image sensor manufacturing method by the 4th Embodiment of this invention typically, respectively.

Explanation of symbols

1 Solid-state image sensor 2 Embedded photodiode 3 Vertical CCD
4 Horizontal CCD
11 N-type silicon substrate 12 P-type well 13 Silicon oxide film 14 Charge accumulation region 15 Depletion prevention region 16 Channel region 17 First polysilicon electrode 18, 51 Silicon oxide film 19 Interlayer insulating film 25 Microlens

Claims (9)

A second conductivity type charge accumulation region provided in the first conductivity type semiconductor region, and a first conductivity type depletion appearing on the surface of the semiconductor region provided between the charge accumulation region and the surface of the semiconductor region. A buried photodiode having a prevention region;
A transfer gate electrode for controlling transfer of charges accumulated in the charge accumulation region from the charge accumulation region to a predetermined region;
With
A solid-state imaging device, wherein the transfer gate electrode has a thickness of 100 nm or less. A second conductivity type charge accumulation region provided in the first conductivity type semiconductor region, and a first conductivity type depletion provided between the charge accumulation region and the semiconductor region surface; A solid-state imaging device comprising: a buried photodiode having an anti-oxidation region; and a transfer gate electrode that controls transfer of charges accumulated in the charge accumulation region from the charge accumulation region to a predetermined region,
A semiconductor in which an insulating film is formed on the semiconductor region, a patterned conductive film to form the transfer gate electrode is formed on the insulating film, and a mask auxiliary film including one or more layers is formed on the conductive film Preparing a substrate;
Using the conductive film and the mask auxiliary film as at least part of a mask, ions of the first conductivity type are applied to the semiconductor region so that the depletion prevention region is formed in a self-aligned manner with respect to the transfer gate electrode. A first ion implantation step for implantation;
Before or after the first ion implantation step, using the conductive film and the mask auxiliary film as at least a part of a mask so that the charge storage region is formed in a self-aligned manner with respect to the transfer gate electrode, A second ion implantation step of implanting ions of a second conductivity type into the semiconductor region;
After the first and second ion implantation steps, the entire mask auxiliary film is removed or a part of the mask auxiliary film in the thickness direction is removed so that the mask auxiliary film becomes thin. Process,
With
The method of manufacturing a solid-state imaging device, wherein the mask auxiliary film is a film that assists a mask function of the conductive film with respect to ion implantation and enhances the mask function.   The method for manufacturing a solid-state imaging device according to claim 2, wherein the conductive film has a thickness of 100 nm or less.   4. The method of manufacturing a solid-state imaging device according to claim 2, wherein the mask auxiliary film includes a layer made of a material other than silicon oxide.   5. The method for manufacturing a solid-state imaging device according to claim 4, wherein the layer made of a material other than silicon oxide is an etching mask resist layer used for patterning the conductive film.   5. The method for manufacturing a solid-state imaging device according to claim 4, wherein the layer made of a material other than silicon oxide is a silicon nitride film. The mask auxiliary film comprises two or more layers,
The layer closest to the conductive film of the mask auxiliary film is a silicon oxide film,
The step of preparing the semiconductor substrate includes a silicon oxide film forming step of forming the silicon oxide film on the conductive film,
7. The removing process according to claim 2, wherein the removing step is a step of removing another layer of the mask auxiliary film so that at least a part of the silicon oxide film in the thickness direction remains. The manufacturing method of the solid-state image sensor of description.   8. The method for manufacturing a solid-state imaging device according to claim 7, wherein the thickness of the silicon oxide film formed in the silicon oxide film forming step is 1 nm or more.   9. The method for manufacturing a solid-state imaging device according to claim 7, wherein the thickness of the silicon oxide film formed in the silicon oxide film forming step is 10 nm or less.

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