JP2006171907A - Information processor and nonvolatile memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of accessing a memory, and not allowing reduction of performance, even during data erasure of a nonvolatile storage device, and to provide a memory controller controlling the nonvolatile storage device. <P>SOLUTION: This information processor has: a CPU 11 performing control; an HDD 15 to which the CPU 11 performs reading/writing of data; and an HDD controller 14 controlling the reading/writing of the data to the HDD 15 by the CPU 11. The HDD controller 14 has, in a PC 1, an erasure data writing part 142 writing the data to the HDD 15 independently of the CPU 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus including a non-volatile storage unit and a non-volatile memory control apparatus that controls the non-volatile storage unit.

  Information processing apparatuses such as PCs (personal computers) are often provided with non-volatile storage devices such as HDDs (hard disk drives) and flash memories. Since these nonvolatile storage devices continue to store data even after the power is turned off, data leakage becomes a problem. In particular, another person can read data from a discarded or transferred nonvolatile storage device, which is a problem. For this reason, it is a common practice to erase all data in the non-volatile storage device upon disposal or transfer. As one method in this case, random data or predetermined data generated by calculation by the CPU (central processing unit) of the information processing apparatus is written into a memory included in the information processing apparatus, and the data is transferred from the memory to the DMA (dynamic memory access). ) To the entire storage area of the nonvolatile storage means using the function.

  FIG. 3 is a functional configuration diagram of the PC 1 for explaining the related art. The PC 1 includes a CPU 11, a memory controller 12, a memory 13, an HDD controller 14 ', and an HDD 15, and the CPU 11, the memory controller 12, and the HDD controller 14' are connected by a bus B. The HDD controller 14 'has a DMA function. In the PC 1 having such a configuration, the data in the HDD 15 is erased by writing the data in the memory 13 to the entire storage area of the HDD 15 using a DMA (direct memory access) function.

  FIG. 4 is a flowchart showing the flow of HDD data erasure processing in this conventional case. Writing (data erasing) of data in the memory 13 to the HDD 15 is instructed by the CPU 11 to the HDD 15 (step S111), and the HDD 15 receives this and transmits a DMA request signal to the HDD controller (DMA controller) 14 ′ (step S111). S411). In response, the HDD controller 14 'transmits a DMA acknowledge signal to the HDD 15 and transmits a memory access request signal to the memory controller 12 (step S211). Thereby, data transfer (data writing) from the memory 13 to the HDD 15 is performed (step S311). This data transfer is repeated until data is written in all storage areas of the HDD 15 while changing the write destination address (HDD address) (NO in step S312). Accordingly, the memory 13, the memory controller 12, and the bus B are in use until the data erasure of the HDD 15 is completed. Therefore, even if the CPU 11 tries to read data from the memory 13 (steps S112 and S113), the HDD 15 If the data erasure is not completed (NO in step S312), the data cannot be read from the memory 13, and the data is read from the memory 13 after the data erasure of the HDD 15 is completed. (YES in step S312, step S313).

  However, in the above-described data erasing method, the memory, the memory controller, and the bus are in use until the data erasing is completed, and the performance (access speed) of the memory and the bus is lowered until the data erasing is completed. In recent years, with the increase in the capacity of storage media such as HDDs, the time taken to erase stored contents has increased, which is a further problem.

  The present invention has been made in view of the above problems, and an information processing apparatus that does not affect the performance of other parts of the information processing apparatus by erasing data in the nonvolatile storage apparatus, and the nonvolatile storage apparatus An object of the present invention is to provide a memory control device for controlling.

  The information processing apparatus according to claim 1 controls a control unit that performs control, a nonvolatile storage unit that reads and writes data from and to the control unit, and controls reading and writing of data to and from the nonvolatile storage unit of the control unit Nonvolatile memory control means, and the nonvolatile memory control means comprises writing means for writing data in the nonvolatile memory control means into the nonvolatile storage means.

  An information processing apparatus according to a second aspect is the information processing apparatus according to the first aspect, wherein the nonvolatile memory control means further includes a storage means for storing data received from the outside, and the writing means The data stored in the storage means is written into the nonvolatile storage means.

  An information processing apparatus according to a third aspect is the information processing apparatus according to the first or second aspect, wherein the nonvolatile storage means is detachable from the information processing apparatus.

  According to a fourth aspect of the present invention, there is provided a non-volatile memory control device that controls reading and writing of data with respect to the non-volatile storage means by a control means that performs control, wherein data in the non-volatile memory control device is stored in the non-volatile storage means. Writing means for writing is provided.

  According to the first or fourth aspect of the present invention, data can be written to the non-volatile storage means without using the memory or bus provided in the information processing apparatus. Even when other jobs are in progress, data can be written to the non-volatile storage means, and the data in the non-volatile storage means can be erased without degrading the performance of the memory, bus, etc. . Even if the memory or bus is used for other jobs, this does not increase the time required for erasing data in the nonvolatile storage means.

  According to the second aspect of the present invention, data can be written from the outside to the storage means included in the nonvolatile storage means, and the data is written to the nonvolatile storage means. The previous data in the nonvolatile storage means can be erased.

  According to the third aspect of the present invention, since it is detachable, it can be easily detached from the apparatus, and then can be easily attached to another apparatus, so that others can easily reuse it. It is possible to prevent leakage of data stored in the detachable non-volatile storage means that easily leaks.

  Embodiments according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a functional configuration of a PC (personal computer) as an information processing apparatus according to an embodiment of the present invention. The PC 1 includes a CPU 11, a memory controller 12, a memory 13, an HDD controller 14, and an HDD 15.

  The CPU 11 performs computation, control, etc. in the PC 1 by executing a program. The memory 13 is a storage device that stores a program executed by the CPU 11 and is used as a work area when the program is executed. The memory 13 is, for example, a RAM (Random Access Memory). The memory controller 12 controls access (read / write) to the memory 13. The HDD 15 is a non-volatile storage device that includes a magnetic disk. The HDD 15 stores and retains data even after the power source of the PC 1 (that is, power supply to the HDD 15) is turned off.

  The HDD controller 14 controls access (read / write) to the HDD 15. The HDD controller 14 writes data to the HDD 15 and erases data already written to the HDD 15. This erasing process is completed only between the HDD controller 14 and the HDD 15, and the memory controller 12, the memory 13, and the bus B are not used. The HDD controller 14 includes an erase data storage unit 141 and an erase data writing unit 142. The erase data storage unit 141 stores data of a predetermined length, for example, 10 kBytes (for example, a list of 0) used as erase data. The erase data storage unit 141 is a register, for example. Erase data stored in the erase data storage unit 141 is written by the CPU 11. The CPU 11 acquires the erased data by writing it in advance in a program executed by the CPU 11, generating the program by calculation, or allowing the user to input it. The erasure data writing unit 142 writes the erasure data in the erasure data storage unit 141 to the HDD 15 while changing the write address, and writes it in the entire storage area of the HDD 15. The erasure data writing unit 142 starts erasing the data in the HDD 15 when data is written to the erasure data storage unit 141 by the CPU 11. The HDD controller 14 and the HDD 15 are provided, for example, in one housing (HDD unit), and this housing is detachable from the PC 1.

  Next, the flow of HDD data erasure processing in this embodiment will be described. FIG. 2 is a flowchart showing the flow of HDD data erasure processing.

  In the CPU 11, in step S 101, the CPU 11 instructs the erasure of all data in the HDD 15 by writing the erasure data (for example, a list of 0s) to the erasure data storage unit (register) 141 of the HDD controller 14. In step S102, the CPU 11 checks whether, for example, reading of data from the memory 13 has occurred in the CPU 11 as access to the memory 13, and if it occurs (YES in step S102), the process proceeds to step S103. In step S103, the CPU 11 transmits a read instruction, a read address, and a read data length to the memory controller 12, and instructs the memory controller 12 to read data from the memory 13. If no data is read in step S102 (NO in step S102) and if the process in step S103 is completed, the normal program execution is continued.

  In the HDD controller 14, in step S 201, the erase data writing unit 142 receives the data stored in the erase data storage unit 141 in response to the CPU 11 having written the erase data in the erase data storage unit 141. The write address is sequentially written from the initial address to the entire storage area of the HDD 15 while being shifted by the data length of the data stored in the erase data storage unit 141.

  In step S <b> 301, the memory controller 12 receives an instruction from the CPU 11, reads data having a specified length (read data length) from a specified address (read address) in the memory 13, and transmits the data to the CPU 11. I do.

  As described above, in this embodiment, since the data written in the HDD controller 14 by the CPU 11 is written in the entire area of the HDD 15 by the CPU 11, the data erasure of the HDD 14 is performed only between the HDD controller 14 and the HDD 15. During this time, the memory 13, the memory controller 12, and the bus B are not used for erasing the data in the HDD 15, so that the performance of the memory 13 and the bus B does not deteriorate during the data erasing of the HDD 15. Further, the memory 13 can be used during data erasure of the HDD 15.

  In addition, this invention is not limited to the thing of the said embodiment, The aspect described below can be employ | adopted. In this embodiment, the PC 1 has been described using an example including the CPU 11, the memory controller 12, the memory 13, the HDD controller 14, and the HDD 15. However, other components (for example, a printer) are connected to the PC 1 with respect to the PC 1. It may be connected inside or outside. In this case, as in the case of access from the CPU 11 to the memory 13 (this embodiment), the data erasure of the HDD 15 according to the present invention causes an access wait for the access from the PC 1 (or the CPU 11) to this component. It is done without affecting the performance and performance.

  In this embodiment, the CPU 11 writes erasure data to the erasure data storage unit 141 in the HDD controller 14 and writes the data to the HDD 15. However, the erasure data storage unit 141 stores the erasure data in advance, The data may be written in the HDD 15, or data (for example, random data) may be generated in the HDD controller 14 and the data may be written in the HDD 15. When data is generated in the HDD controller 14, an erasure data generation unit that generates erasure data (for example, random data) by a program, for example, may be provided instead of the erasure data storage unit 141.

  In the present embodiment, the HDD has been described as the nonvolatile storage means. However, any nonvolatile storage means may be used, for example, a flash memory or an MRAM (Magnetic Resistance Random Access Memory).

  In this embodiment, erase data is written to all storage areas of the HDD and all data of the HDD is erased. However, the present invention is not limited to the case of erasing all data. For example, data in only one partition) may be deleted.

It is a block diagram which shows the function structure of PC in one Embodiment of this invention. It is a flowchart which shows the flow of a process of HDD data deletion of PC in one Embodiment of this invention. It is a block diagram which shows the function structure of PC in a prior art. It is a flowchart which shows the flow of a process of HDD data deletion of PC in a prior art.

Explanation of symbols

1 PC (information processing equipment)
11 CPU (control means)
14 HDD controller (nonvolatile memory control means, nonvolatile memory control device)
141 Erased data storage unit (storage means)
142 Erase data writing unit (writing means)
15 HDD (nonvolatile storage means)

Claims (4)

Control means for controlling;
Non-volatile storage means for the control means to read and write data; and
Non-volatile memory control means for controlling reading and writing of data to the non-volatile storage means of the control means,
The non-volatile memory control means is an information processing apparatus comprising writing means for writing data in the non-volatile memory control means into the non-volatile storage means. The nonvolatile memory control means further comprises storage means for storing data received from the outside,
The information processing apparatus according to claim 1, wherein the writing unit writes the data stored in the storage unit into the nonvolatile storage unit.   The information processing apparatus according to claim 1, wherein the nonvolatile storage unit is detachable from the information processing apparatus. In a non-volatile memory control device that controls reading and writing of data with respect to the non-volatile storage means by the control means that performs control,
A nonvolatile memory control device comprising writing means for writing data in the nonvolatile memory control device into the nonvolatile storage means.

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