JP2006165393A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006165393A
JP2006165393A JP2004357081A JP2004357081A JP2006165393A JP 2006165393 A JP2006165393 A JP 2006165393A JP 2004357081 A JP2004357081 A JP 2004357081A JP 2004357081 A JP2004357081 A JP 2004357081A JP 2006165393 A JP2006165393 A JP 2006165393A
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post
hole
resin layer
sealing resin
semiconductor device
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JP4972280B2 (en
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Shingo Higuchi
晋吾 樋口
Takuya Kadoguchi
卓矢 門口
Osamu Miyata
修 宮田
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing damage of an external connection terminal on a post by stress concentration, and to provide its manufacturing method. <P>SOLUTION: The post 6 is formed in the through hole 51 of a sealing resin layer 5 to be lower by a stage than the surface of the layer 5 in such a shape that a gap occurs between a tip and the internal surface 511 of the through hole 51. A metallic ball 7 is provided on the tip of the post 6. The base end of the ball 7 has its center joined to the leading end surface 61 of the post 6, and has its periphery entering between a continuous surface 63 of the post 6 and the internal surface 511 of the hole 51 along the surface 63. Since the base end of the metallic ball 7 thus has no corner, stress concentration to the base end of the metallic ball 7 can be prevented and damage of the ball 7 due to the stress concentration can be prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、ＷＬ−ＣＳＰ（ウエハレベルチップスケールパッケージ：Wafer Level-Chip Scale Package）の半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device of WL-CSP (Wafer Level-Chip Scale Package) and a manufacturing method thereof.

最近、半導体装置の小型化、高機能化および高性能化を可能にするＷＬ−ＣＳＰの実用化が進んでいる。ＷＬ−ＣＳＰでは、ウエハ状態でパッケージング工程が完了され、ダイシングによって切り出された個々のチップのサイズがパッケージサイズとなる。
ＷＬ−ＣＳＰの半導体装置は、図５に示すように、半導体チップ１０１の表面がパッシベーション膜１０２で覆われている。このパッシベーション膜１０２には、半導体チップ１０１の表面に形成された内部配線の一部を電極パッド１０３として露出させるためのパッド開口１０４が形成されている。また、パッシベーション膜１０２上には、ポリイミド層１０５が積層されている。さらに、ポリイミド層１０５上には、再配線１０６が形成されており、この再配線１０６は、ポリイミド層１０５に貫通して形成された貫通孔１０７を介して電極パッド１０３に接続されている。そして、ポリイミド層１０５および再配線１０６上には、エポキシ樹脂からなる封止樹脂層１０８が積層され、再配線１０６は、その封止樹脂層１０８を貫通する円柱状のポスト１０９を介して、封止樹脂層１０８の表面に配設された半田ボール１１０に接続されている。ＷＬ−ＣＳＰの半導体装置は、半田ボール１１０が実装基板上のパッドに接続されることによって、実装基板への実装（実装基板に対する電気的および機械的な接続）が達成される。 Recently, practical application of WL-CSP that enables miniaturization, high functionality, and high performance of semiconductor devices has been advanced. In the WL-CSP, the packaging process is completed in a wafer state, and the size of each chip cut out by dicing becomes the package size.
In the WL-CSP semiconductor device, the surface of the semiconductor chip 101 is covered with a passivation film 102 as shown in FIG. In the passivation film 102, a pad opening 104 is formed for exposing a part of the internal wiring formed on the surface of the semiconductor chip 101 as the electrode pad 103. Further, a polyimide layer 105 is laminated on the passivation film 102. Further, a rewiring 106 is formed on the polyimide layer 105, and the rewiring 106 is connected to the electrode pad 103 through a through hole 107 formed so as to penetrate the polyimide layer 105. Then, a sealing resin layer 108 made of an epoxy resin is laminated on the polyimide layer 105 and the rewiring 106, and the rewiring 106 is sealed via a cylindrical post 109 penetrating the sealing resin layer 108. The solder ball 110 is connected to the surface of the stop resin layer 108. In the WL-CSP semiconductor device, the solder balls 110 are connected to pads on the mounting substrate, whereby mounting on the mounting substrate (electrical and mechanical connection to the mounting substrate) is achieved.

このような半導体装置の製造工程では、まず、複数の半導体チップが作り込まれたウエハが用意される。ウエハの表面は、パッシベーション膜１０２によって被覆されている。次いで、パッシベーション膜１０２上に、ポリイミド層１０５および再配線１０６が形成される。さらに、再配線１０６上の所定位置に、めっきなどの手法によってポスト１０９が形成された後、パッシベーション膜１０２上に、封止樹脂層１０８の材料であるエポキシ樹脂がポスト１０９を埋没させるように供給される。そして、そのエポキシ樹脂の硬化後に、エポキシ樹脂の表面がグラインダで研削されて、ポスト１０９の表面（先端面）がエポキシ樹脂から露出される。   In the manufacturing process of such a semiconductor device, first, a wafer in which a plurality of semiconductor chips are formed is prepared. The surface of the wafer is covered with a passivation film 102. Next, a polyimide layer 105 and a rewiring 106 are formed on the passivation film 102. Further, after a post 109 is formed at a predetermined position on the rewiring 106 by a technique such as plating, an epoxy resin, which is a material of the sealing resin layer 108, is supplied on the passivation film 102 so as to bury the post 109. Is done. After the epoxy resin is cured, the surface of the epoxy resin is ground with a grinder, and the surface (tip surface) of the post 109 is exposed from the epoxy resin.

ところが、ポスト１０９を形成する銅などの金属材料は、延性を有しているため、グラインダによるエポキシ樹脂の研削時に、そのグラインダにつられて、図５に仮想線で示すように、ポスト１０９の先端部が、封止樹脂層１０８（エポキシ樹脂）の表面上に延びて拡がる（だれる）。このようなポスト１０９のだれは、たとえば、複数のポスト１０９間での短絡などの問題を生じるおそれがある。   However, since the metal material such as copper forming the post 109 has ductility, when the epoxy resin is ground by the grinder, the tip of the post 109 is picked up by the grinder as shown by a virtual line in FIG. The portion extends and spreads on the surface of the sealing resin layer 108 (epoxy resin). Any one of the posts 109 may cause a problem such as a short circuit between the plurality of posts 109.

そこで、グラインダによるエポキシ樹脂の研削後には、封止樹脂層１０８の表面にアンモニア系のエッチング液が供給されて、封止樹脂層１０８の表面に延びて拡がった金属材料を除去するためのエッチング処理が行われる。このエッチング処理の後、ポスト１０９の先端面（表面）に半田ボール１１０が形成される。そして、ウエハ内の各半導体チップ間に設定されたダイシングラインに沿って、パッシベーション膜１０２および封止樹脂層１０８とともにウエハが切断（ダイシング）されることにより、図５に示すＷＬ−ＣＳＰの半導体装置が得られる。
特開２００３−３１７６８号公報 Therefore, after grinding the epoxy resin by the grinder, an etching process is performed to remove the metal material that is extended to the surface of the sealing resin layer 108 by supplying an ammonia-based etching solution to the surface of the sealing resin layer 108. Is done. After this etching process, a solder ball 110 is formed on the front end surface (surface) of the post 109. Then, the wafer is cut (diced) together with the passivation film 102 and the sealing resin layer 108 along the dicing line set between the semiconductor chips in the wafer, whereby the WL-CSP semiconductor device shown in FIG. Is obtained.
JP 2003-31768 A

しかるに、エッチング処理後は、図５に示すように、ポスト１０９の先端面の位置が封止樹脂層１０８の表面の位置よりも一段低くなり、ポスト１０９の先端面は、封止樹脂層１０８のポスト１０９と接触する側面（ポスト１０９を貫通させる貫通孔の内面）に対して直角をなす平坦面となる。そのため、ポスト１０９の先端面上に形成される半田ボール１１０は、ポスト１０９の軸線方向に沿って切断したときの断面において、ポスト１０９側の端部（基端部）が、ポスト１０９の先端面および封止樹脂層１０８の側面に接する直角な角部１１１を有する形状となる。このような角部１１１には応力が集中しやすく、その応力によって、半田ボール１１０にクラックが入るなどの損傷を生じるおそれがあった。   However, after the etching process, as shown in FIG. 5, the position of the tip surface of the post 109 is one step lower than the position of the surface of the sealing resin layer 108, and the tip surface of the post 109 is It becomes a flat surface that is perpendicular to the side surface that contacts the post 109 (the inner surface of the through hole through which the post 109 passes). Therefore, the solder ball 110 formed on the front end surface of the post 109 has an end portion (base end portion) on the post 109 side in the cross section when cut along the axial direction of the post 109. And it becomes a shape which has the right-angle corner | angular part 111 which touches the side surface of the sealing resin layer 108. Stress is likely to concentrate on the corner portion 111, and the stress may cause damage such as cracks in the solder ball 110.

そこで、この発明の目的は、ポスト上の外部接続端子の応力集中による損傷を防止することができる半導体装置およびその製造方法を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing damage due to stress concentration of external connection terminals on a post and a method for manufacturing the same.

前記の目的を達成するための請求項１記載の発明は、ＷＬ−ＣＳＰの半導体装置であって、半導体チップ（１）と、この半導体チップの表面上に積層され、前記半導体チップの表面と直交する方向に貫通して形成された貫通孔（５１）を有する封止樹脂層（５）と、前記貫通孔内において、少なくとも先端部と前記貫通孔の内面（５１１）との間に隙間を空けて設けられた金属製のポスト（６）と、このポストの先端部上に配置され、前記封止樹脂層の表面から突出する外部接続端子（７）とを含むことを特徴とする半導体装置である。   The invention according to claim 1 to achieve the above object is a WL-CSP semiconductor device, wherein the semiconductor chip (1) is stacked on the surface of the semiconductor chip and orthogonal to the surface of the semiconductor chip. A gap is formed between at least the tip portion and the inner surface (511) of the through hole in the through hole and the sealing resin layer (5) formed through the through hole (51) formed in a through direction. And a metal post (6) provided on the tip of the post and an external connection terminal (7) protruding from the surface of the sealing resin layer. is there.

なお、括弧内の英数字は、後述の実施形態における対応構成要素等を表す。以下、この項において同じ。
この構成によれば、ポストの先端部と封止樹脂層に形成された貫通孔の内面との間に隙間が形成されているので、外部接続端子の基端部は、ポストの先端面および貫通孔の内面に接するような角部を有しない。そのため、外部接続端子の基端部への応力集中を防止することができ、応力集中による外部接続端子の損傷を防止することができる。 In addition, the alphanumeric characters in parentheses represent corresponding components in the embodiments described later. The same applies hereinafter.
According to this configuration, since the gap is formed between the front end portion of the post and the inner surface of the through hole formed in the sealing resin layer, the base end portion of the external connection terminal is connected to the front end surface of the post and the through hole. There are no corners that contact the inner surface of the hole. Therefore, stress concentration on the base end portion of the external connection terminal can be prevented, and damage to the external connection terminal due to stress concentration can be prevented.

また、請求項２記載の発明は、前記外部接続端子は、前記ポスト側の基端部が、前記ポストの先端部の表面に沿って、前記ポストの先端部と前記貫通孔の内面との間の隙間に入り込んでいることを特徴とする請求項１記載の半導体装置である。
この構成によれば、外部接続端子の基端部は、ポストの先端部の表面に沿って、ポストの先端部と貫通孔の内面との間の隙間に入り込み、角部を有していないので、外部接続端子の基端部への応力集中を一層防止することができ、応力集中による外部接続端子の損傷を効果的に防止することができる。 According to a second aspect of the present invention, in the external connection terminal, the base end portion on the post side is between the tip end portion of the post and the inner surface of the through hole along the surface of the tip end portion of the post. The semiconductor device according to claim 1, wherein the semiconductor device enters the gap.
According to this configuration, the proximal end portion of the external connection terminal enters the gap between the distal end portion of the post and the inner surface of the through hole along the surface of the distal end portion of the post, and has no corner portion. Further, stress concentration on the base end portion of the external connection terminal can be further prevented, and damage to the external connection terminal due to stress concentration can be effectively prevented.

また、請求項３記載の発明は、前記ポストは、前記封止樹脂層の表面とほぼ平行な平坦状の先端面（６１）と、前記貫通孔の内面に対して先端側ほど大きな隙間を生じるように傾斜する傾斜側面（６２）と、前記貫通孔の貫通方向に沿った断面形状が略円弧状を有し、前記先端面と前記傾斜側面とを連続する連続面（６３）とを備えていることを特徴とする請求項１または２に記載の半導体装置である。   According to a third aspect of the present invention, the post has a flat front end surface (61) substantially parallel to the surface of the sealing resin layer and a larger gap toward the front end side with respect to the inner surface of the through hole. Inclined side surface (62) which inclines like this, and the cross-sectional shape along the penetration direction of the said through-hole has a substantially circular arc shape, The continuous surface (63) which continues the said front end surface and the said inclined side surface is provided. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.

この構成によれば、外部接続端子の基端部を、断面略円弧状の連続面に沿って、その連続面と貫通孔の内面との間の隙間に確実に入り込ませることができ、さらには傾斜側面と貫通孔の内面との間の隙間にまで入り込ませることもできる。
また、請求項４記載の発明は、前記ポストは、前記封止樹脂層の表面とほぼ平行な平坦状の先端面（６１）と、前記貫通孔の内面に対して先端側ほど大きな隙間を生じるように傾斜する傾斜側面（６２）と、前記貫通孔の内面に対して前記傾斜側面よりも大きな角度で傾斜し、前記先端面と前記傾斜側面とを連続する連続面（６４）とを備えていることを特徴とする請求項１または２に記載の半導体装置である。 According to this configuration, the base end portion of the external connection terminal can surely enter the gap between the continuous surface and the inner surface of the through hole along the continuous surface having a substantially arc-shaped cross section. It is also possible to enter the gap between the inclined side surface and the inner surface of the through hole.
According to a fourth aspect of the present invention, the post has a flat front end surface (61) substantially parallel to the surface of the sealing resin layer and a larger gap toward the front end side with respect to the inner surface of the through hole. And a continuous surface (64) that is inclined at a larger angle than the inclined side surface with respect to the inner surface of the through hole and that continues the tip surface and the inclined side surface. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.

この構成によれば、外部接続端子の基端部を、傾斜側面よりも大きな角度で傾斜する連続面に沿って、その連続面と貫通孔の内面との間の隙間に確実に入り込ませることができ、さらには傾斜側面と貫通孔の内面との間の隙間にまで入り込ませることもできる。
また、請求項５記載の発明は、ＷＬ−ＣＳＰの半導体装置を製造する方法であって、複数の半導体チップ（１）が作り込まれたウエハ（Ｗ）の表面上に、金属製のポスト（６）を形成するポスト形成工程と、前記ウエハの表面上に、前記ポストを埋没させるように封止樹脂層（５）を形成する封止樹脂層形成工程と、前記封止樹脂層の表面を研削して、前記ポストの先端面を前記封止樹脂層から露出させる研削工程と、この研削工程の後、前記封止樹脂層の表面上に硫酸過水系のエッチング液を供給して、前記ポストの一部をエッチングするエッチング工程とを含むことを特徴とする半導体装置の製造方法である。 According to this configuration, the base end portion of the external connection terminal can surely enter the gap between the continuous surface and the inner surface of the through hole along the continuous surface inclined at a larger angle than the inclined side surface. It is also possible to enter the gap between the inclined side surface and the inner surface of the through hole.
The invention according to claim 5 is a method of manufacturing a WL-CSP semiconductor device, wherein a metal post (on a surface of a wafer (W) in which a plurality of semiconductor chips (1) are formed is provided. 6) forming a post-forming step, forming a sealing resin layer (5) on the surface of the wafer so as to bury the post, and a surface of the sealing resin layer. Grinding to expose the front end surface of the post from the sealing resin layer, and after the grinding step, supplying a sulfuric acid / hydrogen peroxide-based etching solution onto the surface of the sealing resin layer, the post An etching process for etching a part of the semiconductor device.

この方法により、請求項１ないし４に記載の半導体装置を製造することができる。
また、硫酸過水系のエッチング液を用いることによって、封止樹脂層上にレジストパターンなどを形成することなく、ポストを、そのポストの先端部と封止樹脂層においてポストを貫通する貫通孔の内面との間に隙間が生じるような形状にエッチングすることができる。そのため、封止樹脂層上に適当なレジストパターンを形成した後、その封止樹脂層上にアンモニア系のエッチング液を供給することによってポストを形成する手法に比べて、より簡単にポストを形成することができる。 By this method, the semiconductor device according to claims 1 to 4 can be manufactured.
Further, by using a sulfuric acid / hydrogen peroxide-based etching solution, without forming a resist pattern or the like on the sealing resin layer, the post can be connected to the tip of the post and the inner surface of the through hole that penetrates the post in the sealing resin layer. Can be etched into a shape in which a gap is formed between the two. Therefore, after forming an appropriate resist pattern on the sealing resin layer, the post is formed more easily than a method of forming a post by supplying an ammonia-based etching solution onto the sealing resin layer. be able to.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明の一実施形態に係る半導体装置の構成を示す断面図である。この半導体装置は、ＷＬ−ＣＳＰの半導体装置であり、半導体チップ１と、この半導体チップ１の表面（機能素子が形成されている側の面）を被覆するパッシベーション膜（表面保護膜）２と、このパッシベーション膜２上に積層された応力緩和層３と、この応力緩和層３上に形成された再配線４と、この再配線４上に積層された封止樹脂層５と、この封止樹脂層５を貫通して設けられたポスト６と、このポスト６の先端部上に配置された外部接続端子としての金属ボール７とを備えている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a WL-CSP semiconductor device, and includes a semiconductor chip 1 and a passivation film (surface protective film) 2 covering the surface of the semiconductor chip 1 (the surface on which the functional elements are formed), The stress relaxation layer 3 laminated on the passivation film 2, the rewiring 4 formed on the stress relaxation layer 3, the sealing resin layer 5 laminated on the rewiring 4, and the sealing resin A post 6 provided through the layer 5 and a metal ball 7 as an external connection terminal disposed on the tip of the post 6 are provided.

半導体チップ１は、たとえば、平面視略矩形状に形成されている。
パッシベーション膜２は、酸化シリコンまたは窒化シリコンからなり、半導体チップ１の表面全域を被覆するように形成されている。このパッシベーション膜２には、半導体チップ１の表面に形成されたアルミニウムなどの金属からなる内部配線の一部を、電極パッド８として露出させるためのパッド開口２１が形成されている。 The semiconductor chip 1 is formed, for example, in a substantially rectangular shape in plan view.
The passivation film 2 is made of silicon oxide or silicon nitride and is formed so as to cover the entire surface of the semiconductor chip 1. In the passivation film 2, a pad opening 21 is formed for exposing a part of the internal wiring made of metal such as aluminum formed on the surface of the semiconductor chip 1 as the electrode pad 8.

応力緩和層３は、たとえば、ポリイミドからなり、パッシベーション膜の表面全域を被覆するように形成されている。この応力緩和層３は、半導体装置に応力が加わったときに、その応力を吸収して緩和する機能を有している。また、応力緩和層３には、電極パッド８と対向する位置にコンタクト孔３１が貫通して形成されている。
再配線４は、たとえば、銅などの金属材料を用いて形成され、応力緩和層３の表面に沿って延びている。この再配線４は、応力緩和層３のコンタクト孔３１を介して、電極パッド８に接続されている。 The stress relaxation layer 3 is made of polyimide, for example, and is formed so as to cover the entire surface of the passivation film. The stress relaxation layer 3 has a function of absorbing and relaxing the stress applied to the semiconductor device. Further, a contact hole 31 is formed through the stress relaxation layer 3 at a position facing the electrode pad 8.
The rewiring 4 is formed using, for example, a metal material such as copper, and extends along the surface of the stress relaxation layer 3. The rewiring 4 is connected to the electrode pad 8 through the contact hole 31 of the stress relaxation layer 3.

封止樹脂層５は、たとえば、エポキシ樹脂からなり、パッシベーション膜２、応力緩和層３および再配線４の表面を覆うように形成されている。この封止樹脂層５には、再配線４上において、たとえば、円筒状の内面５１１を有する貫通孔５１が、半導体チップ１の表面と直交する方向に貫通して形成されている。また、封止樹脂層５は、表面が平坦面に形成されるとともに、その側面が半導体チップ１の側面と面一に形成されている。これによって、この半導体装置は、平面視におけるサイズが半導体チップ１のサイズと等しい略直方体形状を有している。   The sealing resin layer 5 is made of, for example, an epoxy resin and is formed so as to cover the surfaces of the passivation film 2, the stress relaxation layer 3, and the rewiring 4. In the sealing resin layer 5, on the rewiring 4, for example, a through hole 51 having a cylindrical inner surface 511 is formed so as to penetrate in a direction orthogonal to the surface of the semiconductor chip 1. The sealing resin layer 5 has a flat surface and a side surface that is flush with the side surface of the semiconductor chip 1. Thus, the semiconductor device has a substantially rectangular parallelepiped shape whose size in plan view is equal to the size of the semiconductor chip 1.

ポスト６は、たとえば、銅などの金属からなり、封止樹脂層５の貫通孔５１内において、封止樹脂層５の表面よりも一段低く、少なくとも先端部と貫通孔５１の内面５１１との間に隙間を生じるような形状に形成されている。具体的には、図２に示すように、ポスト６は、封止樹脂層５の表面とほぼ平行な平坦状の先端面６１と、貫通孔５１の内面５１１に対して先端側（再配線４側と反対側）ほど大きな隙間を生じるように傾斜する傾斜側面６２と、貫通孔５１の貫通方向（半導体チップ１の表面と直交する方向）に沿った断面形状が略円弧状を有し、先端面６１と傾斜側面６２とを連続する連続面６３とを有する形状に形成されている。これにより、ポスト６の連続面６３と貫通孔５１の内面５１１との間には、ポスト６の傾斜側面６２と貫通孔５１の内面５１１との間の隙間よりも大きな隙間が形成され、ポスト６の傾斜側面６２と貫通孔５１の内面５１１との間の隙間は、再配線４に近づくにつれて徐々に間隔が狭まっている。   The post 6 is made of, for example, a metal such as copper, and is one step lower than the surface of the sealing resin layer 5 in the through hole 51 of the sealing resin layer 5, and at least between the tip and the inner surface 511 of the through hole 51. It is formed in a shape that creates a gap. Specifically, as shown in FIG. 2, the post 6 has a flat front end surface 61 substantially parallel to the surface of the sealing resin layer 5 and a front end side (rewiring 4) with respect to the inner surface 511 of the through hole 51. And the cross-sectional shape along the penetrating direction of the through hole 51 (direction perpendicular to the surface of the semiconductor chip 1) has a substantially arc shape, It is formed in a shape having a continuous surface 63 that continues the surface 61 and the inclined side surface 62. Thereby, a gap larger than the gap between the inclined side surface 62 of the post 6 and the inner surface 511 of the through hole 51 is formed between the continuous surface 63 of the post 6 and the inner surface 511 of the through hole 51. The gap between the inclined side surface 62 and the inner surface 511 of the through hole 51 gradually decreases as the distance from the rewiring 4 approaches.

金属ボール７は、たとえば、半田などの金属材料を用いてボール状に形成されており、ポスト６を介して再配線４と電気的に接続されている。したがって、この金属ボール７が実装基板上のパッドに接続されることによって、この半導体装置の実装基板への実装（実装基板に対する電気的および機械的な接続）が達成される。また、金属ボール７の基端部は、その中央部が、ポスト６の先端面６１に接合されるとともに、中央部の周囲の周縁部が、ポスト６の連続面６３に沿って、その連続面６３と貫通孔５１の内面５１１との間の隙間に入り込み、さらには傾斜側面６２と貫通孔５１の内面との間の隙間にまで入り込んでいる。   The metal ball 7 is formed in a ball shape using, for example, a metal material such as solder, and is electrically connected to the rewiring 4 via the post 6. Therefore, when the metal balls 7 are connected to the pads on the mounting board, the semiconductor device is mounted on the mounting board (electrical and mechanical connection to the mounting board). Further, the base end portion of the metal ball 7 is joined at its central portion to the distal end surface 61 of the post 6, and the peripheral edge around the central portion is a continuous surface along the continuous surface 63 of the post 6. 63 and the inner surface 511 of the through hole 51, and further enters the gap between the inclined side surface 62 and the inner surface of the through hole 51.

このような構成によれば、ポスト６の先端部と封止樹脂層５に形成された貫通孔５１の内面５１１との間に隙間が形成されているので、金属ボール７の基端部は、ポスト６の先端面６１および貫通孔５１の内面５１１に接するような角部を有しない。そのため、金属ボール７の基端部への応力集中を防止することができ、応力集中による金属ボール７の損傷を防止することができる。   According to such a configuration, since a gap is formed between the front end portion of the post 6 and the inner surface 511 of the through hole 51 formed in the sealing resin layer 5, the base end portion of the metal ball 7 is There are no corners that contact the tip surface 61 of the post 6 and the inner surface 511 of the through hole 51. Therefore, stress concentration on the base end portion of the metal ball 7 can be prevented, and damage to the metal ball 7 due to stress concentration can be prevented.

また、この実施形態では、金属ボール７の基端部が、断面略円弧状の連続面６３に沿って、その連続面６３と貫通孔５１の内面５１１との間の隙間に入り込み、さらには傾斜側面６２と貫通孔５１の内面との間の隙間にまで入り込んでおり、角部を有していないので、外部接続端子の基端部への応力集中を一層防止することができ、応力集中による外部接続端子の損傷を効果的に防止することができる。   Further, in this embodiment, the base end portion of the metal ball 7 enters the gap between the continuous surface 63 and the inner surface 511 of the through hole 51 along the continuous surface 63 having a substantially arc-shaped cross section, and is further inclined. Since it penetrates into the gap between the side surface 62 and the inner surface of the through hole 51 and does not have a corner, stress concentration on the base end of the external connection terminal can be further prevented. Damage to the external connection terminals can be effectively prevented.

図３は、この半導体装置の製造工程を工程順に示す断面図である。まず、図３（ａ）に示すように、複数の半導体チップ１が作り込まれたウエハＷの表面を被覆するパッシベーション膜２にパッド開口２１を形成した後、さらに、そのパッシベーション膜２上に応力緩和層３、再配線４およびポスト６を形成する。
次に、図３（ｂ）に示すように、パッシベーション膜２上に、封止樹脂層５の材料である樹脂（たとえば、エポキシ樹脂）がポスト６を埋没させるように供給される。そして、その樹脂の硬化後に、樹脂（封止樹脂層５）の表面がグラインダで研削されて、図３（ｃ）に示すように、ポスト６の表面（先端面）が封止樹脂層５から露出される。このとき、ポスト６を形成する金属材料が、その延性のために、グラインダにつられて、封止樹脂層５の表面における貫通孔５１の周囲にだれる。 FIG. 3 is a cross-sectional view showing the manufacturing process of this semiconductor device in the order of steps. First, as shown in FIG. 3A, after a pad opening 21 is formed in the passivation film 2 that covers the surface of the wafer W on which a plurality of semiconductor chips 1 are formed, a stress is further applied to the passivation film 2. Relaxation layer 3, rewiring 4 and post 6 are formed.
Next, as shown in FIG. 3B, a resin (for example, epoxy resin) that is a material of the sealing resin layer 5 is supplied on the passivation film 2 so as to bury the post 6. After the resin is cured, the surface of the resin (sealing resin layer 5) is ground by a grinder, and the surface (tip surface) of the post 6 is removed from the sealing resin layer 5 as shown in FIG. Exposed. At this time, the metal material forming the post 6 is drawn around the through hole 51 on the surface of the sealing resin layer 5 by the grinder due to its ductility.

そこで、樹脂研削後、そのようなポスト６のだれた部分を除去するために、封止樹脂層５の表面に硫酸過水系のエッチング液（硫酸および過酸化水素水を含むエッチング液）が供給される。この硫酸過水系のエッチング液によって、ポスト６は、図３（ｄ）に示すように、その先端面が封止樹脂層５の表面よりも一段低い位置に先端面６１を有し、少なくとも先端部と貫通孔５１の内面５１１との間に隙間を生じるような形状にエッチングされる。   Therefore, after removing the resin, a sulfuric acid / hydrogen peroxide-based etching solution (an etching solution containing sulfuric acid and hydrogen peroxide solution) is supplied to the surface of the sealing resin layer 5 in order to remove the slack portion of the post 6. The As shown in FIG. 3D, the post 6 has a tip surface 61 at a position lower than the surface of the sealing resin layer 5 by the sulfuric acid / hydrogen peroxide-based etching solution, and at least the tip portion. And a shape that creates a gap between the inner surface 511 of the through hole 51 and the through hole 51.

このような形状（具体的には、図２を参照して説明した形状）のポスト６は、封止樹脂層５上に適当なレジストパターンを形成した後、その封止樹脂層５上にアンモニア系のエッチング液を供給することによっても形成することができるが、硫酸過水系のエッチング液を用いることによって、レジストパターンの形成工程を省略することができ、より簡単にポスト６を形成することができる。   The post 6 having such a shape (specifically, the shape described with reference to FIG. 2) forms an appropriate resist pattern on the sealing resin layer 5, and then forms ammonia on the sealing resin layer 5. However, by using a sulfuric acid / hydrogen peroxide-based etchant, the step of forming a resist pattern can be omitted and the post 6 can be formed more easily. it can.

エッチング処理の後、図３（ｅ）に示すように、ポスト６の先端面に金属ボール７が形成される。そして、ウエハＷ内の各半導体チップ１間に設定されたダイシングラインに沿って、パッシベーション膜２および封止樹脂層５とともにウエハＷが切断（ダイシング）されることにより、図１に示す構成の半導体装置が得られる。
図４は、ポスト６の他の形状を示す断面図である。この図４において、図２に示された各部に対応する部分には、図２の場合と同一の参照符号を付して示す。 After the etching process, a metal ball 7 is formed on the tip surface of the post 6 as shown in FIG. Then, along the dicing line set between the semiconductor chips 1 in the wafer W, the wafer W is cut (diced) together with the passivation film 2 and the sealing resin layer 5, so that the semiconductor having the configuration shown in FIG. A device is obtained.
FIG. 4 is a cross-sectional view showing another shape of the post 6. 4, portions corresponding to the respective portions shown in FIG. 2 are denoted by the same reference numerals as those in FIG.

この図４に示すポスト６は、先端面６１と傾斜側面６２とを連続する連続面６４が、貫通孔５１の内面５１１に対して傾斜側面６２よりも大きな角度で傾斜しており、その先端部の形状が円錐台形状に形成されている。このような形状によっても、金属ボール７の基端部を、連続面６４に沿って、その連続面６４と貫通孔５１の内面５１１との間の隙間に確実に入り込ませることができ、さらには傾斜側面６２と貫通孔５１の内面５１１との間の隙間にまで入り込ませることもできる。   In the post 6 shown in FIG. 4, the continuous surface 64 that continues the tip surface 61 and the inclined side surface 62 is inclined with respect to the inner surface 511 of the through hole 51 at a larger angle than the inclined side surface 62, Is formed into a truncated cone shape. Even with such a shape, the base end portion of the metal ball 7 can surely enter the gap between the continuous surface 64 and the inner surface 511 of the through hole 51 along the continuous surface 64, It is also possible to enter the gap between the inclined side surface 62 and the inner surface 511 of the through hole 51.

以上、この発明の２つの実施形態を説明したが、この発明はさらに他の形態で実施することもできる。たとえば、ポスト６は、封止樹脂層５の貫通孔５１内において、封止樹脂層５の表面よりも一段低く、少なくとも先端部と貫通孔５１の内面５１１との間に隙間を生じるような形状に形成されていれば、図２および図４に示す形状とは異なる形状に形成されていてもよい。   While the two embodiments of the present invention have been described above, the present invention can also be implemented in other forms. For example, the post 6 has a shape that is one step lower than the surface of the sealing resin layer 5 in the through hole 51 of the sealing resin layer 5, and creates a gap between at least the tip portion and the inner surface 511 of the through hole 51. If it is formed in, it may be formed in the shape different from the shape shown in FIG. 2 and FIG.

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of the matters described in the claims.

この発明の一実施形態に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. ポストの近傍を示す断面図である。It is sectional drawing which shows the vicinity of a post | mailbox. 上記半導体装置の製造工程を工程順に示す断面図である。It is sectional drawing which shows the manufacturing process of the said semiconductor device in order of a process. ポストの他の形状を示す断面図である。It is sectional drawing which shows the other shape of a post | mailbox. 従来のＷＬ−ＣＳＰの半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional WL-CSP semiconductor device.

符号の説明Explanation of symbols

１ 半導体チップ
２ パッシベーション膜
５ 封止樹脂層
６ ポスト
７ 金属ボール
５１ 貫通孔
６１ 先端面
６２ 傾斜側面
６３ 連続面
６４ 連続面
５１１ 内面
Ｗ ウエハ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Passivation film 5 Sealing resin layer 6 Post 7 Metal ball 51 Through-hole 61 Front end surface 62 Inclined side surface 63 Continuous surface 64 Continuous surface 511 Inner surface W Wafer

Claims (5)

ＷＬ−ＣＳＰの半導体装置であって、
半導体チップと、
この半導体チップの表面上に積層され、前記半導体チップの表面と直交する方向に貫通して形成された貫通孔を有する封止樹脂層と、
前記貫通孔内において、少なくとも先端部と前記貫通孔の内面との間に隙間を空けて設けられた金属製のポストと、
このポストの先端部上に配置され、前記封止樹脂層の表面から突出する外部接続端子とを含むことを特徴とする半導体装置。 A WL-CSP semiconductor device,
A semiconductor chip;
A sealing resin layer having a through hole laminated on the surface of the semiconductor chip and formed in a direction perpendicular to the surface of the semiconductor chip;
In the through hole, at least a metal post provided with a gap between the tip and the inner surface of the through hole,
A semiconductor device comprising: an external connection terminal disposed on a front end portion of the post and protruding from the surface of the sealing resin layer. 前記外部接続端子は、前記ポスト側の基端部が、前記ポストの先端部の表面に沿って、前記ポストの先端部と前記貫通孔の内面との間の隙間に入り込んでいることを特徴とする請求項１記載の半導体装置。   The external connection terminal is characterized in that a base end portion on the post side enters a gap between the front end portion of the post and the inner surface of the through hole along the surface of the front end portion of the post. The semiconductor device according to claim 1. 前記ポストは、前記封止樹脂層の表面とほぼ平行な平坦状の先端面と、前記貫通孔の内面に対して先端側ほど大きな隙間を生じるように傾斜する傾斜側面と、前記貫通孔の貫通方向に沿った断面形状が略円弧状を有し、前記先端面と前記傾斜側面とを連続する連続面とを備えていることを特徴とする請求項１または２に記載の半導体装置。   The post has a flat front end surface substantially parallel to the surface of the sealing resin layer, an inclined side surface inclined so as to form a larger gap toward the front end side with respect to the inner surface of the through hole, and a through hole of the through hole. 3. The semiconductor device according to claim 1, wherein a cross-sectional shape along a direction has a substantially arc shape and includes a continuous surface that continues the tip surface and the inclined side surface. 4. 前記ポストは、前記封止樹脂層の表面とほぼ平行な平坦状の先端面と、前記貫通孔の内面に対して先端側ほど大きな隙間を生じるように傾斜する傾斜側面と、前記貫通孔の内面に対して前記傾斜側面よりも大きな角度で傾斜し、前記先端面と前記傾斜側面とを連続する連続面とを備えていることを特徴とする請求項１または２に記載の半導体装置。   The post has a flat front end surface substantially parallel to the surface of the sealing resin layer, an inclined side surface inclined so as to form a larger gap toward the front end side with respect to the inner surface of the through hole, and an inner surface of the through hole. The semiconductor device according to claim 1, further comprising: a continuous surface that is inclined with respect to the inclined side surface at a larger angle than the inclined side surface and that continues the tip surface and the inclined side surface. ＷＬ−ＣＳＰの半導体装置を製造する方法であって、
複数の半導体チップが作り込まれたウエハの表面上に、金属製のポストを形成するポスト形成工程と、
前記ウエハの表面上に、前記ポストを埋没させるように封止樹脂層を形成する封止樹脂層形成工程と、
前記封止樹脂層の表面を研削して、前記ポストの先端面を前記封止樹脂層から露出させる研削工程と、
この研削工程の後、前記封止樹脂層の表面上に硫酸過水系のエッチング液を供給して、前記ポストの一部をエッチングするエッチング工程とを含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a WL-CSP semiconductor device,
A post forming step of forming a metal post on the surface of a wafer on which a plurality of semiconductor chips are formed;
A sealing resin layer forming step of forming a sealing resin layer on the surface of the wafer so as to bury the post;
Grinding the surface of the sealing resin layer to expose the front end surface of the post from the sealing resin layer;
A method of manufacturing a semiconductor device comprising: an etching step of etching a part of the post by supplying a sulfuric acid / hydrogen peroxide-based etching solution onto the surface of the sealing resin layer after the grinding step.
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