JP2006165291A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the generation of obstacles such as the generation of void near a wiring, disconnection or the like without applying any big change on a conventional process, in reference to the multi-layer interconnection of a detailed/highly integrated semiconductor device. <P>SOLUTION: In reference to the arrangement structure of an upper layer wiring and a lower layer wiring which are neighbored up-and-down to the multi-layer wiring and via connecting them electrically, when the width of the lower layer wiring is specified so as to be same as the sectional diameter of the via when it is seen from the orthogonal direction to the surface of a semiconductor substrate, the center line of sectional diameter of the via is deviated from the center line of the wiring width of the lower layer wiring with each other. Further, the via is contacted with the side wall of the lower layer wiring at that time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a highly reliable multilayer wiring structure in a highly integrated semiconductor device and a manufacturing method thereof.

  Along with the high integration of semiconductor devices and the reduction in chip size, the miniaturization and multilayering of wiring inside semiconductor elements are being accelerated. In the latest 90 nm node (generation) Si semiconductor devices that are currently on the market, the minimum line width of the wiring is about 120-140 nm, but sample shipment is about to begin in 2005. In a node (generation) device, the value is expected to be about 100 nm or less. In a semiconductor device formed with such fine wiring, wiring having a total length of up to several kilometers is integrated in one chip.

  The wiring of such semiconductor devices is becoming more complex and highly integrated as the generation progresses, and as a result, ensuring the reliability of the wiring has become increasingly important. The most serious deterioration of wiring reliability is the stress migration phenomenon and the electromigration phenomenon.

The former stress migration phenomenon is a phenomenon in which metal atoms diffuse using the residual stress generated by the difference in thermal expansion coefficient between the wiring metal and the insulating film as a driving force, and finally the wiring is disconnected. This phenomenon is known to occur in both Al wiring and Cu wiring. Klema et al. (See Non-Patent Document 1), etc. T. T. et al. Ogawa et al. (See Non-Patent Document 2) and the like. In the following discussion, the damascene Cu wiring, which is the current typical wiring structure, is mainly taken into consideration, but the same discussion holds even if the main constituent metal of the damascene wiring is other than Cu. E. T. T. et al. According to Ogawa et al., The stress migration phenomenon is caused by the fact that a large amount of vacancy originally contained in the metal diffuses and gathers in the vicinity of the via which is a stress-specific part, resulting in voids in the vicinity of the via. It is supposed to take a process of forming and eventually breaking the wire as the void grows.
J. Klema et al, International Reliability of Physics Symposium 1984 Proceedings, PP1 ET Ogawa et al, International Reliability of Physics Symposium 2002 Proceedings, PP312 On the other hand, the electromigration phenomenon is caused by the fact that the metal electrons that make up the wiring are caused by the electron wind caused by the high-density electron flow caused by the current flowing through the device It is a moving phenomenon. This phenomenon can cause voids and hillocks in the wiring, which can cause disconnection and short-circuiting between adjacent wirings, thereby reducing the reliability of the semiconductor device. Also in this case, it is known that a void is easily formed in the vicinity of the via on the cathode side where the flow of metal electrons is blocked by the barrier metal, and this leads to disconnection.

  As a countermeasure against the two phenomena that reduce the reliability described above, for example, it is effective to arrange a plurality of vias so that even if a void occurs in one of the vias, an electrical disconnection does not occur. It is a widely used method.

  However, this method can be applied only to a circuit having a wiring arrangement that has a sufficient wiring width and length so that a plurality of vias can be arranged. Further, making all the vias plural increases the circuit / chip area and leads to an increase in cost.

  An object of the present invention is to provide a semiconductor device having a more reliable multilayer wiring structure suitable for highly integrated semiconductor devices and a method for manufacturing the same, and in particular, for example, a damascene method that is generally used conventionally. In thin multi-layered wiring where the wiring width and via cross-sectional diameter are approximately the same without changing the wiring formation process, there are problems in the formation of voids near the via due to stress migration phenomenon and electromigration phenomenon, and disconnection It is an object of the present invention to provide a new semiconductor device having a wiring-via arrangement structure and a method for manufacturing the same.

  A semiconductor device according to the present invention includes two or more wiring layers formed on a semiconductor substrate, and vias that electrically connect upper and lower wirings formed in different wiring layers in the two or more wiring layers. The cross-sectional diameter of the via is the same as the wiring width in the wiring width direction diameter of the lower layer wiring and the wiring width in the longitudinal direction diameter of the lower layer wiring when viewed from the vertical direction of the semiconductor substrate surface It is the same or longer than that, and the center line of the cross-sectional diameter of the via and the center line of the wiring width of the lower layer wiring are formed to be shifted from each other.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a first wiring on a first wiring layer on a semiconductor substrate, a step of forming an insulating layer on the first wiring, and the insulating layer. When the opening is formed in a direction perpendicular to the semiconductor substrate surface, the cross-sectional diameter is the same as the wiring width in the wiring width direction diameter of the first wiring, and the diameter in the longitudinal direction of the first wiring is And electrically connected to the first wiring in which the center line of the cross-sectional diameter and the center line of the wiring width of the first wiring are shifted from each other. Forming a via and forming a second wiring electrically connected to the via in a second wiring layer on the via.

  In the semiconductor device of the present invention, the via connecting the upper and lower wirings of the multilayer wiring layer on the semiconductor substrate is formed to have substantially the same diameter as the lower wiring width, and the via center line and the lower wiring width center line are misaligned. Therefore, one end of the via connected to the lower layer wiring is placed outside the lower layer wiring corner, and the other end of the via end is placed within the lower layer wiring width. The stress-specific region is formed so as to at least halve the occurrence of the stress-specific region at the corner portion of the lower layer wiring. Since a void is easily generated in the stress singularity region generated in the wiring layer corner immediately under the via, which leads to a disconnection failure or the like, the semiconductor device of the present invention can achieve an effect of greatly reducing the disconnection failure or the like in the via.

The best embodiment of the present invention will be described below with reference to the drawings.
(1) Preliminary reliability test analysis for carrying out the invention First, an analysis by a reliability test is performed on a semiconductor integrated circuit on which a multilayer wiring film having vias is mounted by a conventionally performed method. It was.

  FIG. 1 is a diagram (cross-sectional view perpendicular to the longitudinal direction of the wiring) schematically showing an image obtained by observing a cross-section of the multilayer wiring film portion after the reliability test with a TEM (Transmission Electron Microscope). is there.

  The formation method of the multilayer wiring film of the integrated circuit used for the test is the same as the formation method of the semiconductor device of the present invention described later. That is, as shown in FIG. 1, after forming a hard mask film 2 (SiC, 50 nm) on an interlayer insulating film 1 (SiOC, 400 nm) formed on a semiconductor substrate (not shown), this and the interlayer insulating film 1 is opened, barrier metal 3 (Ta / TaN, 10 nm) is formed on the inner wall, and lower layer wiring 4 (Cu, width 140 nm, height 200 nm) and adjacent lower layer wiring 5 are formed by Cu damascene method. Next, after forming a cap film 6 (SiC, 50 nm), an interlayer insulating film 7 (SiOC, 400 nm) and then a hard mask film 8 (SiC, 50 nm) are formed, and the hard mask film 8, the interlayer insulating film 7, and the cap film 6 are formed. And a barrier metal 9 (Ta / TaN, 10 nm) is formed on the inner wall. Then, a via 10 (Cu, 140 nm, height 300 nm) and an upper layer wiring 11 (Cu, height 200 nm) having substantially the same diameter as the lower layer wiring 4 are formed by a Cu dual damascene method, and a cap film 12 (SiC) is formed thereon. , 50 nm) to obtain a sample for reliability test. At that time, as shown in FIG. 1, the via 10 and the lower layer wiring 4 having the same size as each other are formed by matching the corners (edges) without shifting the connection center position. ing.

  The reliability test was performed at a temperature of 250 ° C., and an electromigration test in which an electric signal was passed through the wiring and a stress migration test by being left at a high temperature were performed. As a result, although disconnection did not occur, voids were observed in the lower layer wiring portion indicated by V in the vicinity of the via on the cathode side as shown in FIG.

  This void was observed using an OBIRCH (Optical Beam Induced Resistance Change) method after the reliability test. This method irradiates an integrated circuit chip with an infrared laser and detects a current change accompanying a resistance change at that time. If there is a void or a defect in the current path, the temperature rises and the resistance rises at that point. Therefore, the abnormality occurrence part can be extracted with high sensitivity. This OBIRCH method finds a locally highly resistive part in an integrated circuit, cuts that part with a FIB (Focused Ion Beam), reveals the cross section, and observes the cross section using the TEM method. did.

  As a result, as described above, the void V was observed in the lower layer wiring portion in the vicinity of the via 10 on the cathode side. This phenomenon was observed when the wiring length of the lower layer wiring 4 exceeded 100 μm, and when it was 50 μm or less, the occurrence could not be found within the observation error range. This means that this occurs with long wires that will contain substantially more vacancy to form voids.

  On the other hand, the void V observed in this way was generated at a corner portion at the upper end of the wiring 4 in contact with the via 10. This phenomenon is caused by the fact that the wiring structure changes greatly in the vicinity of the via V. Therefore, as described above, the stress migration phenomenon occurs as a region having a specific stress distribution (stress singular region) occurs. It is considered that vacancies in the wiring are attracted to this region and voided.

  In both cases of electromigration and stress migration, voids forming voids have a higher probability of diffusing through the Cu / cap insulating film interface than at the Cu / barrier metal interface. This is because the bonding force at the interface is weaker at the Cu / cap insulating film interface, and thus the diffusion coefficient is larger. Since defects (voids) are preferentially generated at the corner portion at the upper end of the wiring, it is considered that the one-dimensional diffusion using the wiring corner portion as a diffusion path is a main diffusion path. In this case, in the corner portion, the three interfaces of Cu / cap insulating film / barrier metal intersect with each other, the bonding force is weaker than that of the Cu / cap insulating film interface, and the diffusion coefficient of holes is large. Because. In other words, the defect (void) in question here is considered to be a defect that occurs only when the via diameter and the wiring width are substantially equal so that the three interfaces and the via can intersect.

Such narrow wiring is the most frequently used for forming semiconductor devices, and therefore the reliability and overall degradation of the entire device are greatly reduced, even if there is a slight probability of abnormalities or deterioration of the narrow wiring. Therefore, there is a demand for a semiconductor device having a low probability of occurrence of defects as described above.
(2) Implementation Configuration Example of the Present Invention A schematic diagram of a typical implementation configuration example of the multilayer wiring structure of the present invention is shown in FIG. Each component of each number given in the figure indicates the same component as the number given in FIG. FIG. 2 is a cross-sectional view passing through the central axis of the via 10 and perpendicular to the longitudinal direction of the wiring (the lower layer wiring 4, the adjacent lower layer wiring 5, and the upper layer wiring 11). Here, regarding the upper portion of the lower layer wiring 4 on the side facing the via 10, one corner (left side in the drawing) is a corner portion A and the other corner (right side in the drawing) is a corner portion B.

  In this figure, with respect to the positional relationship between the lower layer wiring 4 and the bottom of the via 10, one corner portion A of the lower layer wiring 4 is arranged by shifting the sectional center line of the via 10 and the center line of the width of the lower layer wiring 4. Is not in contact with the via 10. The other corner B of the lower wiring 4 is in contact with the via 10.

  In this manner, by disposing the via 10 and the lower layer wiring 4 in a shifted manner, the influence of the stress due to the via is reduced in the corner portion A. Therefore, the possibility that holes are gathered is greatly reduced, and voids are not easily formed. On the other hand, since the influence of the via 10 remains in the corner portion B, the possibility that a void is formed remains here. However, since the void formation probability is approximately halved in this arrangement, the disconnection life of the semiconductor device of the present invention can be greatly extended.

  In the example of FIG. 2, the vias 10 are arranged so as to be shifted from each other, and the bottom of the via 10 is lowered below the upper end of the lower layer wiring 4. By carrying out like this, the effect for reducing the probability of the disconnection failure in the corner part B can be expected. First, paying attention to the structure in which the barrier metal 9 of the via 10 and the barrier metal 3 on the side wall of the lower layer wiring 4 are in contact with each other, even if the diffused holes gather in the corner portion B, voids grow there. However, since a current can flow through the barrier metal where the side wall of the lower layer wiring 4 and the via 10 are in contact with each other, the possibility of disconnection failure is further reduced. Further, since the via 10 has a structure extending along the side wall of the lower layer wiring 4, the mutual contact area is enlarged, and even if a void is formed in the corner portion B, the current through the enlarged contact side wall is increased. There is a high possibility that the service life will be secured and the life until disconnection will be prolonged. At this time, it is also effective to increase the contact area between the lower layer wiring 4 and the via 10 by increasing the depth of the via correspondingly when the deviation between the via and the lower layer wiring is increased.

  Further, in general, a leakage current between adjacent wirings often flows on the boundary surface between the laminated hard mask film and the cap film. According to the structure of the present invention of FIG. 2, the hard mask film 2 and the cap film 6 between the lower layer wiring 4 and the adjacent lower layer wiring 5 are blocked by the strong barrier metal 9 of the via 10 extending downward. Another effect of reducing leakage current can be expected.

In order to create a semiconductor device having such a multilayer wiring structure, it is possible to use almost the conventional wiring process as it is by simply making a new regulation regarding the layout relationship between the wiring and the via. In the case of the structure of FIG. 2, it is necessary to change the design layout by shifting the center position of the via 10 and to change the etching time in the opening process of the interlayer insulating film 7 for the via 10 to form a deep opening. It is. However, film formation of the barrier metal (and Cu seed layer) by, for example, the PVD (Physical Vapor Deposition) method, followed by Cu embedding (damascene method) by, for example, electrolytic plating may be the same as the previous steps. . Therefore, there is almost no increase in manufacturing cost.
(3) Analysis of the configuration example of the present invention (Part 1: Comparison with the conventional example)
The effect of the present invention was clarified by stress analysis. 3 shows and compares the stress analysis results (extracting the upper and lower wirings and vias) of the conventional structure example as shown in FIG. 1 and the structure example of the present invention as shown in FIG. Is.

  The stress analysis here was performed using commercially available finite element analysis software (ANSYS 7.1). As analysis conditions, a stress-free state was calculated at a temperature of 200 ° C. to 250 ° C., and a stress state generated by thermal strain generated when the temperature was lowered to room temperature was calculated. This method is a general approximation method used for obtaining the stress remaining in the wiring or via. In this finite element analysis software (ANSYS 7.1), the stress state is displayed by color change, and the stress state in each color can be grasped in the bar at the bottom of each diagram of the result display diagram. Therefore, it is shown that the stress distribution is greatly changed at the portion where the color is greatly changed. However, in FIG. 3, the color copy of the calculation result is shown by monochrome printing.

  The left side of FIG. 3, FIGS. 1-A and 1-B are display examples of calculation results in the conventional structure example. In FIG. 1 (A), the lower quadrangular column shape is the lower layer wiring structure, the upper quadrangular column shape is the upper layer wiring structure, and the cylindrical shape arranged so as to connect the vias is the via. Represents the structure of In this case, the via cross-sectional diameter and the lower layer wiring width are the same, and the cross-sectional center line of the via and the center line in the width direction of the lower layer wiring are made to coincide. FIG. 1 (B) shows only the lower layer wiring extracted and displayed at this time in order to easily understand the influence of the lower layer wiring of interest on the corner portion.

  The right side of FIG. 3, FIGS. 2-A and 2-B are display examples of calculation results in the structural example of the present invention. In FIG. (2-A), as in FIG. (1-A), the lower quadrangular column shape connects the lower layer wiring structure, and the upper quadrangular column shape connects the upper layer wiring structure. A cylindrical shape arranged in FIG. 3 represents the via structure. Similarly, FIG. 2-B shows only the lower layer wiring extracted at this time. In FIG. 2A, the via cross-sectional diameter and the lower layer wiring width are the same. For the 140 nm diameter via, the cross-sectional center line is shifted by 40 nm with respect to the width center line of the lower layer wiring, and the lower end surface of the via Is an example of a structure 20 nm lower than the upper end surface of the lower layer wiring.

  In each of the structural examples, the wiring width is 140 nm for both the upper layer and the lower layer, the wiring height is 200 nm, the via is a complete cylindrical shape with a diameter of 140 nm, the height (inter-wiring length) is 200 nm, and the material is Cu. In the stress calculation, an insulating film (such as SiOC / SiC) and a substrate (such as Si / SiO2) between layers are considered, but are not shown here for the sake of easy understanding. In reality, there is a barrier metal (Ta / TaN) around Cu, but this thickness is very small compared to the volume of 10 nm and Cu, so the contribution to stress is not large. Not.

  Looking at (1-B) of FIG. 3, which is a conventional structure, it is found that there is a region (stress singular region) in which the stress distribution is changed specifically in the portion directly below the via in the upper end region of the lower layer wiring. This stress singularity region extends to the corner C of the wiring at the two ends. Compared with the void formation location in the experimental results of FIG. 1, it corresponds to this stress singularity region, and it can be seen that voids are easily formed in such a stress singularity region.

Looking at (2-B) in FIG. 3, which is an example of the structure of the present invention, the stress singularity region is found in the corner portion B at the upper end of one of the lower layer wirings, but the upper corner portion far from the cross-sectional center of the via. It is rarely found in A. In other words, the stress distribution in the corner portion A is not different from the stress distribution in the wiring portion without vias, so that the driving force that the voids are attracted locally and gathered (becomes a void) is generated at this location. It will not exist. Therefore, it can be easily analogized that the void occurrence probability of the semiconductor device of the present invention is about half that of the conventional structure.
(4) Analysis of an exemplary embodiment of the present invention (Part 2: Analysis of effect by deviation amount)
First, in the structure in which the via center line is shifted from the width center line of the lower layer wiring and the lower end portion of the via is formed deeper than the upper end portion of the lower layer wiring as shown in FIG. The change of stress distribution was analyzed. The stress distribution calculation method and the preconditions for the configuration are the same as those described in the previous section (3). From the calculation results, the stress distribution in part A in FIG. 3 (2-B), that is, the corner part of the lower layer wiring on the far side from the via center line, is extracted and shown in FIG.

  In FIG. 4, the horizontal axis is the distance in the longitudinal direction of the lower layer wiring, and 0 μm is the position where the position of the cross-sectional center line of the via is shifted to the wiring A section side corner. The vertical axis represents the stress value, and there are a case where the parameter is not deviated (conventional type) and a case of 5 to 40 nm (5 steps).

According to this figure, in the case of the conventional type, the stress is drastically reduced at the position of the via. This indicates that such stress change / concentration is the driving force for void formation. On the other hand, as the amount of deviation increases, the stress change / concentration near the via becomes less noticeable. From this figure, it can be said that when the amount of deviation exceeds about 14 nm, the stress distribution becomes almost flat. Since the calculation here does not depend on the scale of the calculation model, for example, even if the overall size is halved and the deviation amount is halved, the stress distribution of the calculation result is the same. Therefore, from this result, it can be said that it is reasonable to determine that the effect of the present invention is large and is approximately 1/10 or more of the via diameter.
(5) Example of the present invention and reliability test result A semiconductor device having a multilayer wiring structure according to the configuration of the present invention and a semiconductor device having a conventional multilayer wiring structure were prepared and subjected to a reliability test and compared.

  First, as in the above calculation model (see FIG. 2), the via has a structure shifted, and a part of the lower end of the via 10 extends below the upper end of the lower layer wiring 4, A device in contact with the side surface (via shift / stretched structure: referred to as “Example 1”) was prepared. The width of the lower layer wiring 4 and the diameter of the via 9 are both 140 nm, the height of the lower layer wiring 4 is 200 nm, the amount of deviation of the via 9 from the lower layer wiring 4 is 14 nm, and is 1/10 of the diameter of the via 9. The wiring metal is Cu, the barrier metals 3 and 9 are Ta / TaN, and the thickness is 10 nm. The interlayer insulating films 1 and 7 are SiOC films formed by CVD. The hard mask films 2 and 8 and the cap films 6 and 12 above the wiring are SiC films having a thickness of 50 nm. As the length of the lower layer wiring 4, a wiring in which wiring lengths of 5, 10, 20, 50, 100, and 200 μm were connected in series was used.

  Further, as shown in FIG. 5 (cross-sectional view perpendicular to the wiring longitudinal direction), the cross-sectional center line of the via 10 is shifted from the width center line of the lower layer wiring 4, but the lower end of the via 10 and the upper end of the lower layer wiring 4 are one. Then, a device having a structure in which the via 10 does not extend downward (via shift / non-stretched structure: referred to as “Example 2”) was produced. In addition, each component of each number attached | subjected in the figure in FIG. 5 shows the same component as the number attached | subjected in FIG. The advantage of this embodiment is that the etching process when creating the via shape can be performed under exactly the same conditions as in the conventional process. On the other hand, since the contact area between the via 10 and the lower layer wiring 4 is reduced, the resistance at the contact portion between them may be slightly increased (−10%). Other conditions such as the via shift amount and the wiring structure in the second embodiment are exactly the same as those in the first embodiment.

  In the second embodiment (see FIG. 5), since the cross-sectional center line of the via 10 is merely shifted from the width center line of the lower layer wiring 4, the via shape creation and via embedding processes are not different from the conventional ones. Since the contact area between the wiring 4 and the via 10 is narrowed, the resistance per via increases as the shift amount increases. To solve this problem, a method of enlarging the contact area by making the cross-sectional shape of the via an ellipse or a shape similar to the ellipse and making the long axis of the via cross-section parallel to the longitudinal direction of the lower layer wiring is conceivable.

  On the other hand, in Example 1 (see FIG. 2), one lower portion of the via 10 is made deeper than the upper portion of the lower layer wiring 4, so that an increase in resistance in connection with the via can be suppressed by contacting the side wall of the lower layer wiring 4. It has a structure. However, when the via 10 is deepened (further, the smaller the shift amount), there is a concern that the via metal filling is somewhat difficult depending on the shape. To solve this problem, the wiring width is made narrower than the wiring width at the other normal locations at the wiring side where the via 10 and the lower layer wiring 4 are in contact with each other. A method is conceivable in which the metal can be easily embedded in the via 10 by expanding the area.

  FIG. 6 shows an example in which the above two measures are taken simultaneously. Each component of each number given in the figure indicates the same component as the number given in FIG. FIG. 6A is a cross-sectional view perpendicular to the wiring longitudinal direction at that time. The width of the cross section of the lower layer wiring 4 connected to the via 10 is narrower than the width of the cross section of the adjacent lower layer wiring 5. FIG. 6B shows a cross-sectional view taken along line CD in the figure as viewed from the direction perpendicular to the substrate surface. The cross-sectional shape of the via 10 is an elliptical shape, and the center line is shifted by about 10 to 15% from the center line of the normal wiring width. The diameter of the via 10 in the lower-layer wiring width direction (length of the minor axis of the ellipse) is 140 nm, but the diameter of the via 10 in the longitudinal direction of the lower-layer wiring (length of the major axis of the ellipse) is 200 nm. Further, the width of the lower layer wiring 4 in contact with the via 10 is set to 100 nm, which is narrower than 140 nm which is the standard width (not in contact with the via 10). A device having such a structure (elliptical via shift / stretching / wiring narrowing structure: referred to as “Example 3”) was produced. The basic formation process of this device is the same as in the first and second embodiments.

  By adopting this structure, the connection resistance per via can be reduced by about 20% compared to Example 1 and by about 50% compared to Example 1. This contributes to improving the performance of the LSI chip, and in this case, it can be expected that the via filling conditions can be found relatively easily and contribute to cost reduction. In the third embodiment, the two methods of using the ellipse via and shifting from the wiring and the method of narrowing the wiring width of the connection portion with the via were used at the same time. As shown in the schematic wiring diagram of FIG. Simply connect the via 10 to the lower layer wiring 4 by making the section of the ellipse elliptical, or simply shift the via 10 having a circular section at the position of the wiring 4 having a narrow width, as shown in FIG. Of course, it is possible and effective to connect.

  A device having the structure of the conventional example is also created with the same wiring length in the same process, and a reliability test is performed on the devices of the first example, the second example, and the conventional example. The part detection rates were compared. The reliability test is performed at a temperature of 250 ° C., and an electromigration test is performed by flowing electricity in the wiring, or a stress migration test is performed by leaving it at a high temperature, and then a locally high resistance portion is measured by the OBIRCH method. And the abnormal part detection rate was calculated | required from the number of the high resistance location.

  FIG. 8 shows the reliability test results of the conventional example, Example 1, and Example 2. Note that Example 3 is not shown because it is almost the same as Example 1 and there was no significant difference. The horizontal axis represents the wiring length, and the vertical axis represents the abnormal part detection rate (arbitrary unit). FIG. 8 clearly shows that the wiring structure according to the present invention (Example 1 and Example 2) is more effective in improving the reliability than the conventional example. However, even with the structure of the conventional example, since there is almost no abnormality when the wiring length is 100 μm or less, the defect as a problem in the present invention is a long wiring length mainly exceeding 100 μm in this case. Therefore, when considering the ratio to the via diameter / wiring width (140 nm), 100 μm is equivalent to 714 times. Therefore, the defect targeted by the present invention is a wiring whose wiring length is about 700 times or more of the via diameter. Therefore, it can be understood that the wiring structure of the present invention is effective in the case of such a long wiring.

  In addition, although the detection rate of Example 2 is lower than that of the conventional example, the effect is lower than that of Example 1. In FIG. 5, although the void in the A portion can be suppressed, the occurrence of the void in the B portion is unavoidable. In this case, since the contact area between the lower wiring 4 and the via 10 is narrow, the void is generated at this location. This is thought to be due to a rapid increase in resistance.

In addition, the abnormal part detection rate shown in FIG. 8 is the ratio which detected the abnormal part by the OBIRCH method, and the void was not observed by TEM about all the abnormal parts. However, as a result of observing typical locations, all of the voids as shown in FIG. 1 and voids that grew sufficiently to cover the bottom of the via were found. The “abnormal part” is not necessarily a complete disconnection, and the majority indicates a part having a higher resistance than usual. In FIG. 8, a slight abnormal portion is detected when the wiring length of the conventional example is 50 μm, but this abnormal portion is generated in the middle of the wiring and is a high resistance portion that has existed from the initial stage of manufacturing. This is considered to be caused by a cause different from the location where an abnormality has occurred due to deterioration related to the present invention.
(6) Analysis of Embodiment Configuration Example of the Present Invention Using Vias Made of Materials Different from Wiring Using the same configuration example (see FIG. 2) as Example 1, the material of vias is different from the material of wiring (Cu). The case was further analyzed. The model used for the stress distribution calculation by the method as described above is a critical structure in which the stress concentration in the vicinity of the via is almost eliminated when the deviation between the via section center line and the lower layer wiring width center line is 14 nm. (Materials) were examined. As the via material, Cu (elastic constant: 128 GPa), Al (elastic constant: 70 GPa), and W (elastic constant: 362 GPa) are compared. Other components are the same as those in the first embodiment.

  Al and W are materials conventionally used as wiring and via materials for semiconductor devices, and are partially used in devices mainly composed of Cu wiring. These can be formed and embedded by sputtering, for example, and it is not so difficult to introduce into the process step practically. Of course, for example, in the case of a Cu alloy in which some additive element is added to Cu, the elastic constant changes greatly. Therefore, this study is performed in consideration of such a case.

  The results of stress analysis of these materials are shown in FIG. The vertical and horizontal axes in this figure are the same as those in FIG. 4, and the analysis part is also the same, that is, the wiring corner part on the side far from the shifted via (part A in FIG. 2B). It is. Cu is used as the material for the wiring. As shown in FIG. 4, in the case of the conventional example (in the case of “no deviation” in FIG. 4), a significant change in stress reduction was observed in the vicinity of the via center line, which was a cause of void formation. From the graph of FIG. 7, it can be seen that when Al vias are used compared to Cu vias, the stress decrease near the via center line is large, and in this case, voids are more easily formed. This means that in order to prevent void formation to the same extent as Cu, it is necessary to make the amount of shift larger than Cu.

  On the other hand, when W having the largest elastic constant is used, in this case, the stress tends to be rather large in the vicinity of the via, and it is considered that this material is the most effective material for suppressing voids.

From the above considerations, it can be considered that it is generally advantageous for the present invention to use a material having a larger elastic constant for the via material than for the wiring material. For example, when Al, Cu or an alloy material of these metals is used as a wiring material, it is effective to use W having a larger elastic constant as the via material. In any case, the present invention can be more effectively implemented by using a material of a via portion different from the wiring portion.
(7) Forming Example of Semiconductor Device of the Present Invention A forming example related to the structure example of the present invention shown in FIG. 2 is a diagram mainly showing a multilayer wiring portion in each forming step shown in FIG. This will be described with reference to a vertical sectional view.

  FIG. 10A is a cross-sectional view in which a low-k interlayer insulating film 103 and a hard mask film (SiC film) 104 for forming a lower wiring layer are formed in the first stage of the wiring process. Before the wiring process, there are a transistor and a contact process connected to the wiring, which are included in the Si substrate 101 and the SiO 2 layer 102, respectively, and are not shown in the drawing. In this embodiment, an SiOC film, which is a low-k film, is formed on the interlayer insulating film 103 at a substrate temperature of 400 ° C. using a CVD (Chemical Vapor Deposition) method. The SiC film 104 serving as a cap film is formed at a substrate temperature of 400 ° C. by plasma CVD. The thickness of the SiOC film after film formation is about 200 nm, and the thickness of the SiC film is about 50 nm.

  Thereafter, as shown in FIG. 10B, a lower wiring trench 105 having a width of 140 nm is formed through photolithography and an etching process. Then, as shown in FIG. 10 (3), after forming a barrier metal 106 and a seed Cu film, a Cu buried layer 107 was formed by electrolytic plating to bury Cu in the wiring trench. The barrier metal 106 used here is a film made of Ta or TaN and having a thickness of about 10 nm. Next, as shown in FIG. 10D, the buried layer Cu 107 and the barrier metal 106 remaining above the SiC film 104 are removed by a CMP (Chemical Mechanical Polishing) process (108), and the lower layer wiring 109 is formed. It is formed. During the CMP process, the SiC film 104 is used as a hard mask film.

  After the lower layer wiring 109 is formed in this way, the process proceeds to the via and upper layer wiring processes. First, as shown in FIG. 11 (5), an SiC film 110 is formed as a cap layer to be a Cu diffusion prevention film, and then a low-k interlayer insulating film 111 and an SiC film 112 as a Cu diffusion prevention film are formed. . The thickness of the SiC film 110 is about 50 nm, the thickness of the interlayer insulating film 111 is about 550 nm, and the thickness of the SiC 112 film thereon is about 50 nm.

  Then, as shown in FIG. 11 (6), vias and an upper layer wiring trench 113 are formed again through photolithography and etching processes. At this time, the groove 113 is formed by slightly shifting the cross-sectional center of the via from the width center line of the lower layer wiring. The via groove has a diameter of 140 nm and a depth of about 330 nm. As shown in the drawing, a part of the via groove is formed so that a part of one side surface of the lower layer wiring 109 is exposed. Further, the width of the groove for the upper layer wiring is 140 nm.

  Thereafter, FIG. 11 (7), which is a film forming process of the barrier metal and Cu, is similar to the previous FIG. 10 (3), and after depositing the barrier metal 114 and the seed Cu film, the Cu buried layer 115 is replaced with the via and the upper layer. It is embedded in the wiring groove 113. Further, the process of removing the extra Cu and SiC film 112 by CMP (116) and forming the via 117 and the upper wiring 118 shown in FIG. 11 (8) is the same as the process of FIG. 10 (4). It is.

  Then, as shown in FIG. 12 (9), after forming the SiC film 119 as a cap film, the low-k interlayer insulating film 120 is formed, and the cross-sectional center line of the via 117 is the width center of the lower layer wiring 109. A semiconductor device of the present invention having a structure deviated from the line was formed.

  As described above, the manufacturing process of the present invention is almost the same as the conventional manufacturing process. The difference is that the location of the via groove is shifted in the step of FIG. 11 (6), and the etching time is slightly increased accordingly, so that the groove is formed deeper than the upper end of the lower layer wiring 109. It is. Therefore, a highly reliable semiconductor device can be created without greatly changing the conventional multilayer wiring process.

The following supplementary notes are further disclosed with respect to the embodiments including the above examples.
(Appendix 1) Two or more wiring layers formed on a semiconductor substrate;
A via for electrically connecting an upper layer wiring and a lower layer wiring formed in different wiring layers in the two or more wiring layers;
When viewed from the vertical direction of the semiconductor substrate surface, the cross-sectional diameter of the via is the same as the wiring width in the wiring width direction diameter of the lower layer wiring and the same as the wiring width in the longitudinal direction diameter of the lower layer wiring. A semiconductor device characterized in that it is long and the center line of the cross-sectional diameter of the via and the center line of the wiring width of the lower layer wiring are shifted from each other.
(Supplementary note 2) The supplementary note 1 is characterized in that the deviation amount between the center line of the cross-sectional diameter of the via and the center line of the wiring width of the lower layer wiring is about 10% or more of the cross-sectional diameter of the via. The semiconductor device described.
(Additional remark 3) The length of the said lower layer wiring is about 700 times or more of the cross-sectional diameter of a previous period via | veer, The semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the via has a contact surface on one side surface in a rectangular cross section of the lower layer wiring.
(Supplementary note 5) The semiconductor device according to supplementary note 4, wherein a wiring width of the lower layer wiring at a position where the via contacts the lower layer wiring is narrower than a main wiring width of the lower layer wiring.
(Appendix 6) The contact area of the contact surface is increased at a rate equal to or greater than the rate of deviation between the center line of the cross-sectional diameter of the via and the center line of the wiring width of the lower layer wiring. 6. The semiconductor device according to any one of appendices 4 to 5, wherein the semiconductor device is provided.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein an elastic constant of a via metal material used for the via is equal to or greater than an elastic constant of a lower layer metal material used for the lower layer wiring. .
(Appendix 8) The lower wiring metal material is Al or an alloy material mainly composed of Al or an alloy material mainly composed of Cu or Cu, and the via metal material is an alloy material mainly composed of Al or Cu or Cu. 8. The semiconductor device according to appendix 7, wherein the semiconductor device is an alloy material mainly composed of or W.
(Additional remark 9) The process of forming a 1st wiring in the 1st wiring layer on a semiconductor substrate,
Forming an insulating layer on the first wiring;
When the opening is formed in the insulating layer and viewed from the direction perpendicular to the semiconductor substrate surface, the cross-sectional diameter is the same as the wiring width in the wiring width direction diameter of the first wiring, and the length of the first wiring The first wiring and the electrical power having the same or longer than the wiring width in the direction diameter, and the center line of the cross-sectional diameter and the center line of the wiring width of the first wiring are shifted from each other Forming electrically connected vias;
Forming a second wiring electrically connected to the via in a second wiring layer on the via.

Schematic diagram of TEM image of abnormal part Schematic cross-sectional view of an embodiment of the invention Figure showing the results of stress analysis Diagram showing changes in stress distribution when via displacement is changed Cross-sectional schematic diagram of the wiring and via structure used in Example 2 Cross-sectional schematic diagram of wiring / via structure used in Example 3 Diagram showing examples of combinations of wiring shape and via shape Figure showing reliability test results Diagram showing changes in stress distribution when via metal material is changed Cross-sectional schematic diagram showing the production process of the present invention (1) Cross-sectional schematic diagram showing the production process of the present invention (2) Cross-sectional schematic diagram showing the production process of the present invention (3)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 7 Interlayer insulating film 2, 8 Hard mask film 3, 9 Barrier metal 4 Lower layer wiring 5 Adjacent lower layer wiring 6, 12 Cap film 10 Via 11 Upper layer wiring 101 Si substrate 102 SiO2 layer 103 Interlayer insulating film 104 SiC film 105 Lower layer wiring Groove 106 Barrier metal 107 Cu buried layer 108 State after CMP process 109 Lower layer wiring 110 SiC film 111 Interlayer insulating film 112 SiC film 113 Via and upper layer wiring groove 114 Barrier metal 115 Cu buried layer 116 State after CMP process 117 Via 118 Upper layer wiring 119 SiC film 120 Interlayer insulating film

Claims (5)

Two or more wiring layers formed on a semiconductor substrate;
A via for electrically connecting an upper layer wiring and a lower layer wiring formed in different wiring layers in the two or more wiring layers;
When viewed from the vertical direction of the semiconductor substrate surface, the cross-sectional diameter of the via is the same as the wiring width in the wiring width direction diameter of the lower layer wiring and the same as the wiring width in the longitudinal direction diameter of the lower layer wiring. A semiconductor device characterized in that it is long and the center line of the cross-sectional diameter of the via and the center line of the wiring width of the lower layer wiring are shifted from each other.   2. The semiconductor according to claim 1, wherein a deviation amount between a center line of a cross-sectional diameter of the via and a center line of a wiring width of the lower layer wiring is about 10% or more of a cross-sectional diameter of the via. apparatus.   The semiconductor device according to claim 1, wherein the via has a contact surface on one side surface in a rectangular cross section of the lower layer wiring.   4. The semiconductor device according to claim 1, wherein an elastic constant of a via metal material used for the via is equal to or greater than an elastic constant of a lower layer metal material used for the lower layer wiring. Forming a first wiring in a first wiring layer on a semiconductor substrate;
Forming an insulating layer on the first wiring;
When the opening is formed in the insulating layer and viewed from the direction perpendicular to the semiconductor substrate surface, the cross-sectional diameter is the same as the wiring width in the wiring width direction diameter of the first wiring, and the length of the first wiring The first wiring and the electrical power having the same or longer than the wiring width in the direction diameter, and the center line of the cross-sectional diameter and the center line of the wiring width of the first wiring are shifted from each other Forming electrically connected vias;
Forming a second wiring electrically connected to the via in a second wiring layer on the via.

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