JP2006164355A - Counter device and counting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce device load and to increase reliability of a counted value without increasing memory capacity and cost. <P>SOLUTION: "1" is beforehand written into all bits in a low-order counter 2a and counting is conducted from bit OFF (1→0). by making the bit to OFF from ON, "256" are counted by 32 bytes without sector erase. When all bits become "0", all bits are reset to "1" and the above counting operation is repeated. When all bits of the low-order counter 2a are reset to "1" from "0", a high-order counter 2b for carry is incremented for one at a time from the low-order bit in the above counting operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a counter device and a counting method using a nonvolatile memory.

  Printers and copiers manage many counters in a non-volatile memory (flash memory: registered trademark). The counter counts the number of printed sheets and is also used for billing purposes, so high reliability is required. By the way, the reliability of the nonvolatile memory becomes lower as the bit is used more frequently. Therefore, the manufacturer sets the guaranteed number of times of writing, and if the number is exceeded, the reliability of the nonvolatile memory is remarkably lowered (not guaranteed by the manufacturer).

  Due to the device characteristics of the nonvolatile memory, the counter value cannot be overwritten at the same location on the nonvolatile memory every time the counter is updated. In other words, in the nonvolatile memory, the storage area is divided in units called sectors, and in order to turn ON the bits that are OFF when updating data, all the data in the sector is once turned ON (0xff). It is necessary to write new data after performing sector erasure.

  Generally, as a counter, as shown in FIG. 4, “0” is written in advance to all bits, and when counting, the lower bits are counted up bit by bit. As described above, in the non-volatile memory, in order to turn on a bit that is turned off, it is necessary to perform sector erasing that once sets all data in the sector to bit ON (0xff). Therefore, in this case, as shown in FIG. 5, every time the counter value is updated, sector erasure is performed, and writing for the number of bits of the counter occurs. For this reason, as described above, the reliability of the nonvolatile memory is rapidly lowered. In order to increase the reliability of the counter value, it is desirable that the number of rewrites is small.

Thus, several techniques for reducing the number of sector erasures at the time of updating the counter value have been proposed (see, for example, Patent Document 1 and Patent Document 2). In this prior art, as shown in FIG. 6, “1” is written in advance to all bits of the counter, and counting is performed by bit OFF (1 → 0). By turning the bit from ON to OFF, the number of bytes of the counter can be counted without sector erasure.
JP 2001-118391 A JP-A-11-110983

  However, in the above-described prior art, the number of bits is equal to the maximum counter value, so the number of bits corresponding to the maximum count value is required. For example, when counting hundreds of thousands of units, hundreds of thousands of bits are required, and in consideration of memory capacity and cost, there is a problem that mounting becomes difficult in practice.

  The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide a counter capable of reducing the device burden and increasing the reliability of the counter value without increasing the memory capacity and increasing the cost. It is to provide an apparatus and a counting method.

  In order to solve the above-described problems, the present invention requires sector erasing to make all data in a sector high once before changing low data to high data in each bit. In a counter device comprising a rewritable counter comprising a non-volatile memory and a control unit for controlling data writing and data reading of the counter, the counter comprises a first number of bits and counts a first count value And a lower counter comprising a second number of bits and counting a second count value, and the control unit changes the bit of the lower counter by changing the bit from high to low in 1-bit units. 1 count value is updated, and each time the first count value of the lower counter makes a round, the upper counter And updates the second count value.

  Also, the present invention is characterized in that, in the above invention, the control unit resets all the bits of the lower counter to high when all the bits of the lower counter are turned off.

  In addition, in order to solve the above-described problems, the present invention requires sector erasure to temporarily change all data in a sector to high data before changing low data to high data in each bit. In the counting method for controlling data writing and data reading of a rewritable counter consisting of a non-volatile memory, the counter is composed of a first counter and a lower counter that counts a first count value; The upper counter that counts the second count value, and updates the first count value of the lower counter by changing the bit from high to low in 1-bit units. The second count value of the upper counter is updated every time the first count value by the counter makes a round. To.

  Further, the present invention is characterized in that, in the above invention, when all the bits of the lower counter are turned off, all the bits of the lower counter are reset to high.

  According to the present invention, the control unit updates the first count value of the lower counter by changing the bit from high to low in units of 1 bit, and each time the first count value of the lower counter makes a round. The second count value of the upper counter is updated. Therefore, there is an advantage that the device burden can be reduced and the reliability of the counter value can be increased without increasing the memory capacity and increasing the cost.

  According to the present invention, when all the bits of the lower counter are turned off by the control unit, all the bits of the lower counter are reset to high. Therefore, it is possible to count the guaranteed number of times of writing in the flash memory with a small memory capacity, and there is an advantage that the device burden can be reduced and the reliability of the counter value can be increased without increasing the cost.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a counter device according to an embodiment of the present invention. The flash memory 1 is a nonvolatile memory and has a counter 2. The counter 2 is composed of a predetermined number of bits and counts the cumulative number of rewrites. The control unit 3 controls data writing and data reading of the counter 2. Similarly to the conventional counter, the counter 2 has a low-order counter 2a that counts by turning a bit on (1) to off (0) in 1-bit units, and the number of resets every time the low-order counter 2a is reset Is comprised of a high-order counter 2b that counts by a general counting method (see FIG. 4). In the following, in order to simplify the description, the lower counter 2a is 32 bytes (1 byte = 8 bits, all 256 bits), and the upper counter 2b is 1 byte (8 bits). However, the number of bits is not limited to this, and a necessary number of bits may be secured according to the maximum count value.

  Next, FIG. 2 is a conceptual diagram for explaining the operation of the counter device. In the present embodiment, as in the conventional counters disclosed in Patent Documents 1 and 2, the lower counter 2a writes “1” in all bits in advance, and counts by bit OFF (1 → 0). By turning the bit from ON to OFF, it is possible to count “256” in 32 bytes without sector erasure. When all the bits become “0”, all the bits are reset to “1” again, and the above counting operation is repeated. In the counting operation, when all the bits of the lower counter 2a are reset from “0” to “1”, the upper counter 2b is incremented one by one from the lower bits, and the number of resets is counted. Therefore, the counter 2 can count 2 ^ 8 × 256 = 65536.

  FIG. 3 is a conceptual diagram showing the frequency of sector erasure in the counter device according to the present embodiment. As described above, in the flash memory 1, sector erasure occurs when the bit is changed from OFF to ON (0 → 1). That is, in this embodiment, as shown in FIG. 3, sector erasure occurs every time the lower counter 2a is reset, that is, once every 256 times (thick frame portion). In this embodiment, since the number of bits of the lower counter 2a is n and the number of bits of the upper counter 2b is m, it is possible to count only 2 ^ m × n because the counting is not performed in units of bits. Therefore, it is possible to count the number of guaranteed writes in the flash memory with a small memory capacity.

  According to the present embodiment, it is possible to reduce the device burden and increase the reliability of the counter value without increasing the memory capacity and increasing the cost. That is, a simple software change can reduce the device burden to half and increase the reliability of the counter value.

  In the above-described embodiment, the control unit 3 is executed in the computer system. A series of processing steps by the control unit 3 described above is stored in a computer-readable recording medium in the form of a program, and the above-described processing is performed by the computer reading and executing the program. That is, each processing means and processing unit in the control unit 3 is such that a central processing unit such as a CPU reads the above program into a main storage device such as a ROM or RAM, and executes information processing / calculation processing. It is realized.

  Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

It is a block diagram which shows the counter apparatus by embodiment of this invention. It is a conceptual diagram for demonstrating operation | movement of the counter apparatus by this embodiment. It is a conceptual diagram which shows the generation frequency of the sector erase in the counter apparatus by this embodiment. It is a conceptual diagram for demonstrating operation | movement of the conventional general counter. It is a conceptual diagram which shows the occurrence frequency of the sector erase in the conventional general counter. It is a conceptual diagram for demonstrating the operation | movement of the counter which reduced the conventional sector erase generation frequency.

Explanation of symbols

1 Flash memory (nonvolatile memory)
2 Counter 2a Lower Counter 2b Upper Counter 3 Control Unit

Claims (4)

Prior to changing low data to high data in each bit, a rewritable counter comprising a non-volatile memory that requires sector erasure to make all the data in the sector once high data, and the counter In a counter device comprising a control unit that controls data writing and data reading of
The counter is composed of a first number of bits, and is composed of a lower counter that counts the first count value and a second counter that is composed of the second number of bits and counts the second count value,
The control unit updates the first count value of the lower counter by changing the bit from high to low in units of one bit, and the upper counter every time the first count value by the lower counter makes a round And updating the second count value.   2. The counter apparatus according to claim 1, wherein the control unit resets all the bits of the lower counter to high when all the bits of the lower counter are turned off. Prior to changing the low data to the high data in each bit, once the data in the rewritable counter consisting of a non-volatile memory that requires sector erasure to make all the data in the sector high data and In a counting method for controlling data reading,
The counter is composed of a first number of bits and is composed of a lower counter that counts the first count value and a higher order counter that is composed of the second number of bits and counts the second count value. The first count value of the lower counter is updated by changing the bit from high to low at, and the second count value of the upper counter is updated each time the first count value of the lower counter makes a round. A counting method characterized by: 4. The counting method according to claim 3, wherein when all the bits of the lower counter are turned off, all the bits of the lower counter are reset to high.

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