JP2006163674A - Image processing device, printer, and load distribution method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To appropriately perform load distribution of a plurality of processing sections from the beginning of the processing, and to appropriately perform the load distribution even when there are three or more processing sections. <P>SOLUTION: This image processing device comprises CPUs 12-18 as a plurality of processing sections for sequentially applying a plurality of types of image processing to image data in the same region, a load distribution table 51 having distribution percentage of each type of image processing to one or more processing sections and having a default distribution percentage as an initial value, a CPU 12 as a distribution percentage updating means for calculating the distribution percentage of each image processing after the start of the image processing and updating the load distribution table 51, and CPUs 12-14 as start processing means for distributing each of at least one type of image processing into two or more processing sections and executing it using the default distribution percentage for the distribution percentage that has not been yet updated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an image processing apparatus, a printing apparatus, and a load distribution method in these apparatuses that sequentially perform a plurality of types of image processing on image data in the same region.

Conventionally, a printing apparatus having two CPUs has been proposed (see, for example, Patent Document 1). For example, in the printing apparatus of Patent Document 1, a first control section having a first CPU controls a process of converting print data into intermediate-stage data, and a second control section having a second CPU is Controls the process of converting intermediate-stage data into bitmap data that can be output to the printing mechanism.

In this printing apparatus, the first control section and the second control section have a function capable of executing processing to be executed by the second control section and the first control section. When one of the first control section and the second control section becomes overloaded, a part of the process is moved to the other.

JP 2003-251867 A (summary etc.)

However, in the above-described conventional printing apparatus, after one control section is overloaded,
Since a part of the process is moved from the one control partition to the other control partition, there is a possibility that load distribution is not appropriately performed from the beginning of the processing. In addition, since there are only two control sections in the above-described conventional printing apparatus, a part of the process can be moved from one to the other as described above, but the number of control sections (processing units) is three or more. In some cases, multiple control sections (processing units)
Therefore, it is difficult to apply the load distribution method in the above-described conventional printing apparatus as it is when the number of processing units is 3 or more.

The present invention can appropriately perform load distribution from the beginning of processing to a plurality of processing units, and can perform load distribution appropriately even if the number of processing units is three or more. And to obtain a load balancing method.

  In order to solve the above problems, the present invention is configured as follows.

An image processing apparatus according to the present invention has a plurality of processing units that sequentially perform a plurality of types of image processing on image data in the same region, and a distribution ratio to one or a plurality of processing units related to various types of image processing. Load distribution table, distribution ratio update means that calculates the distribution ratio of each image processing after image processing starts and updates the distribution ratio in the load distribution table, and distribution ratio that has never been updated by the distribution ratio update means And a start processing unit that distributes the image processing to two or more processing units and executes the image processing for at least one type of image processing.

Thereby, load distribution can be appropriately performed from the beginning of processing to a plurality of processing units,
Furthermore, even when there are three or more processing units, load distribution can be performed appropriately.

In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. That is, in this case, the image processing apparatus further includes a processing capability table that stores the processing capability values of the plurality of processing units, and a default processing capability that stores default values of the processing capability values of the plurality of processing units. A table and processing capacity table updating means for updating the processing capacity value of the processing capacity table based on a processing time for a predetermined amount of image data by each of the plurality of processing units. Then, the distribution ratio update means refers to the processing capacity table preferentially, calculates the distribution ratio of each image processing based on the processing capacity table and the default processing capacity table, and sets it in the load distribution table.

As a result, it is possible to perform load distribution appropriately for the plurality of processing units from the beginning of the processing and dynamically corresponding to the load that fluctuates according to the contents of the image data, and the number of processing units is three or more. However, load distribution can be performed appropriately.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. That is, in this case, the processing capability table update unit is realized by executing a program by the processing unit, and updates the processing capability value based on the processing time and the number of processing pixels for each line or one band.

As a result, the processing capability value at the time of processing the actual image data is acquired and reflected in the distribution ratio. Therefore, an accurate load corresponding to the calculation amount for each type of image processing for each image data is obtained. Dispersion is possible.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. That is, in this case, the processing capability table has a processing capability value for each of a plurality of types of image processing for each of a plurality of processing units.

As a result, for example, even when the processing unit is optimized only for a predetermined type of image processing, an accurate processing capability value can be obtained, and thus accurate load distribution can be performed.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. That is, in this case, after setting the distribution ratio, the distribution ratio update unit completes the image processing of the type with the slowest processing time for one line or one band among the plurality of types.
The dispersion ratio is set again.

As a result, since the distribution ratio is set after all the processing units have performed processing for at least one line or one band, it is possible to set an appropriate distribution ratio that reflects the processing capability value at each time point. .

A printing apparatus according to the present invention includes any one of the image processing apparatuses that execute at least color conversion and halftone as a plurality of processes, and a printing unit that prints an image based on image data processed by the image processing apparatus. Prepare.

As a result, it is possible to perform load distribution appropriately for the plurality of processing units from the beginning of the processing and dynamically corresponding to the load that fluctuates according to the contents of the image data, and the number of processing units is three or more. However, load distribution can be performed appropriately. As a result, the printing process can be executed at high speed.

The load distribution method according to the present invention provides a load distribution table having a distribution ratio for each processing type of image processing to a plurality of processing units that sequentially perform a plurality of types of image processing on image data in the same region. The step of updating with the distribution ratio of each image processing calculated after the start of processing, and the default distribution ratio for the distribution ratio that has never been updated in the load distribution table, for at least one type of image processing, The image processing is distributed to two or more processing units and executed respectively.

Thereby, load distribution can be appropriately performed from the beginning of processing to a plurality of processing units,
Furthermore, even when there are three or more processing units, load distribution can be performed appropriately.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. An image processing apparatus according to Embodiment 1 of the present invention is built in a printing apparatus and is JPEG (Joint Phot
ographic Experts Group) A device that performs a series of image processing on image data such as image data before printing.

In FIG. 1, an ASIC 1 is a multi-CPU (Central Proc) composed of one chip.
essing Unit) processor. The ASIC 1 incorporates eight CPUs 11 to 18,
The CPU 11 controls the printer drive unit 4 and seven CPUs 12 to 18 execute a series of image processing including JPEG decoding, image correction, color conversion, and halftone. In the first embodiment, a plurality of different processes such as JPEG decoding, image correction, color conversion, and halftone are sequentially performed on the image data, and pipeline processing is performed in the order of JPEG decoding, image correction, color conversion, and halftone. Is executed.

In addition, one or more processes among JPEG decoding, image correction, color conversion, and halftone are distributed by a plurality of CPUs of the CPUs 12 to 18 according to the load balance of the CPUs 12 to 18.

An external RAM (Random Access Memory) 2 is connected to each C of the ASIC 1 via the bus 20.
This is a semiconductor memory connected to the PUs 11 to 18. In the first embodiment, the external RAM 2
Is a DDR-SDRAM, and 20 to 30 clocks are required to read / write one word.

The memory card 3 is a storage medium that is detachable from the apparatus and has a non-volatile semiconductor memory that stores a JPEG file including JPEG-encoded image data. The memory card 3 is connected to the bus 20 via an interface circuit (not shown).

The printer drive unit 4 is an electrical and mechanical component necessary for printing on a medium such as paper, such as a printer head and various motors. The printer driver 4 is connected to the bus 20 via an interface circuit (not shown). The printer drive unit 4 functions as a printing unit that prints an image based on image data processed by the image processing apparatus.

In the ASIC 1 shown in FIG. 1, the CPU 11 executes a drive control program 45 (see FIG. 3).
CP for controlling the printer drive unit 4 based on the image data after a series of image processing
U.

The CPU 12 has a JPEG decoding dedicated instruction calculation unit 12b capable of executing a dedicated instruction for JPEG decoding in addition to a general purpose instruction calculation unit 12a capable of executing general instructions common to the CPUs 12 to 18. A CPU that executes JPEG decoding.

The dedicated instruction for JPEG decoding is a collection of a series of operations frequently used during JPEG decoding into one instruction. The JPEG decoding dedicated instruction operation unit 12b performs the series of operations corresponding to the dedicated instruction. The arithmetic unit configuration can be executed with a smaller number of clocks than the general-purpose instruction arithmetic unit 12a. Note that the number of such dedicated instructions is not limited to one, but is defined at the time of design as necessary. That is, it can be said that the JPEG decode dedicated instruction calculation unit 12b is dedicated hardware for speeding up JPEG decoding, which operates corresponding to one or more dedicated instructions.

In addition to the general-purpose command calculation unit 13a capable of executing a general-purpose command common to the CPUs 12 to 18, the CPU 13 includes an image correction dedicated command calculation unit 13b capable of executing a dedicated command for image correction.
And a CPU that mainly performs image correction. As image correction, one or more of a first process for tone adjustment and saturation emphasis, a second process for sharpness (adjustment of sharpness), and a third process for noise removal are necessary. Done. Each process may be performed in the same way as APF (Auto Photo Fine) provided by the applicant, for example.

The dedicated instruction for image correction is a series of operations frequently used during image correction processing, and is integrated into one instruction. The image correction dedicated instruction calculation unit 13b corresponds to the dedicated instruction and the series of operations. Has a computing unit configuration that can be executed with a smaller number of clocks than the general-purpose instruction computing unit 13a. Note that the number of such dedicated instructions is not limited to one, but is defined at the time of design as necessary.
That is, the image correction dedicated instruction calculation unit 13b can be said to be dedicated hardware for speeding up image correction that operates in response to one or more dedicated instructions.

Further, the CPU 14 includes a color conversion dedicated command calculation unit 14b capable of executing a color conversion dedicated command in addition to a general command calculation unit 14a capable of executing a general command common to the CPUs 12 to 18. The CPU executes color conversion. In the first embodiment, conversion from RGB data to CYMK data is performed as color conversion.

The dedicated instruction for color conversion is a series of operations frequently used during color conversion processing, and is integrated into one instruction, and the dedicated instruction for color conversion operation unit 14b corresponds to the dedicated instruction and performs the series of operations. Has a computing unit configuration that can be executed with a smaller number of clocks than the general-purpose instruction computing unit 14a. Note that the number of such dedicated instructions is not limited to one, but is defined at the time of design as necessary. That is, it can be said that the color conversion dedicated instruction calculation unit 14b is dedicated hardware for speeding up color conversion that operates in response to one or more dedicated instructions.

Further, the CPU 15 has a halftone dedicated instruction calculation unit 15b capable of executing a dedicated instruction for halftone in addition to the general purpose command calculation unit 15a capable of executing a general purpose command common to the CPUs 12 to 18. It is a CPU that executes halftone. CPU16 to CPU18
Respectively have the same configuration as the CPU 15, and general-purpose instruction arithmetic units 16a, 17a, 18a.
And halftone dedicated instruction calculation units 16b, 17b, and 18b.

The four CPUs 15 to 18 are a CPU group that executes halftones in parallel. Further, at the time of halftone dispersion processing, the other CPUs (CPUs 12 to 14) are used together with the CPUs 15 to 18.

The dedicated instruction for halftone is a series of operations that are frequently used during halftoning, and is integrated into one instruction. The dedicated instruction calculation units 15b to 18b for halftone correspond to the dedicated instruction and the series of operations. It has a computing unit configuration that can perform computations with a smaller number of clocks than the general-purpose command computation units 15a to 18a. Note that the number of such dedicated instructions is not limited to one, but is defined at the time of design as necessary. That is, it can be said that the halftone dedicated instruction calculation units 15b to 18b are dedicated hardware for increasing the halftone speed, which operates corresponding to one or more dedicated instructions.

In the first embodiment, the CPU 1 having the halftone dedicated instruction calculation units 15b to 18b.
Although four of 5 to 18 are provided, the number of CPUs having the halftone dedicated instruction calculation units 15b to 18b may be different. The number may be determined according to the number of colors after color conversion.

The local bus 19 is connected to the CPUs 11 to 18 and the dual port RA in the ASIC 1.
A bus connecting M21 and M22, and a data transmission path between them. A bus 20 connects the CPUs 11 to 18 to the external RAM 2, the printer driving unit 4, and the memory card 3, and is a data transmission path between them. The local bus 19a and the bus 20 are, for example, 128-bit data buses.

The dual port RAMs 21 and 22 are built in the ASIC 1 and have two input / output ports.
The RAM is capable of independently executing read / write to one port and the other port. The dual port RAMs 21 and 22 are composed of static RAM (SRAM).
It is possible to read / write data faster than the external RAM 2. The storage capacity of the dual port RAMs 21 and 22 is several to several tens of kilobytes, which is smaller than the storage area of the external RAM 2.

One port of the dual port RAMs 21 and 22 is connected to the local bus 19, and the other port is directly connected to the CPU 12 and the CPU 14, respectively.

FIG. 2 is a block diagram showing a detailed configuration of the CPU 12 in FIG. In FIG. 2, an instruction management unit 31 manages input / output of instructions during program execution. The instruction cache 32 is a high-speed RAM such as an SRAM that temporarily stores fetched instructions and post-execution instructions. The instruction RAM 33 is an instruction storage internal RAM built in the CPU 12. The instruction RAM 33 is a high-speed memory composed of SRAM, and other C
This memory cannot be accessed from the PU.

The data management unit 34 manages data input / output during program execution. The data cache 35 is an SRA that temporarily stores loaded data and operation results.
It is a high-speed RAM such as M. The data RAM 36 is an internal RAM for data storage built in the CPU 12. The data RAM 36 is a high-speed memory composed of SRAM and cannot be accessed from other CPUs.

The memory interface 37 is an interface for executing data input / output with a memory provided in the CPU 12. The memory interface 37 is directly connected to the dual port RAM 21 and is connected to the dual port RA via the local bus 19.
Connected to M22. The external interface 38 is connected to the bus 20 and other external devices, and peripheral devices (external RAM 2 and the like) outside the ASIC 1 are connected via the bus 20.
It is an interface that executes data input / output with.

Although the CPU 12 has been described here as an example, the CPUs 13 to 18 are the same as those in FIG. 2 except that the dedicated instruction calculation unit is different as shown in FIG. However, the memory interface 37 is connected to the local bus 19 and the dual port RAM 22 in the CPU 14, but is connected to the local bus 19 in the other CPUs 13 and 15 to 18.

The data management unit 34 can read / write data from / to the dual port RAMs 21 and 22 connected to the memory interface 37 via the local bus 19. In this case, the read / write to the dual port RAMs 21 and 22 can be executed faster than the read / write to the external RAM 2. When the CPUs 11 to 18 read / write to the dual port RAM 21, the CPU 12 reads / writes to one port without going through the local bus 19, and the other CPUs 11, 13 to 18 1
The other port is read / written via 9. Similarly, when the CPUs 11 to 18 read / write the dual port RAM 22, the CPU 14 reads / writes to one port without going through the local bus 19, and the other CPUs 11 to 1.
3 and 15 to 18 read / write to the other port via the local bus 19.

FIG. 3 is a block diagram showing a program executed by the CPUs 11 to 18 in FIG. The programs 41s to 44s, 41g to 44g, and 45 shown in FIG.
The external memory 2 is loaded from a nonvolatile memory (not shown) connected to 0.

In FIG. 3, a JPEG decoding program 41s is a program for the CPU 12 to decode JPEG image data. JPEG decoding program 41s
This is a program described using a dedicated instruction for EG decoding. Therefore, JPE
In the G decode program 41s, the dedicated instruction is executed by the dedicated instruction calculation unit 12b, and the other general-purpose instructions are executed by the general-purpose instruction calculation unit 12a. Therefore, CP in ASIC1
It is not executed by a CPU other than U12.

On the other hand, the JPEG decoding program 41g is a program for the CPUs 13 to 18 to decode JPEG image data. The JPEG decoding program 41g is a program described only with general-purpose instructions. Therefore, JPEG decoding program 41g
Are executed by the general-purpose instruction calculation units 13a to 18a.

The JPEG decode program 41s and the JPEG decode program 41g partially use different instructions. However, for the same data, the calculation result by the JPEG decode program 41s and the calculation result by the JPEG decode program 41g are the same. Become.

The image correction program 42s is a program for the CPU 13 to execute image correction. The image correction program 42s is a program described using a dedicated instruction for image correction. Therefore, in the image correction program 42s, the dedicated instruction is executed by the dedicated instruction calculation unit 13b, and the other general-purpose instructions are executed by the general-purpose instruction calculation unit 13a. For this reason, this program 42 s is not executed by a CPU other than the CPU 13 in the ASIC 1.

On the other hand, the image correction program 42g is a program for the CPUs 12, 14 to 18 to perform image correction. The image correction program 42g is a program described only with general-purpose instructions. Therefore, the image correction program 42g is used for the general-purpose command calculation units 12a and 14a.
Executed at ~ 18a.

The image correction program 42s and the image correction program 42g partially use different commands, but the calculation result by the image correction program 42s and the calculation result by the image correction program 42g are the same for the same data. Become.

The color conversion program 43s is a program for the CPU 14 to perform color conversion. The color conversion program 43s is a program described using a dedicated instruction for color conversion. Accordingly, in the color conversion program 43 s, the dedicated instruction is the dedicated instruction calculation unit 14.
The other general-purpose instructions executed by b are executed by the general-purpose instruction calculation unit 14a. For this reason, A
The CPU 43 other than the CPU 14 in the SIC 1 does not execute this program 43s.

On the other hand, the color conversion program 43g is a program for the CPUs 12, 13, 15 to 18 to perform color conversion. The color conversion program 43g is a program described only with general-purpose instructions. Therefore, the color conversion program 43g is stored in the general-purpose instruction calculation units 12a, 13a,
It is executed at 15a to 18a.

The color conversion program 43s and the color conversion program 43g use partially different instructions, but the calculation result by the color conversion program 43s and the calculation result by the color conversion program 43g are the same for the same data. Become.

The halftone program 44s is a program for the CPUs 15 to 18 to execute halftone. The halftone program 44s is a program described using a dedicated instruction for halftone. Accordingly, in the halftone program 44s, dedicated instructions are executed by the dedicated instruction calculation units 15b to 18b, and other general-purpose instructions are executed by the general-purpose instruction calculation units 15a to 18a. For this reason, CPU15-18 in ASIC1
In other CPUs, the program 44s is not executed.

On the other hand, the halftone program 44g is a program for the CPUs 12 to 14 to execute halftone. The halftone program 44g is a program described only with general-purpose instructions. Therefore, the halftone program 44g is stored in the general-purpose instruction calculation unit 12.
a to 14a.

The halftone program 44s and the halftone program 44g use partially different instructions, but the calculation result by the halftone program 44s and the calculation result by the halftone program 44g are the same for the same data. Become.

The drive control program 45 is a program for the CPU 11 to control the printer drive unit 4.

Of the above-mentioned programs, the programs 41s to 44s including dedicated instructions are coded optimized for each CPU by using dedicated instructions and using the instruction RAM 33 and data RAM 36 built in the CPU as much as possible. ing. On the other hand, the programs 41g to 44g having only general-purpose instructions have the number of reads / writes to the external RAM 2 via the bus 20 in consideration of the capacities of the instruction cache 32 and data cache 35 and the instruction RAM 33 and data RAM 36 built in the CPU. Coded to be less. For example, the amount of data used in a certain loop process is set below the capacity of the data cache 35.

Note that the ASIC 1 described above can be designed by, for example, Tensilica's Xtensa technology. When the Xtensa technology is used, each dedicated instruction described above can be defined by using an instruction extension TIE (Tensilica Instruction Extension) provided by the Xtensa technology, and the hardware configuration of each dedicated instruction calculation unit 12b to 18b Xtensa
It is feasible with technology. By using dedicated instructions set using TIE,
The same operation is speeded up 2 to 5 times, but in some cases it is speeded up to several tens of times.

Next, a series of image processing executed by the apparatus will be described. FIG. 4 is a flowchart for describing a series of image processing executed by the apparatus according to the first embodiment.

In this apparatus, first, JPEG data included in a JPEG image file is decoded (step S1). The decoded image data is RGB image data.

Next, image correction is performed on the decoded image data as necessary (step S2). As the image correction, one or more of a first process that performs tone adjustment and saturation enhancement, a second process that performs sharpness, and a third process that performs noise removal are performed as necessary.

Then, resizing and layout processing is performed on the image data after image correction (step S3). In the resizing process, the size of image data (the number of vertical and horizontal pixels) is changed at an enlargement / reduction ratio corresponding to the print resolution, print paper size, and number of images to be printed on one sheet. In the layout process, image data (RGB data) that matches the print image is generated.

Next, the color coordinate system is changed. In the first embodiment, the RGB image data after the resizing and layout processing is converted into CYMK image data (step S4). In the first embodiment, the RGB image data is CYMK image data of 7 colors (cyan C,
Yellow Y, Magenta M, Black K, Red R, Blue B, Clear (Glossy) CL)
Is converted to

Halftone is performed on the image data of each color in the CYMK image data after color conversion (step S5). In the halftone, the image data of each color is binarized by a dither method or an error dispersion method.

Then, based on the image data of each color after binarization, the CPU 11 causes the printer driver 4
Is controlled, and an image is printed on the medium (step S6). At that time, for example, a microweave process is appropriately performed.

In this way, general-purpose image data such as JPEG data is converted into a data format suitable for the drive control of the printer drive unit 4 unique to the printer.

Here, the flow of data when the above-described processing is executed in the image processing apparatus according to Embodiment 1 will be described. Here, for the sake of simplicity of explanation, a description will be given on the assumption that a part of a certain process is not executed by a CPU that executes a CPU of another type. However, the CPUs 15 to 18 perform halftone dispersion processing. FIG. 5 is a block diagram illustrating a data flow when a series of image processing is executed in the image processing apparatus according to the first embodiment.

First, JPEG data contained in the JPEG file 3a in the memory card 3 is stored in the CPU 1
2 (flow F1).

Based on the JPEG file 3a, print paper size, print resolution, and user-specified conditions, parameters for specifying the type and degree of image correction, parameters for specifying an LUT (lookup table) for color conversion, and half Tone setting parameters (parameters for selecting a binarization method, setting a coefficient pattern of error variance at the time of binarization, etc.) are generated, transferred from the CPU 12 to the dual port RAM 21, and stored.

After JPEG decoding by the CPU 12, the decoded image data is transferred from the CPU 12 to the dual port RAM 21 for each predetermined block or band, stored, and then read by the CPU 13 (flow F2).

Further, a parameter relating to image correction is read from the dual port RAM 21 by the CPU 13, and image correction corresponding to the parameter is executed by the CPU 13 on the image data read from the dual port RAM 21. After the image correction, the processed image data is transferred from the CPU 13 to the external RAM 2 and stored therein, and then read out by the CPU 12 (flow F3).

After the resizing / layout processing by the CPU 12, the processed image data is CP
After being transferred from U12 to the external RAM 2 and stored, it is read by the CPU 14 (flow F4).

Next, a parameter relating to color conversion is read from the dual port RAM 21 by the CPU 14, and color conversion corresponding to the parameter is executed by the CPU 14. After color conversion, the processed image data is transferred from the CPU 14 to the dual port RAM for each block of a predetermined size.
After being transferred to 22 and stored, it is sequentially read out by the CPUs 15 to 18 (flow F5).

Next, the parameters relating to the halftone are changed from the dual port RAM 21 to the CPU 15-.
18 and halftones corresponding to the parameters are executed by the CPUs 15-18. After halftone processing, the processed image data is transferred from the CPU 15-18 to the external RAM.
After being transferred to 2 and stored, it is read by the CPU 11 (flow F6).

As described above, the path of the dual port RAMs 21 and 22 and the path of the external RAM 2 are used for transferring the image data between the CPUs 11 to 18.

Here, the description has been made assuming that the distributed processing is not performed as described above. However, when the distributed processing is executed by the CPU having the dedicated instruction calculation unit and other CPUs, the CPU 1 is similarly processed.
The dual port RAMs 21 and 22 and the external RAM 2 are used for transferring image data between the CPU 1 and the CPU 18, and parameters relating to various processes, image data after JPEG decoding, and image data after color conversion are transferred: Dual port RAMs 21 and 22 are used.

FIG. 6 is a diagram illustrating an example of a data processing flow and a time sequence when distributed processing is not performed by a CPU having a dedicated instruction calculation unit and other CPUs. In FIG. 6, the period of each process is shown for each block that is a unit of image data processing. The numbers in the figure indicate the block numbers. That is, the block with “(1)” indicates a series of processes for the same part in the image.

As shown in FIG. 6, for example, for the block (1), in the period from T0 to T1, C
The JPEG decoding is executed by the PU 12, the image correction is executed by the CPU 13 during the period T1 to T2, the resizing and layout are executed by the CPU 12 during the period T2 to T3, and the color conversion is executed by the CPU 14 during the period T3 to T4. CPU15
Thus, halftone is executed, and then the control of the printer driving unit 4 by the CPU 11 is executed.

In FIG. 6, the data transfer time is not shown. In addition, since halftone is sequentially executed on data for which color conversion has been completed, color conversion and halftone for the same block are executed substantially in parallel.

Also, the processing is executed in the same order for the blocks (2),... After the block (1). Further, in order to increase the utilization efficiency of the CPUs 11 to 18, as shown in FIG. 6, JPEG decoding, image correction, color conversion, halftone, and drive unit control are as follows.
Pipeline processing is executed.

Here, it has been described that the distributed processing in which the same processing is executed by a plurality of CPUs other than the halftone distributed processing by the CPUs 15 to 18 is not performed, but in the first embodiment, in practice, The same processing is performed by a plurality of CPUs (CPs having a dedicated instruction calculation unit for the processing)
U and other CPUs) may be executed in a distributed manner.

Up to this point, in order to briefly describe a series of image processing executed by the image processing apparatus according to the first embodiment and the basic operation of the image processing apparatus, the CPUs 15 to 18 are described.
In the above description, it is assumed that the distributed processing in which the same processing is executed by a plurality of CPUs is not performed other than the halftone distributed processing according to the above. Next, distributed processing executed by the image processing apparatus according to the first embodiment will be described.

In the distributed processing executed by the image processing apparatus according to the first embodiment, (1) distributed ratio determination processing for determining the processing ratio in each processing unit (CPU 12, CPU 13, CPU 14, CPU 15-18) for each processing type. (2) Start processing for starting processing corresponding to the processing rate determined in the distribution ratio determination process to the processing unit assigned processing in the distribution ratio determination processing for each processing type; (3) Assigned for each processing type Individual processing for executing processing corresponding to the processing ratio is executed.

FIG. 7 is a block diagram illustrating distributed processing executed by the image processing apparatus according to Embodiment 1 of the present invention.

As shown in FIG. 7, the distribution ratio determination process 61 is executed by the CPU 12. The distribution ratio determination process 61 is realized by the CPU 12 executing a program (not shown) describing the distribution ratio determination process 61. The program is stored in the external RAM 2, for example. In the distribution ratio determining process 61, the CPU 12 has data (predetermined processing capacity) of each processing unit (four CPUs 12, 13, 14, and 15 to 18) corresponding to each processing type stored in the processing capacity table 52. Each processing so that the calculation time required for one or more individual processes assigned to each processing unit is as uniform as possible. The processing ratio to each processing unit for the type is determined. The load distribution table 51 and the processing capacity table 52 are preferably stored in the dual port RAMs 21 and 22, but may be stored in the external RAM 2.

FIG. 8 is a diagram showing an example of the processing capability table 52 according to Embodiment 1 of the present invention.
The processing capacity table 52 is a preset default processing capacity table 52a (FIG. 8 (
A)) and a processing capability table 52b (FIG. 8B) including processing capability information collected during each actual individual processing 63 for the image data.

The processing capability table 52a has default processing capability information (processing speed in FIG. 8) for combinations of processing units and processing types. In the processing capacity table 52a, the processing type is JP.
EG decoding, first image correction process (tone adjustment and saturation enhancement), second image correction process (sharpness), third image correction process (noise removal), color conversion, dither halftone, and error One of the halftones by the diffusion method, and the processing unit is CP
It has a default value of processing capability information for all combinations of any of U12, CPU13, CPU14, and CPU15-15. For example, the default value of the processing capability information of the CPU 12 for JPEG decoding is 800 × 1000 pixels / second.

The processing capability table 52b includes processing capability information for combinations of processing units and processing types as measured values measured for each band or line of image data when processing certain image data (in FIG. 8, Processing speed). In the state shown in FIG. 8B, the processing capability information 52 (760 × 100) of the CPU 12 regarding JPEG decoding is stored in the processing capability table 52b.
0 pixel / second), JPEG decoding and three image correction processing information of the CPU 13 (300 × 1000 pixels / second, 2,300 × 1000 pixels / second, 1,190 × 100)
0 pixel / second, 350 × 1000 pixel / second), processing capacity information of the CPU 14 for color conversion (1,600 × 1000 pixel / second), and the first processing of image correction and the CPU 15 to 18 for halftone Processing capability information (543 × 1000 pixels / second, 980 × 100
Only 0 pixel / second) is registered. That is, for the other combinations, the individual processing for one band or one line is not executed, so that the processing capability information is not registered.

The CPU 12 refers to the processing capability information in the processing capability table 52 during the distribution ratio determination process, but preferentially uses the value of the processing capability table 52b. That is, when the processing capability information is collected for a combination of a certain CPU and processing type, the processing capability table 52b.
Is used and the default value of the processing capacity table 52a is used.

The processing capacity information of the CPUs 15 to 18 includes representative values of the processing capacity information of the four CPUs 15 to 18 (a predetermined CPU value, an average value, a maximum value, a minimum value, etc. of the CPUs 15 to 18).
Is used. Moreover, about the process part which CPU15-18 comprises, CPU15-18
Any one of the CPUs may update the processing capability information in the processing capability table 52 with the representative value.

FIG. 9 is a diagram showing an example of the load distribution table 51 according to Embodiment 1 of the present invention.
The load distribution table 51 shown in FIG. 9 is an example in the case where four pieces of image data of 2592 × 1944 pixels are printed at 1440 × 720 dpi on 8 × 11 inch printing paper.
The load distribution table 51 includes the number of pixels of the output image data and the CP for each processing type.
Each of the processing capacity values of U12, CPU 13, CPU 14, and CPUs 15 to 18 (equivalent to the processing capacity information in the processing capacity table 52), processing ratio, and processing time (expected time)
Have

Further, the load distribution table 51 includes CPU 12, CPU 13, CPU 14, and CPU.
Total processing time of 15 to 18 (total processing time for six processing types) Tcp
u, the average value and the maximum value of the total processing time of CPU12, CPU13, CPU14 and CPU15-18, and CPU12, CPU13, CPU14 and CPU15-18
The difference between the total processing time and the above average value.

In the distribution ratio determination process, the processing ratio is calculated based on the number of pixels of the output image data for each processing type and the processing capability values of the CPUs 12, 13, and 14 and CPUs 15 to 18 for each processing type. Note that the number of pixels of output image data for each processing type is calculated from the number of pixels of JPEG data, printing conditions, and the like. Further, the CPU 12 for each processing type,
The processing capability information values in the processing capability table 52 are used as they are as the processing capability values of the 13, 14 and CPUs 15-18.

Next, the start processing 62 is a JPE that causes one or more processing units to start JPEG decoding.
G decode start processing 62a, image correction start processing 62b for starting image correction by one or more processing units, color conversion start processing 62c for starting color conversion by one or more processing units, and one or more halftones It consists of a halftone start process 62d to be started by the processing unit. When a CPU that executes each of the start processes 62a to 62d requests an individual process from a CPU other than itself, it issues a process request to that CPU.

The JPEG decoding start process 62a is executed by the CPU 12, and the image correction start process 6a.
2b is executed by the CPU 13, and the color conversion start process 62c and the halftone start process 62d are executed by the CPU 14. Each start process 62a, 62b, 62c, 62d is a program (not shown) that describes each start process 62a, 62b, 62c, 62d.
This is realized by executing steps 12, 13, and 14. These programs are for example external RA
Stored in M2.

The distribution ratio determining process 61 and the start process 62 are fixedly executed by a CPU assigned in advance. Also, the distribution ratio determination process 61 and the start process 62 are repeatedly executed asynchronously with each other.

The distribution ratio determining process 61 is executed every time the processing capability information is updated for all types of processes. Each of the start processes 62a to 62d is repeatedly executed whenever JPEG decoding, image correction, color conversion, or halftone is completed for a predetermined amount of data, and the processing of the predetermined amount of data is performed in one or a plurality of processing units. Assigned as individual processing 63.

Then, for each processing type, the individual processing 63 of the amount allocated by the start processing 62 is executed by the allocated processing unit.

In the first embodiment, for JPEG decoding, the CPU 12 having the JPEG decoding dedicated instruction calculation unit 12b, or the CPU 12 and other CPUs 13 to 18 for image processing.
Individual processing 63 is assigned to two CPUs, one of which is a CPU (CPU_X).

In the following, for each processing type, a CP having a dedicated instruction calculation unit for that processing type.
Of the CPUs for image processing other than U, one CPU to which individual processing is assigned is C
It is called PU_X.

When the CPU 12 executes JPEG decoding by itself, only the CPU 12
PEG decoding individual processing 63a is executed. When the CPU 12 and CPU_X execute JPEG decoding, the CPU 12 executes JPEG decoding individual processing 63a, and any one of the CPUs 13 to 18 executes JPEG decoding individual processing 63e. At that time, the JPEG decode individual processing 63a is realized by the CPU 12 executing the JPEG decode program 41s. The JPEG decode individual process 63e is realized by the CPU_X executing the JPEG decode program 41g.

In the first embodiment, when JPEG decoding is executed by two CPUs, JP
Ratio of processing data amount between EG decoding individual processing 63a and JPEG decoding individual processing 63e (
The dispersion ratio) is any one of 3: 1, 1: 1, and 1: 3. Therefore, the processing ratios for the processing units that execute the individual processes 63a and 63e are 0, 0.25, 0.5, 0.
One of 75 and 1.

In the first embodiment, for image correction, the individual process 63 is assigned to the CPU 13 having the image correction dedicated command calculation unit 13b, or the two CPUs of the CPU 13 and CPU_X. When the CPU 13 performs image correction alone, the image correction individual processing 63b is executed only by the CPU 13. When the CPU 13 and the CPU_X execute image correction, the CPU 13 executes the image correction individual process 63b, and the CPUs 12 and 14 are executed.
Image correction individual processing 63f is executed by any one of -18. At this time, the individual image correction process 63b is realized by the CPU 13 executing the image correction program 42s. Further, the individual image correction process 63f is realized by the CPU_X executing the image correction program 42g.

In the first embodiment, when image correction is executed by two CPUs, the ratio (dispersion ratio) of the processing data amount between the image correction individual processing 63b and the image correction individual processing 63f is 3: 1, 1.
1: and 1: 3. Accordingly, the processing ratio for the processing units that execute the individual processes 63b and 63f is one of 0, 0.25, 0.5, 0.75, and 1.

In the first embodiment, for color conversion, the individual processing 63 is assigned to the CPU 14 having the color conversion dedicated instruction calculation unit 14b, or the two CPUs of the CPU 14 and CPU_X. When the CPU 14 executes color conversion alone, the color conversion individual processing 63c is executed only by the CPU 14. When the CPU 14 and CPU_X execute color conversion, the CPU 14 executes the color conversion individual processing 63c, and the CPUs 12, 13, 15 to 18 are executed.
The color conversion individual process 63g is executed by any one of the above. At that time, color conversion individual processing 63
c is realized by the CPU 14 executing the color conversion program 43s. Further, the individual color conversion process 63g is realized by the CPU_X executing the color conversion program 43g.

In the first embodiment, when color conversion is executed by two CPUs, the ratio (dispersion ratio) of the processing data amount between the color conversion individual processing 63c and the color conversion individual processing 63g is 3: 1, 1: 1,
And 1: 3. Accordingly, the processing ratio for the processing units that execute the individual processes 63c and 63g is one of 0, 0.25, 0.5, 0.75, and 1.

In the first embodiment, halftone dedicated instruction calculation unit 1 is used for halftone.
CPU15-18 which has 5b-18b, or 5 of CPU15-18 and CPU_X
Individual processing 63 is assigned to each CPU. When the CPUs 15 to 18 perform color conversion, the halftone individual processing 63d is executed only by the CPUs 15 to 18. CPU
When 15 to 18 and CPU_X execute the halftone individual processing, the CPU 15 to
18, the halftone individual process 63d is executed, and any one of the CPUs 12 to 14 executes the halftone individual process 63h. At that time, the halftone individual processing 63d is realized by the CPUs 15 to 18 executing the halftone program 44s.
Further, the halftone individual process 63h is realized by the CPU_X executing the halftone program 43h.

In the first embodiment, seven colors of CMYK image data are generated by color conversion.
A binarization process by a dither method is executed for two colors of the CMYK image data of colors 5
A binarization process using an error diffusion method is performed on the color. Since the calculation amount of the binarization processing by the dither method is much smaller than the calculation amount of the binarization processing by the error diffusion method, the four CPUs 15 to
When halftone is performed at 18, the CPU 15 executes binarization processing by the error diffusion method for two colors, and the CPU 16 performs binarization processing by the error diffusion method for one color and the dither method for one color. A binarization process is executed, a binarization process by an error diffusion method for one color and a binarization process by a dither method for one color are executed by the CPU 17, and a binary value by an error diffusion method for one color is executed by the CPU 18. Processing is executed.

On the other hand, when halftone is performed by the CPUs 15 to 18 and the CPU_X, the CPU 15
The binarization processing by the error diffusion method for one color is executed by the CPU 16, the binarization processing by the error diffusion method for one color and the binarization processing by the dither method for one color are executed by the CPU 17, and 1 is executed by the CPU 17. A binarization process by an error diffusion method for one color and a binarization process by a dither method for one color are executed, and a binarization process by an error diffusion method for one color is executed by the CPU 18, and one color is processed by the CPU_X. The binarization process by the error diffusion method is executed.

Therefore, when halftone is executed by five CPUs, halftone individual processing 63d
The ratio (dispersion ratio) of the processing data amount between the halftone individual processing 63h and the halftone individual processing 63h is approximately 4: 1.

In each of the individual processes 63a to 63g, when the assigned image processing (one band or one line of image data) is completed, data such as the time and the amount of processing data required for the assigned image processing is processed as processing capability data. Stored in the processing capacity table 52. And
This processing capacity data is reflected in the subsequent distribution ratio determination processing 61.

In the first embodiment, each CPU 12 is running a multitasking OS. In the CPU 12, the dispersion ratio determination process 61a, the JPEG decode start process 62a and the J
Two of the individual PEG decoding processes 63b and the other individual processes 63f, 63g, 63
Each h is executed as a separate task (process). Further, the multitask OS may be operated in the CPUs 13-18. In that case, for example, CPU 1
3, the image correction start process 62b and the image correction individual process 63b, and the other individual processes 63e, 63g, and 63h are executed as separate tasks (processes). In the CPU 14, the color conversion start process 62c, the color conversion individual process 63c, the halftone start process 62d, and the other individual processes 63e, 63f, and 63h are executed as separate tasks (processes). . Moreover, in each CPU of CPU15-18,
The halftone individual process 63d and the other individual processes 63e, 63f, and 63g are executed as separate tasks (processes).

Here, details of the distribution ratio determination processing 61 will be described. FIG. 10 is a flowchart for explaining the distribution ratio determination processing 61 in Embodiment 1 of the present invention.

First, the CPU 12 generates a default load distribution table 51 based on image data (JPEG data) to be processed, printing conditions (printing paper, printing resolution), a default processing capacity table 52a, and the like (step S11). The first load distribution table 5
1, for JPEG decoding, the processing rate of the CPU 12 is 1, and other CPs
The processing rate of U13 to 18 is zero. In addition, regarding the first process to the third process of image correction,
The processing rate of the CPU 13 is 1, and the processing rates of the other CPUs 12, 14 to 18 are 0. For color conversion, the processing ratio of the CPU 14 is 1, and the other CPUs 12,
The processing ratio of 13, 15 to 18 is 0. For halftone, CPU15 ~
The processing ratio of the CPU 18 is 1, and the processing ratios of the other CPUs 12 to 14 are 0.

Next, the CPU 12 performs processing for one band or one line of image data from the start end to the end of the image in the horizontal direction (the direction in which the image data of adjacent image areas are continuous in the vertical direction and the horizontal direction). However, it waits until it finishes at least once about all the processing types (JPEG decoding, 3 processes of image correction, color conversion, and a halftone) (step S12).

Note that one process from the beginning to the end of the image horizontal direction in JPEG decoding is one band composed of pixels corresponding to the vertical direction of the MCU (Minimum Coded Unit) in the vertical direction and pixels corresponding to the horizontal width of the image. JPEG decoding for. Note that the MCU is a block of 8 vertical pixels and 8 horizontal pixels.

In addition, the one-time processing from the start edge to the end edge in the image horizontal direction in the image correction is performed for the first process for one line of image data (that is, the vertical region is one pixel and the horizontal direction is a pixel area corresponding to the horizontal width of the image).
Processing to third processing.

In addition, one processing from the start edge to the end edge in the horizontal direction of the image in the color conversion is performed with 2 of the image data.
Color coordinate conversion processing for the line is performed.

Further, a single process from the start edge to the end edge in the horizontal direction of the image in the halftone is a binarization process for two lines of image data.

As described above, the pixel area related to one process from the start edge to the end edge in the horizontal direction of the image differs depending on the processing type, and the calculation amount differs depending on the processing type. Individual processing in the processing type does not end at the same time. However,
In individual processing for all processing types, barrier synchronization is not performed. When processing for one band or one line is completed in each processing type, individual processing for the next one band or one line is immediately performed after the start processing. Be started.

For determining whether or not processing for one band or one line has been completed at least once for all processing types, a flag for the processing type is set, for example, in the processing capability table 52b.
The processing unit that executes each individual processing 63 sets the processing type flag of the individual processing 63 when the individual processing 63 for one band or one line is completed, and the CPU 12 It may be determined whether or not processing for one band or one line has been completed at least once for all processing types depending on whether or not the user is standing. In that case, CPU
No. 12 lowers all the flags when it is determined that the processing for one band or one line has been completed at least once for all processing types.

If the CPU 12 determines that the processing for one band or one line has been completed at least once for all processing types, the CPU 12 determines the processing ratio of each processing unit for each processing type based on the processing capacity table, The distribution table 51 is updated (step S13).
In the first embodiment, for each processing type, individual processing for one band or one line 6
3 is completed, the processing unit that executes the individual processing 63 updates the processing capability information for the combination of the processing type and the self, so that processing for one band or one line is performed for all processing types. By updating the load distribution table 51 after completing at least once, the processing ratio to each processing unit is determined in consideration of the dynamically changing processing capability value of all the processing units.

Then, the processes in step S12 and step S13 described above are repeated until the image data is finished, and when there is no image data to be processed in any of the processing types, the distribution ratio determining process 61 ends (step S14).

Here, FIG. 11 is a flowchart for explaining the details of the load distribution table update process (step S13) in FIG.

In the load distribution table update process (step S13), first, the CPU 12 updates the processing capacity value of the load distribution table 51 corresponding to each processing capacity information of the processing capacity table 52 (step S13a). Further, the CPU 12 determines the number of pixels of the output image of each processing type (that is, the pixel to be processed) based on the size of the image data (input image data) of the JPEG file 3a, the number of print images, the print paper size, the print resolution, and the like. The number is calculated and registered in the load distribution table 51.

Then, the CPU 12 sets the processing ratio for each processing type to a default value (step S13b). By default, for each processing type, the processing ratio of the CPU having the dedicated instruction calculation unit corresponding to the processing type is 1, and the processing ratio of the other CPUs is 0.
Therefore, for example, for JPEG decoding, the processing ratio of the CPU 12 is 1.
The processing ratio of the CPUs 13, 14, 15 to 18 is zero.

Next, the CPU 12 calculates the processing time Tcpu for each processing unit, the average processing time Tav, and the deviation dTcpu of the processing time Tcpu for each processing unit from the average processing time Tav (step S13c).

At that time, the CPU 12 refers to the load distribution table 51, and for each processing type, based on the number Np of pixels to be processed, the processing capability value P of each processing unit, and the processing ratio α of each processing unit. The processing time T (T = Np × α × P) for the type is calculated. Further, the CPU 12 processes JPEG decoding processing time T1 and image correction first processing time T2 for a certain processing unit,
The sum of the processing time T3 of the second processing of image correction, the processing time T4 of the third processing of image correction, the processing time T5 of color conversion, and the processing time T6 of halftone is the processing time Tcpu (T
cpu = T1 + T2 + T3 + T4 + T5 + T6).

In addition, the CPU 12 performs processing time Tcpu12 for the CPU 12 and processing time Tc for the CPU 13.
pu13, processing time Tcpu14 of CPU 14, and processing time T of CPUs 15-18
The average value of cpu15 to 18 is calculated as the average processing time Tav (Tav = (Tcpu1
2 + Tcpu13 + Tcpu14 + Tcpu15-18) / 4).

Further, the CPU 12 calculates a processing time deviation dTcpu for each processing unit from the processing time Tcpu and the average processing time Tav. For example, the processing time deviation dTcpu12 for the CPU 12 is (Tav−Tcpu12).

Next, based on the calculation result in step S13c, the CPU 12 determines the processing unit (CPU_A) having the maximum processing time Tcpu, the processing type (PROC_A) having the maximum processing time T among the processing of CPU_A, and other than CPU_A. One or more processing units (CPs) that execute only the processing types assigned by default and do not execute distributed processing of other processing types among the processing units
U_X) is specified (step S13d).

For example, in the case of the load distribution table 51 shown in FIG. 9, CPU_A is identified as CPU 13, PROC_A is identified as the third image correction process (noise removal), and CPU_X is defined as
It is specified as CPU 12, CPU 14, and CPUs 15-18.

Next, the CPU 12 calculates the processing ratio of the CPU_A and the CPU_X for each combination of the predetermined distribution ratio (1: 0, 3: 1, 1: 1, 1: 3, etc.) and the CPU_X, and at the processing ratio. The processing time Tcpu for CPU_A and CPU_X is calculated (step S13e).

For example, when the distribution ratio of CPU_A and CPU_X is 3: 1, the processing ratio of CPU_A is 0.75, and the processing ratio of CPU_X is 0.25.

Next, the CPU 12 processes the CPU_A processing time Tcpu and the CPU_X processing time Tcpu.
CPU_X and the distribution ratio that minimize the processing time of which is larger are specified, and the processing ratio of CPU_A and CPU_X is calculated based on the distribution ratio (step S13f).

Further, the CPU 12 calculates the processing time Tcpu, the average processing time Tav for each processing unit, and the deviation dTcpu for the processing time for each processing unit based on the processing ratio between CPU_A and CPU_X calculated in step S13f (step S13g).

Then, the CPU 12 determines whether or not the maximum value of the processing time Tcpu calculated in step S13g is smaller than the maximum value of the processing time Tcpu recorded in the load distribution table 51 (step S13h).

When the maximum value of the processing time Tcpu calculated in step S13g is smaller than the maximum value of the processing time Tcpu recorded in the load distribution table 51, the CPU 12 proceeds to step S13.
The corresponding values in the load distribution table 51 are updated with the values of the processing ratio, processing time Tcpu, average processing time Tav, and processing time deviation dTcpu calculated in f and S13g (step S13i).

On the other hand, the maximum value of the processing time Tcpu calculated in step S13g is the load distribution table 5
If it is not equal to or greater than the maximum value of the processing time Tcpu recorded in 1, the CPU 12 ends the load distribution table update process (step S13).

In this way, while the maximum value of the processing time Tcpu for each processing unit decreases, step S13d.
Step S13i is repeatedly executed, and the load distribution table 51 is updated.
In this load distribution table update process, the heaviest process among the processes assigned to the CPU with the heaviest load is distributed, so that the load on the processing unit is made uniform.

Here, as an example, the update of the load distribution table 51 shown in FIG. 9 will be described. FIG.
2 is a diagram showing the load distribution table 51 in the middle of updating the load distribution table 51 of FIG.
FIG. 13 is a diagram showing a load distribution table 51 obtained by updating the load distribution table 51 of FIG.

First, in the load distribution table 51 shown in FIG. 9, CPU_A is identified as CPU 13,
CPU_X is identified as CPU12, CPU14 and CPU15-18, and PROC_
A is identified as the third image correction process (noise removal) (step S13d).

Next, the processing ratio of the CPU 13 and the processing ratio of the CPU_X are 1 and 0, 0.75 and 0.25.
, 0.5 and 0.5, 0.25 and 0.75, and 0 and 1 respectively.
The processing time of 13 and the processing time of CPU_X are calculated (step S13e), and the calculated C
A dispersion ratio is selected that minimizes the processing time that is larger between the processing time Tcpu of the PU 13 and the processing time Tcpu of the CPU_X (step S13f).

In the case of the load distribution table 51 shown in FIG. 9, with respect to the third process of image correction (noise removal),
(A) The processing time Tcpu of the CPU 13 when the processing ratio is 1.00 is 75.97,
(B) The processing time Tcpu of the CPU 13 when the processing ratio is 0.75 is 63.37,
(C) The processing time Tcpu of the CPU 13 when the processing rate is 0.50 is 50.78,
(D) The processing time Tcpu of the CPU 13 when the processing ratio is 0.25 is 38.18.

Also, when distributing the third image correction process (noise removal) to the CPU 12,
(A) The processing time Tcpu12 when the processing ratio is 1.00 is 176.73,
(B) The processing time Tcpu12 when the processing ratio is 0.75 is 138.85,
(C) The processing time Tcpu12 when the processing ratio is 0.50 is 100.96,
(D) The processing time Tcpu12 when the processing rate is 0.25 is 63.08.

Further, when distributing the third process of image correction (noise removal) to the CPU 14,
(A) The processing time Tcpu14 when the processing rate is 1.00 is 237.22.
(B) The processing time Tcpu14 when the processing ratio is 0.75 is 183.62.
(C) The processing time Tcpu14 when the processing rate is 0.50 is 130.02,
(D) The processing time Tcpu14 when the processing ratio is 0.25 is 76.41.

Further, when distributing the third process of image correction (noise removal) to the CPUs 15 to 18,
(A) The processing time Tcpu15 to 18 when the processing ratio is 1.00 is 76.41,
(B) The processing time Tcpu15 to 18 when the processing ratio is 0.75 is 63.01,
(C) The processing time Tcpu15 to 18 when the processing ratio is 0.50 is 49.61,
(D) The processing time Tcpu15 to 18 when the processing ratio is 0.25 is 36.21.
The processing time of the four CPUs 15 to 18 is one CPU in the CPUs 15 to 18.
Is calculated as one-fourth of the processing time.

Therefore, the CPU_X and the processing ratio at which the processing time of the larger processing time Tcpu of the CPU 13 and the processing time Tcpu of the CPU_X becomes the minimum are the CPUs 15 to 18, 0.5.
(The processing ratio of the CPU 13) and 0.5 (the processing ratio of the CPUs 15 to 18) are selected.
The processing ratio of the CPUs 12 and 14 for the third image processing is 0.

Then, at the calculated processing rate, the processing time Tcpu, the average processing time Tav, and CP
The deviation dTcpu of the processing time for each U is calculated (step S13g). At this time, CPU
The processing times Tcpu of 12 to 14 are 25.19, 50.78, and 22.81, respectively, and the processing times Tcpu of the CPUs 15 to 18 are 49.61. And average processing time T
Av is 37.10, and the maximum value of the processing time Tcpu is 50.78. CPU
The deviations dTcpu of the processing times of 12 to 14 are -11.90, 13.68, -1 respectively.
4.29, and the processing time deviation dTcpu of the CPUs 15 to 18 is 12.51.

Since the maximum value (= 50.78) of the processing time Tcpu at this time is smaller than the maximum value (= 75.97) of the processing time Tcpu of the load distribution table 51 (FIG. 9) at this time,
The update process of the load distribution table 51 is continued (step S13h).

The calculated processing ratio, processing time T for each processing type for each processing unit, processing time Tcpu for each processing unit, average value Tav and maximum value thereof, and processing time deviation dTcpu,
The value of the corresponding load distribution table 51 is updated (step S13i).

For the load distribution table 51 shown in FIG. 9, steps S13d, S13e, S13f,
What performed the process of S13g and S13i becomes the load distribution table 51 shown in FIG.

Next, returning to step S13d, for the load distribution table 51 shown in FIG.
U_A is specified as CPU 13, and CPU_X is CPU 12, CPU 14, and CPU
15 to 18 are specified, and PROC_A is specified as the second image correction process (sharpness).

Similarly, the processes of steps S13e, S13f, and S13g are executed. As a result, the maximum value of the processing time Tcpu is 49.49.

Since the maximum value (= 49.49) of the processing time Tcpu at this time is smaller than the maximum value (= 50.78) of the processing time Tcpu of the load distribution table 51 (FIG. 12) at this time, the load distribution table The update process 51 is continued (step S13h).

Then, the calculated processing ratio, processing time T for each processing type, processing time Tcpu for each processing unit
Then, the corresponding value of the load distribution table 51 is updated with the average value Tav, the maximum value, and the processing time deviation dTcpu (step S13i).

Steps S13d, S13e, and S13f are applied to the load distribution table 51 shown in FIG.
, S13g, and S13i are processed as a load distribution table 51 shown in FIG.

And with respect to the load distribution table 51 shown in FIG. 13, steps S13d, S13e,
The processes of S13f and S13g are executed, and the maximum value of the resulting processing time Tcpu is
The maximum value (= 49.49) of the processing time Tcpu of the load distribution table 51 (FIG. 13) at this time
), The update process of the load distribution table 51 is terminated (step S).
13h).

In this example, the load distribution table 51 shown in FIG. 9 is shown in FIG. 13 so that the loads of the CPUs 12 to 18 are uniformly approached according to the processing ability information in the processing ability table 52 shown in FIG. Updated to the load distribution table 51.

As described above, the image processing apparatus according to the first embodiment includes the CPUs 12 to 18 as a plurality of processing units that sequentially perform a plurality of types of image processing on image data in the same region, and various types of image processing. A load distribution table 51 having a distribution ratio to one or a plurality of processing units and having a default distribution ratio as an initial value, and a distribution ratio updating unit that calculates and updates the distribution ratio of each image processing after the start of image processing As a start processing means for distributing the image processing to two or more processing units for one type of image processing using the default distribution ratio for the distribution ratio that has never been updated. CPU 12-14
With.

Thereby, load distribution can be appropriately performed from the beginning of processing to a plurality of processing units,
Furthermore, even when there are three or more processing units, load distribution can be performed appropriately.

The image processing apparatus according to Embodiment 1 further stores a processing capability table 52b that stores the processing capability values of the plurality of processing units, and a default value of the processing capability values of the plurality of processing units. And a CPU 12-18 as processing capacity table updating means for updating the processing capacity value of the processing capacity table based on the processing time for a predetermined amount of image data by each of the plurality of processing units. Then, the CPU 12 as the distribution ratio update means refers to the processing capacity table 52b preferentially, calculates the distribution ratio of each image processing based on the processing capacity table 52b and the default processing capacity table 52a, and stores it in the load distribution table 51. Set.

As a result, it is possible to perform load distribution appropriately for the plurality of processing units from the beginning of the processing and dynamically corresponding to the load that fluctuates according to the contents of the image data, and the number of processing units is three or more. However, load distribution can be performed appropriately.

In the first embodiment, the processing capability value is updated in the processing capability table 52 based on the processing time and the number of processing pixels for each line or band.

As a result, the processing capability value at the time of processing the actual image data is acquired and reflected in the distribution ratio. Therefore, an accurate load corresponding to the calculation amount for each type of image processing for each image data is obtained. Dispersion is possible.

In the first embodiment, the processing capacity table 52 includes a plurality of processing units (CPUs 12 to 12).
Each of (18) has a processing capability value for each of a plurality of types of image processing.

As a result, for example, even when the processing unit is optimized only for a predetermined type of image processing, an accurate processing capability value can be obtained, and thus accurate load distribution can be performed.

In the first embodiment, after setting the distribution ratio, when the image processing of the type with the slowest processing time for one line or one band among a plurality of types is completed, the distribution ratio determination processing 61 again performs the distribution ratio. Is set.

Thereby, since all the processing units execute processing for at least one line or one band and the distribution ratio is set, an appropriate distribution ratio reflecting the processing capability value at each time point can be set. .

Embodiment 2. FIG.
The image processing apparatus according to the second embodiment of the present invention has the same configuration and functions as the image processing apparatuses according to the other embodiments, and includes a JPEG decoding start process 62a and individual processes 63a,
63e is executed as follows.

Also in the second embodiment, as shown in FIG.
It is executed by the CPU 12. In the start process 62a, the JPEG decode individual process (63a
, 63e) are assigned to one or two processing units.

Further, the JPEG decode individual processing (63a, 63e) is assigned to the CPU 12 when executed by one processing unit, and is executed by the CPU 12 and the CP when executed by two processing units.
It is assigned to any one of U13, CPU 14 and CPUs 15-18 (CPU_X) based on the distribution ratio of the load distribution table 51.

FIG. 14 is a flowchart for explaining the JPEG decoding start process 62a in the second embodiment.

In the JPEG decoding start process 62a, the CPU 12 first determines J for 4 × N MCUs.
PEG data is read from the JPEG file 3a of the memory card 3 into the external RAM 2 (step S21).

Note that the MCU is the minimum unit of decoding. In the second embodiment, the processing rate is 0.00.
Since it is set to one of multiples of 25 (= 1/4), the minimum data unit of distributed processing is M
In order to obtain a CU, data for multiples of 4 (4 × N) MCUs are read at a time. N is a number that is so large that the overhead caused by the distribution (an increase in the amount of calculation generated by dividing the processing, a processing delay due to an increase in the communication amount, etc.) can be ignored,
4 × N is a number that is smaller than the number of MCUs in the horizontal direction of the JPEG data. For example, N = 10.

Next, the CPU 12 extracts the DC components of the read 4 × N MCUs (step S).
22).

Then, the CPU 12 performs C for JPEG decoding in the load distribution table 51.
The processing ratio value of the PU 12 is read, and based on whether the value is 1 or not, it is determined whether or not the JPEG decoding is distributed by the two processing units (step S23). CPU
12 determines that the distributed processing is not performed when the value of the processing ratio is 1, and determines that the distributed processing is performed when the value of the processing ratio is less than 1.

If it is determined that JPEG decoding is distributed by two processing units, a C other than the CPU 12
A process of giving distributed processing to PU_X is executed.

At that time, the CPU 12 determines that the current 4 × N MCUs are the first part of one band of image data (
If it is not the leftmost part), the process waits until the individual processing assigned to the CPU_X other than the previous CPU 12 is completed (steps S24 and S25). On the other hand, if the current 4 × N MCUs are the head part of one band of image data, the CPU 12 does not wait as such,
Immediately proceed to the next process.

Next, the CPU 12 determines the CP for JPEG decoding in the load distribution table 51.
CPU_X is a CPU whose processing ratio value other than U12 is other than 0,
The processing type, the MCU data for the processing ratio of the CPU_X, the DC component, and the output destination address of the calculation result (the address of the calculation result storage area in the external RAM 2) are written in the dual port RAM 21 (step S26).

For example, when the distribution ratio is 3: 1, data for 3 × N MCUs is stored in the CPU 1.
2, data for N MCUs is assigned to CPU_X.

Then, the CPU 12 interrupts the CPU_X, and the individual processing 63e corresponding to the processing ratio.
Is requested to CPU_X (step S27). The interrupt is performed by transmitting an interrupt signal via a control line that interconnects the CPUs 11 to 18. Further, the CPU_X that has received the interrupt indicates the MCU data corresponding to the processing rate of the CPU_X, the DC component thereof, and the output destination address of the calculation result according to the processing type stored in the predetermined area of the dual port RAM 21. Read from.

In this way, the CPU_X other than the CPU 12 is obtained by the processes in steps S24 to S27.
Distributed processing is given. On the other hand, if it is determined in step S23 that JPEG decoding is not distributed, the processes in steps S24 to S27 are skipped.

Then, in the case of distributed processing, the CPU 12 executes JPEG decoding individual processing 63a for MCUs corresponding to the processing ratio of 4 × N, and when not performing distributed processing, the CPU 12 executes JPEG for 4 × N MCUs. The individual decoding process 63a is executed (step S28). CP
When the U12 executes the JPEG decoding individual processing 63a, the function call causes JPE
A function or routine of the G decode individual processing 63a is called and executed. The MCU data for the processing ratio allocated to the CPU 12, its DC component, and the output destination address of the calculation result are temporarily stored in the dual port RAM 21 and / or the data RAM 33 of the CPU 12.
6 and used for the individual processing 63a.

In this way, decoding of JPEG data for 4 × N MCUs is executed. Then, the processes in steps S21 to S28 are repeated until the image data is completed (step S29).

FIG. 15 is a flowchart for explaining JPEG decoding individual processing 63a and 63e in the second embodiment. The JPEG individual decoding process 63a is executed by the CPU 12, and the JPEG individual decoding process 63e is executed by a CPU_X other than the CPU 12.
The CPU 12 executes a program 41s that includes a dedicated command, and the CPU_X executes a program 41g that does not include a dedicated command, but the processing flow of both is the same. However, the calculation speed is higher when dedicated instructions are used.

After storing the CPU timer value Ts at the start of the individual processing 63a (step S31), the CPU 12 decodes the JPEG data for the processing ratio based on the DC component (step S32), and when the decoding is completed, The CPU timer value Te at that time is detected (step S33), the difference (Te−Ts) between the two is used as the measurement time, and is added cumulatively to the total processing time data, and the decoded number of pixels is cumulatively added to the total processing pixel number data. (Step S34).
The total processing time data and the total processing pixel number data are data for totaling the time required for processing and the number of pixels for which processing has been completed. The initial values of these data are 0.

Then, the CPU 12 determines whether or not the current process is the last process in one band (step S35). For this determination, for example, the current individual processing 63a, 63e is 1
Data indicating whether or not this is the last process in the band is started together with other parameters.
What is necessary is just to make it determine by each separate process 63a, 63e based on the data set in a.

If the CPU 12 determines that the current process is the last process in one band, the total processing time data is JPEG processing time data, the total pixel number data is JPEG processing pixel number data, and the processing capability table 52 CPU12 for JPEG decoding
Is updated (step S36). At this time, as processing capability information, JP
A processing speed obtained by dividing the EG processing pixel number data by the JPEG processing time data is used.
After the update, the total processing time data and the total pixel number data, which are local data, are reset to 0 (step S37).

In addition, in this way, the processing capability information collected during the JPEG decoding individual processing 63a for the processing ratio of the image data for one band for each processing of one band, the JPEG in the processing capability table 52 The processing capacity information of the CPU 12 regarding the decoding is updated.

In the case of distributed processing, the CPU 12 and CPU_X execute the above-described processing. Therefore, in addition to the processing capability information of the CPU 12, in the case of distributed processing, JPEG decoding individual processing 63 for the processing ratio of image data for one band for each processing of one band.
The processing capability information of CPU_X for JPEG decoding in the processing capability table 52 is updated with the processing capability information collected during e.

As described above, in the JPEG decoding individual processing 63a and 63e, in addition to JPEG decoding corresponding to the processing ratio, the processing time and the number of processing pixels are totaled, and the processing capability table 52 for each band is updated.

As described above, according to the second embodiment, JPEG decoding start processing 62a and J
The individual PEG decoding processes 63a and 63e are executed efficiently.

Embodiment 3 FIG.
The image processing apparatus according to the third embodiment of the present invention has the same configuration and functions as the image processing apparatuses according to the other embodiments, and the image correction start process and the individual process are executed as follows. .

Also in the third embodiment, as shown in FIG.
3 is executed. In the image correction start process 62b, for each of the first process (tone adjustment and saturation enhancement), the second process (sharpness), and the third process (noise removal),
Whether or not to distribute is determined, and for each of the first to third processes, the image correction individual processes (63b, 63f) are assigned to one or two processing units.

In addition, when the image correction individual processing (63b, 63f) is executed by one processing unit, CP
When assigned to U13 and executed by two processing units, CPU13, CPU12,
The load distribution table 5 is connected to any one of the CPU 14 and the CPUs 15 to 18 (CPU_X).
Allocation is based on a distribution ratio of 1.

In the image correction start process 62b, the CPU 13 causes the image correction individual processes 63b and 63f to be executed for each line of image data in the order of the third process of image correction, the first process, and the second process.
Whether or not to execute the second process and the third process of image correction is determined according to a user setting. That is, for the x-th process (x = 1, 2, 3), it is determined whether or not the distributed process is performed line by line. Depending on the processing ratio, CPU 13 or CPU 13 and CPU_X 2 are determined.
Thus, the individual image correction process (63b, 63f) is executed.

FIG. 16 is a flowchart for explaining the image correction start processing 62b in the third embodiment. FIG. 17 is a flowchart for explaining one-line processing of the x-th processing (x = 1, 2, 3) in FIG.

First, the CPU 13 determines whether or not to execute the third process (noise removal) based on the user setting (step S41). When the third process is executed, the one-line process of the third process is performed. Is executed (step S42). On the other hand, if the third process (noise removal) is not executed, step S42 is skipped.

Next, the CPU 13 executes a one-line process of the first process (tone adjustment and saturation enhancement) (step S43).

Then, when the first process is completed, the CPU 13 performs the second process (
It is determined whether or not the one-line process of sharpness is to be executed (step S44). When the second process is executed, the one-line process of the second process is executed (step S45). On the other hand, if the second process (sharpness) is not executed, step S45 is skipped.

As described above, the image correction is performed on the image data after JPEG decoding one line at a time until the image correction is performed on all the image data.
The process of S45 is repeatedly executed (step S46).

Here, the one-line process of the x-th process in steps S42, S43, and S45 will be described with reference to FIG. The first process, the second process, and the third process are executed in the same procedure. However, the calculation performed on each pixel (step S62 described later) varies depending on the processing type.

In the one-line process of the x-th process, the CPU 13 first reads the value of the processing ratio of the CPU 13 for the x-th process of the image correction in the load distribution table 51, and determines whether the value is 1 or not. It is determined whether or not the correction is distributed by the two processing units (step S).
51). The CPU 13 determines that the distributed processing is not performed when the value of the processing ratio is 1, and determines that the distributed processing is performed when the value of the processing ratio is less than 1.

When it is determined that the x-th process of image correction is distributed by the two processing units, a process of giving the distributed process to the CPU_X other than the CPU 13 is executed.

At this time, the CPU 13 assigns a processing unit whose CPU 12 and 14 to 18 other than the CPU 13 with respect to the x-th process of image correction in the load distribution table 51 have a value other than 0 to the CPU.
_X, image data for one line to be processed is divided at a distribution ratio, and image data corresponding to each processing ratio is assigned to the CPU 13 and CPU_X (step S52).

For example, when the dispersion ratio is 3: 1, 3/4 of the number of horizontal pixels from the head of one line.
Are assigned to the CPU 13, and the remaining quarter of the pixel area is assigned to the CPU_X.

Then, the CPU 13 writes the start address (image data storage area address after JPEG decoding in the external RAM 2) corresponding to the processing type and the processing ratio of the CPU_X to the dual port RAM 21 (step S53).

Then, the CPU 13 interrupts the CPU_X and performs individual processing 63f corresponding to the processing ratio.
Is requested to CPU_X (step S54). The interrupt is performed by transmitting an interrupt signal via a control line that interconnects the CPUs 11 to 18. Further, the CPU_X that has received the interrupt sets the start address of the image data corresponding to the processing rate of the CPU_X to the dual port RA according to the processing type stored in a predetermined area of the dual port RAM 21.
Read from M21.

In this way, the CPU_X other than the CPU 13 is obtained by the processes in steps S52 to S54.
Distributed processing is given. On the other hand, if it is determined in step S51 that the image correction x-th process is not distributed, the processes in steps S52 to S54 are skipped.

Then, in the case of distributed processing, the CPU 13 executes the individual process 63b of the x-th process of image correction for the image data corresponding to the processing ratio of the image data for one line, and when not performing distributed processing, The individual process 63b of the x-th process of the image correction for the image data for one line is executed (step S55). When executing the individual process 63b, the CPU 13 calls and executes a function or routine of the individual process 63b by a function call.

The CPU 13 determines whether or not the current one-line process is distributed (step S5).
6) When the distributed processing is not performed, the one-line processing is ended when the individual processing 63b of the x-th processing of the image correction is completed. On the other hand, when the distributed processing is performed, the CPU 13 waits until the completion of the individual process 63f of the x-th process by the CPU_X after the completion of the individual process 63b of the x-th process of image correction (Step S57). When the individual process 63f of the x-th process is completed, the one-line process ends.

  In this way, the x-th process of image correction is executed on the image data for one line.

FIG. 18 is a flowchart for explaining the individual image correction processes 63b and 63f in the third embodiment. The image correction individual process 63b for the first process to the third process is executed by the CPU 13, and the image correction individual process 63f for the first process to the third process is executed by a CPU_X other than the CPU 13. The CPU 13 executes a program 42s that includes a dedicated instruction, and the CPU_X executes a program 42g that does not include a dedicated instruction, but the processing flow of both is the same. However, the calculation speed is higher when dedicated instructions are used.

After saving the CPU timer value Ts at the start of the individual process 63b (step S61), the CPU 13 specifies the image data to be processed based on the start address of the data to be processed, and image data corresponding to the processing ratio. The x-th processing is performed on each of the pixels (step S62).
When the calculation is completed, the CPU timer value Te at that time is detected (step S63).
The difference between them (Te−Ts) is taken as the measurement time.

Then, the CPU 13 sets the measurement time as the image correction processing time data for the x-th process, and sets the number of processed pixels as the image correction processing pixel number data for the x-th process. The processing capability information of the CPU 13 regarding the processing is updated (step S64). At this time, as the processing capability information, a processing speed obtained by dividing the image correction processing pixel number data by the image correction processing time data is used.

By doing so, the processing capability information collected during the image correction individual processing 63b for the processing ratio of the image data for one line for each processing of one line, the image correction in the processing capability table 52 is performed. The processing capability information of the CPU 13 is updated.

In the case of distributed processing, the CPU 13 and CPU_X execute the above-described processing. Therefore, in addition to the processing capability information of the CPU 13, in the case of distributed processing, processing capability information collected during the image correction individual processing 63f for the processing ratio of image data for one line for each processing of one line. CPU__ for image correction in the processing capacity table 52
The processing capacity information of X is updated.

As described above, in the image correction individual processing (63b, 63f) for the x-th processing, in addition to the x-th processing corresponding to the processing ratio, the processing time and the number of processing pixels are measured, and the processing capacity table 52 is updated for each line. Is done.

As described above, according to the third embodiment, the image correction start process 62b and the image correction individual processes 63b and 63f are efficiently executed.

Embodiment 4 FIG.
The image processing apparatus according to the fourth embodiment of the present invention has the same configuration and functions as the image processing apparatuses according to the other embodiments, and includes color conversion and halftone start processes 62c and 62d and individual processes 63c, The steps 63g, 63d, and 63h are executed as follows.

Also in the fourth embodiment, as shown in FIG. 7, the color conversion start processing 62 c is performed by the CPU 14.
It is executed by. The color conversion individual processing (63c, 63g) is assigned to one or two processing units.

The color conversion individual processing (63c, 63g) is executed by a CPU when executed by one processing unit.
14, the CPU 14 and the CPU 12, C
The load distribution table 51 is connected to any one of the PU 13 and the CPUs 15 to 18 (CPU_X).
Assigned based on the distribution ratio.

Further, in the fourth embodiment, the halftone start process 62d is executed by the CPU 14 in the color conversion start process 62c. Halftone individual processing (63d, 63h) is 1
Alternatively, it is assigned to the second processing unit.

The halftone individual processing (63d, 63h) is assigned to 4 CPUs 15 to 18 when executed by one processing unit, and the CPU is executed when executed by two processing units.
15 to 18 and any of CPUs 12 to 14 (CPU_X) are allocated to a total of 5 CPUs based on the distribution ratio of the load distribution table 51.

FIG. 19 is a flowchart for explaining the color conversion start processing 62c in the fourth embodiment.

In the color conversion start process 62c, the CPU 14 reads the value of the processing ratio of the CPU 14 for the color conversion in the load distribution table 51, and distributes the color conversion by the two processing units based on whether or not the value is 1. It is determined whether or not to process (step S71). CPU1
4 determines that distributed processing is not performed when the value of the processing ratio is 1, and determines that distributed processing is performed when the value of the processing ratio is less than 1.

When it is determined that the color conversion is distributed by the two processing units, a process of giving the distributed process to the CPU_X other than the CPU 14 is executed.

At that time, the CPU 14 sets CPU_X as the CPU_X that has a processing ratio value other than 0 for the CPUs 12, 13, 15 to 18 other than the CPU 14 for color conversion in the load distribution table 51, and image data for one block to be processed. Are divided by the distribution ratio, and image data corresponding to each processing ratio is allocated to the CPU 14 and CPU_X (step S72).

In addition, the block to be processed per process in the color conversion is 2 pixels vertically and horizontally (
4 × M) pixel area. In the fourth embodiment, M = 64.

For example, if the distribution ratio is 3: 1, 3 × from the beginning of each line in the block
M pixel regions (that is, a total of 6 × M pixels) are allocated to the CPU 14 and the remaining 2 ×
M pixel regions are assigned to CPU_X.

Then, the CPU 14 writes the start address of the image data corresponding to the processing type and the processing ratio of CPU_X (the address of the storage area of the image data after resizing / laying out of the external RAM 2) in the dual port RAM 22 (step S73).

Then, the CPU 14 interrupts the CPU_X and performs individual processing 63g corresponding to the processing ratio.
Is requested to CPU_X (step S74). The interrupt is performed by transmitting an interrupt signal via a control line that interconnects the CPUs 11 to 18. Further, the CPU_X that has received the interrupt sets the start address of the image data corresponding to the processing rate of the CPU_X to the dual port RA according to the processing type stored in the predetermined area of the dual port RAM 22.
Read from M22.

In this way, the CPU_X other than the CPU 14 is obtained by the processes in steps S72 to S74.
Distributed processing is given. On the other hand, if it is determined in step S71 that the color conversion is not distributed, the processes in steps S72 to S74 are skipped.

In the case of distributed processing, the CPU 14 executes the color conversion individual processing 63c for the image data corresponding to the processing ratio in the image data for one block, and in the case of not performing the distributed processing, the CPU 14 An individual color conversion process 63c for the image data is executed (step S).
75). When executing the individual process 63c, the CPU 14 uses the function call to execute the individual process 6c.
3c functions and routines are called and executed.

When the individual processing 63c corresponding to the processing ratio is completed, the CPU 14 executes a halftone start process (step S76). As a result, halftone processing is executed on the image data after the individual processing 63c performed by the CPU 14 as described later.

When the color conversion and the halftone are completed for the image data corresponding to the processing ratio, the CPU 14 determines whether or not the color conversion processing is distributed (step S77). When the color conversion process is distributed, the CPU 14 waits until the individual color conversion process 63g by the CPU_X is completed (step S78), and when the individual color conversion process 63g by the CPU_X is completed, the CPU 14 processes the processing ratio. Halftone start processing is executed for the image data after color conversion (step S79).

On the other hand, if the color conversion process is not distributed, steps S78 and S79 are skipped because color conversion and halftone for one block have been completed.

In this way, color conversion and halftone for one block are executed. Then, the process returns to step S71, and color conversion and halftone for the next one block are executed in the same manner. Thereafter, color conversion and halftone are sequentially performed until the end of the image data (
Step S80).

In relation to the color conversion start process described above, first, the color conversion individual processes 63c and 63g will be described. FIG. 20 is a flowchart illustrating color conversion individual processing 63c and 63g according to the fourth embodiment. The color conversion individual process 63c is executed by the CPU 14, and the color conversion individual process 63g is executed by a CPU_X other than the CPU 14. The CPU 14 executes a program 43s that includes a dedicated instruction, and the CPU_X executes a program 43g that does not include a dedicated instruction, but the processing flow of both is the same. However, the calculation speed is higher when dedicated instructions are used. Note that the LUT used for color conversion is a plurality of LUTs stored in a nonvolatile memory (not shown) based on the parameter values stored in the dual port RAM 21.
Selected from.

After storing the CPU timer value Ts at the start of the individual process 63c (step S81), the CPU 14 specifies the image data to be processed based on the start address of the data to be processed, and image data corresponding to the processing ratio. Color conversion is performed on each of the pixels (step S82), and when the calculation is completed, the value Te of the CPU timer at that time is detected (step S83), and the difference (Te−Ts) between the two is used as the measurement time. Cumulative addition is made to the total processing time data, and the decoded number of pixels is cumulatively added to the total processing pixel number data (step S84). The total processing time data and the total processing pixel number data are data for totaling the time required for processing and the number of pixels for which processing has been completed. The initial values of these data are 0.

In the fourth embodiment, RGB data is converted into CYMK data for seven colors for seven color inks.

Then, the CPU 14 determines whether or not the current process is the last process in one band (step S85). For this determination, for example, data indicating whether or not the current individual process is the last process in one band is set in the start process 62c together with other parameters, and the individual processes 63c and 63g are set based on the data. It may be determined.

If the CPU 14 determines that the current process is the last process in one band, the total processing time data is used as color conversion processing time data, and the total pixel number data is used as color conversion processing pixel number data. The processing capability information of the CPU 14 regarding color conversion in the table 52 is updated (step S86). At this time, as the processing capability information, a processing speed obtained by dividing the color conversion processing pixel number data by the color conversion processing time data is used. After the update, the total processing time data and the total pixel number data, which are local data, are reset to 0 (step S87).

In addition, in this way, the color in the processing capability table 52 is obtained by the processing capability information collected during the color conversion individual processing 63c for the processing rate of the image data for one band for each processing of one band. The processing capability information of the CPU 14 regarding the conversion is updated.

In the case of distributed processing, the CPU 14 and CPU_X execute the above-described processing. Accordingly, in addition to the processing capability information of the CPU 14, in the case of distributed processing, processing capability information collected during the color conversion individual processing 63g for the processing ratio of image data for one band for each processing of one band. Thus, the CPU_X processing capability information for color conversion in the processing capability table 52 is updated.

As described above, in the color conversion individual processing (63c, 63g), in addition to the color conversion corresponding to the processing ratio, the processing time and the number of processing pixels are totaled, and the processing capability table 52 for each band is updated.

Next, the halftone start process 62d will be described in relation to the above color conversion start process. As described above, the halftone start process 62d is immediately executed by the CPU 14 after the color conversion by the CPU 14 or CPU_X is completed.

FIG. 21 is a flowchart for explaining halftone start processing 62d in the fourth embodiment.

In the halftone start process 62d, the CPU 14 separates the color-converted image data by color and writes it into the dual port RAM 22 (step S91). At this time, the data of each color is a block of 2 × 256 pixels.

Next, the CPU 14 determines the CPU 1 for the halftone in the load distribution table 51.
A processing ratio value of 5 to 18 is read out, and based on whether the value is 1 or not, it is determined whether or not to distribute the halftone with 5 CPUs (step S92). CPU 14
Determines that distributed processing is not performed when the value of the processing ratio is 1, and determines that distributed processing is performed when the value of the processing ratio is less than 1.

When it is determined that the halftone is to be distributed by five CPUs, a process of giving the distributed processing to the CPUs 15 to 18 and the CPU_X other than the CPUs 15 to 18 is executed.

At that time, the CPU 14 performs CPU for halftone in the load distribution table 51.
A CPU whose processing ratio value other than 15 to 18 is other than 0 is CPU_X, image data for one block to be processed is divided by a distribution ratio, and image data corresponding to each processing ratio is obtained. It assigns to CPU15-18 and CPU_X (step S92).

Note that the block to be processed per process in halftone is the same pixel area as color conversion.

Then, the CPU 14 interrupts the CPU_X and performs individual processing 63h corresponding to the processing ratio.
Is requested to CPU_X (step S94). The interrupt is performed by transmitting an interrupt signal via a control line that interconnects the CPUs 11 to 18. Further, the CPU_X that has received the interrupt sets the start address of the image data corresponding to the processing rate of the CPU_X to the dual port RA according to the processing type stored in the predetermined area of the dual port RAM 22.
Read from M22.

On the other hand, if it is determined in step S91 that the halftone is not distributed by the five CPUs, the process of step S73 is skipped.

Then, the CPU 14 interrupts each of the CPUs 15 to 18 and requests the CPUs 15 to 18 for individual processing 63d corresponding to the processing ratio (step S95). The CPUs 15 to 18 that have received the interrupt read from the dual port RAM 22 the start addresses of the image data corresponding to the processing ratios of the CPUs 15 to 18 in accordance with the processing types stored in a predetermined area of the dual port RAM 22.

In this way, the distributed processing is given to the CPUs 15 to 18 or the distributed processing is given to the CPU_X other than the CPUs 15 to 18 by the processes of steps S93 and S94.

Thereafter, the CPU 14 stands by until the halftone individual processing 63d by the CPUs 15 to 18 is completed (step S95). Then, when the halftone individual processing 63d by the CPUs 15 to 18 is finished, when the five CPUs are performing distributed processing, the CPU 14
The CPU waits until the halftone individual process 63h by the CPU_X is finished, and when the individual process 63h is finished, the halftone start process is finished. On the other hand, when the distributed processing is not performed by the five CPUs, when the halftone individual processing 63d by the CPUs 15 to 18 ends, CP
U14 ends the halftone start process.

  In this way, the allocation process of the halftone individual process is executed.

Here, the details of the halftone individual processing 63d and 63h will be described. FIG. 22 is a flowchart illustrating the halftone individual processing 63d and 63h according to the fourth embodiment. Halftone is distributed and processed in units of data of each color after color conversion. The halftone individual processing 63d is distributed by one color or two colors and is executed in parallel by the CPUs 15 to 18, and the halftone individual processing 63h is executed by a CPU_X other than the CPUs 15 to 18. The CPUs 15 to 18 execute a program 44s including a dedicated instruction, and CPU_X
Executes a program 44g that does not include a dedicated instruction, but the flow of both processes is the same. However, the calculation speed is higher when dedicated instructions are used.

The CPUs 15 to 18 store the value Ts of the CPU timer at the start of the individual process 63d (
Step S101), image data corresponding to the processing rate of the color assigned in advance is read from the dual port RAM 22, and binarization processing is executed on the image data by the dither method or error diffusion method (Step S102). When the calculation is completed, the CPU timer value Te at that time is detected (step S103), the difference between the two (Te-Ts) is added to the total processing time data as a measurement time, and the number of decoded pixels is totaled. Cumulative addition is performed on the pixel number data (step S104). The total processing time data and the total processing pixel number data are
This is data for counting the time required for processing and the number of pixels for which processing has been completed. The initial values of these data are 0.

In the fourth embodiment, CMYK data (C, M, Y, K, R, B, C) for seven colors is used.
L) exists and halftone is executed only by the four CPUs 15 to 18, for example, C
The PU 15 performs binarization of cyan C and magenta M by the error diffusion method, and the CPU 16
Executes binarization of yellow Y by the dither method and binarization of black K by the error diffusion method, and the CPU 17 binarizes the clear CL by the dither method and binarization of the red R by the error diffusion method. The CPU 18 executes binarization of blue B by the error diffusion method. CP
When halftone is executed by five CPUs U15 to 18 and CPU_X, for example, CP
U15 executes binarization of cyan C by the error diffusion method, CPU 16 executes binarization of yellow Y by the dither method and binarization of black K by the error diffusion method, and CPU 17 performs the binarization by the dither method. Executes binarization of clear CL and binarization of red R by error diffusion method, CPU
18 executes binarization of blue B by the error diffusion method, and CPU_X executes binarization of magenta M by the error diffusion method.

And CPU15-18 determines whether this process is the last process in 1 band (step S105). For this determination, for example, data indicating whether or not the current individual process is the last process in one band is set in the start process 62d together with other parameters, and the individual processes 63d and 63h are based on the data. It may be determined.

When the CPUs 15 to 18 determine that the current process is the last process in one band, the total processing time data is set as the HT processing time data, and the total pixel number data is set as the HT processing pixel number data. CPU 15-18 for halftone in table 52
Is updated (step S106). At this time, as processing capability information, H
A processing speed obtained by dividing the T pixel number data by the HT processing time data is used. After the update, the total processing time data and the total pixel number data, which are local data, are reset to 0 (step S107).

Further, in this way, for each processing of one band, the processing capability information collected during the halftone individual processing 63d for the processing ratio of the image data for one band, the half in the processing capability table 52 The processing capability information of the CPUs 15 to 18 for the tone is updated.

Note that in the case of distributed processing, the CPUs 15 to 18 and the CPU_X execute the above-described processing. Therefore, in addition to the processing capability information of the CPUs 15 to 18, in the case of distributed processing, 1
For each band process, the CPU_X processing capability information for the halftone in the processing capability table 52 is updated with the processing capability information collected during the halftone individual processing 63h for the processing rate of the image data for one band. Is done.

As described above, in the halftone individual processing (63d, 63h), in addition to the halftone for the processing ratio, the processing time and the number of processing pixels are counted, and the processing capability table 52 for each band.
Is updated.

As described above, according to the fourth embodiment, the color conversion start process 62c and the individual color conversion processes 63c and 63g are efficiently executed, and the halftone process applied to the color-converted image data for each color. Halftone start processing 62d and halftone individual processing 63d, 6
3h is executed efficiently.

Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

For example, in Embodiments 1 to 4, the image data prepared first is encoded in the JPEG format, but may be encoded in another format instead. In that case, decoding in that format is executed instead of JPEG decoding.

In the first to fourth embodiments, the CPUs 15 to 18 are load-managed as a single processor. Instead, each of the four CPUs 15 to 18 is replaced with another CPU 12.
Similarly to -14, load management may be executed to maintain the load balance.

In the first to fourth embodiments, when individual processing other than halftone, such as JPEG decoding, image correction, and color conversion, is given to the CPUs 15 to 18, processing is performed by other CPUs among the CPUs 15 to 18. What is necessary is just to give individual processing other than the halftone to the CPU having a small number of colors.

In the first to fourth embodiments, seven colors of CYMK image data are generated by color conversion. However, the number of colors of image data after color conversion may be other numbers. For example, CYMK image data of four colors, six colors, eight colors, etc. may be generated by color conversion. In this case, the number of CPUs having a halftone dedicated instruction calculation unit is equal to or less than the number of colors. Further, the color coordinates after color conversion are not limited to those described above, and may be different color coordinates.

In the first to fourth embodiments, the first process to the third process of image correction are separately distributed. However, the first process to the third process are not distinguished and distributed as one image correction process. You may make it make it.

In the first to fourth embodiments, during distributed processing, processing of one processing type is different from the main CPU (that is, a CPU having a dedicated instruction calculation unit corresponding to the processing type).
It is executed by one CPU_X, but may be executed by the main CPU and two or more other CPUs. In that case, the processing ratio of the load distribution table 51 is at least 3
It is a non-zero value for one processing unit.

In the first to fourth embodiments, the CPU 14 (and CPU_X) that performs color conversion.
For example, the method of Japanese Patent Application No. 2004-096845 previously proposed by the present applicant may be applied to the transfer of data from the CPU to the CPUs 15 to 18 (and CPU_X) executing halftone.

In the first to fourth embodiments, the resizing / layout process is performed by the CPU 12 without performing the distributed process. However, the distributed process may be performed in the same manner as other processing types.

In the first to fourth embodiments, the number of arithmetic units such as built-in adders and multipliers may be changed for each CPU in the general-purpose instruction arithmetic units 12a to 18a.

In the first to fourth embodiments, the programs 41s to 44s including the dedicated instructions and the programs 41g to 44g including the general-purpose instructions are loaded into the external RAM 2. However, the programs 41s to 44s including the dedicated instructions are loaded on each CPU 12 to 18 programs may be loaded into the external RAM 2 and the programs 41g to 44g including general-purpose commands may be loaded into the external RAM 2.

In the first to fourth embodiments, the processing ratio for JPEG decoding, image correction, and color conversion is one of a set of 0, 0.25, 0.5, 0.75, and 1. Or any other set of numbers. For example, the processing ratio is 0, 0.12.
Any of the set of 5, 0.25, 0.375, 0.5, 0.625, 0.75, 0.875, and 1 may be used. Also, the processing ratio for halftone may be any other value.

In the first to fourth embodiments, the distribution ratio determination process 61 and the start process 62 are executed by a part of the CPUs 12 to 18 that execute the individual process 63. Instead, the distribution ratio determination process 61 and Start processing 62 is performed by another CPU (for example, CPU 11, CP provided separately)
U) or the like.

In the first to fourth embodiments, there are two load distribution tables 51, one load distribution table 51 is referred to in the start process 62, and the other load distribution table 51 is updated in one distribution ratio determination process 61. When the update is completed, the load distribution table 51 referred to in the start process 62 may be the other updated load distribution table 51. As a result, the two load distribution tables 51 are alternately updated, and the load distribution table 51 is updated.
Even during the update, the load distribution table 51 is referred to smoothly in the start process 62.

In the first to fourth embodiments, the present invention is applied to an image processing system that executes in the order of JPEG decoding, image correction, resizing / layout, color conversion, and halftone. However, the present invention is not limited to this, and the present invention can also be applied to other image processing systems that sequentially execute a plurality of types of image processing.

The present invention is applicable to, for example, an image processing apparatus that sequentially performs a plurality of image processes on image data. Examples of such an image processing apparatus include a printer, a copier, a projector, and a television receiver.

1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. It is a block diagram which shows the detailed structure of CPU12 in FIG. It is a block diagram which shows the program for CPU11-18 in FIG. 3 is a flowchart for describing a series of image processing in the first embodiment. 3 is a block diagram illustrating a data flow in Embodiment 1. FIG. It is a figure which shows an example of the data flow etc. when not performing distributed processing. 3 is a block diagram for explaining distributed processing in Embodiment 1. FIG. 6 is a diagram showing an example of a processing capacity table in the first embodiment. FIG. 6 is a diagram illustrating an example of a load distribution table according to Embodiment 1. FIG. 5 is a flowchart for explaining a distribution ratio determination process in the first embodiment. It is a flowchart explaining the load distribution table update process in FIG. It is a figure which shows the load distribution table in the middle of the update of the load distribution table of FIG. It is a figure which shows the load distribution table which updated the load distribution table of FIG. FIG. 10 is a diagram for describing JPEG decoding start processing in the second embodiment. FIG. 10 is a diagram for explaining JPEG decoding individual processing in the second embodiment. 14 is a flowchart for describing image correction start processing in the third embodiment. It is a flowchart explaining 1 line process of the x-th process in FIG. 10 is a flowchart for explaining individual image correction processing according to the third embodiment. 15 is a flowchart for describing color conversion start processing in the fourth embodiment. 14 is a flowchart for explaining individual color conversion processing according to the fourth embodiment. FIG. 10 is a diagram for explaining halftone start processing in the fourth embodiment. FIG. 10 is a diagram for explaining halftone individual processing in a fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ASIC (processor), 4 Printer drive part (printing means), 12 CPU (a part of several processing part, distribution ratio update means, start process means, processing capacity table update means), 13
, 14 CPU (part of a plurality of processing units, start processing means, processing capacity table updating means), 1
5-18 CPU (part of a plurality of processing units, processing capacity table updating means), 51 load distribution table, 52a processing capacity table (default processing capacity table), 52b processing capacity table.

Claims (7)

In an image processing apparatus that sequentially performs multiple types of image processing on image data in the same region,
A plurality of processing units for sequentially performing the plurality of types of image processing on the image data of the same region;
A load distribution table having a distribution ratio to one or a plurality of processing units related to various types of image processing;
A distribution ratio updating means for calculating a distribution ratio of each image processing after the start of image processing and updating the distribution ratio in the load distribution table;
For the distribution ratio that has never been updated by the distribution ratio update means, the default distribution ratio is used, and at least one type of image processing is processed with 2 images.
Start processing means for distributing and executing each of the above processing units;
An image processing apparatus comprising: A processing capacity table for storing the processing power values of the plurality of processing units;
A default processing capacity table storing a default value of each processing capacity value of the plurality of processing units;
A processing capability table updating means for updating a processing capability value of the processing capability table based on a processing time for a predetermined amount of image data by each of the plurality of processing units;
The distribution ratio update means preferentially refers to the processing capacity table, calculates a distribution ratio of each image processing based on the processing capacity table and the default processing capacity table, and sets the distribution ratio in the load distribution table;
The image processing apparatus according to claim 1. The processing capacity table update unit is realized by executing a program by the processing unit, and updates a processing capacity value based on a processing time and a processing pixel number for each line or band. 2. The image processing apparatus according to 2. The image processing apparatus according to claim 2, wherein the processing capability table has a processing capability value for each of the plurality of types of image processing for each of the plurality of processing units. The dispersion ratio updating means sets the dispersion ratio again when the image processing of the type with the latest processing time for one line or one band among the plurality of types is completed after setting the dispersion ratio. The image processing apparatus according to claim 1, wherein the image processing apparatus is characterized in that: The image processing apparatus according to claim 1, wherein at least color conversion and halftone are executed as a plurality of processes.
Printing means for printing an image based on image data processed by the image processing apparatus;
A printing apparatus comprising: In a load distribution method in an image processing apparatus that sequentially performs a plurality of types of image processing on image data in the same region by a plurality of processing units,
A load distribution table having a distribution ratio for each processing type of the image processing is calculated after the start of the image processing to a plurality of processing units that sequentially perform the plurality of types of image processing on the image data in the same region. A step of updating at a distribution ratio of each image processing;
A step of using the default distribution ratio for a distribution ratio that has never been updated in the load distribution table and distributing the image processing to two or more processing units for at least one type of image processing. When,
A load balancing method comprising:

Images