JP2006163426A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To input a video signal normally by compensating variation in duty ratio of a clock signal inputted to a liquid crystal driving circuit. <P>SOLUTION: A clock compensating circuit 200 generates an internal clock signal of 50% in duty ratio based upon a latch clock signal for display data inputted from outside. Display data sent out of a data input/arithmetic circuit 133 are latched by a latch circuit 135 one after another and outputted to the outside through a data output circuit 134. The data input/arithmetic circuit 133 inputs 1st and 2nd data when the clock signal rises and falls, and sends out the 1st data out to one internal bus line and the 2nd data to the other internal bus line in response to an AC-converted signal. A positive-polarity side circuit which supplies a gradation voltage with the positive polarity is connected to the 1st internal bus line and a negative-polarity side circuit which supplies a gradation voltage with the negative polarity is connected to the 2nd bus line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device, and more particularly, to a technique effective when applied to a drive circuit of a liquid crystal display device that transfers digital signals between drive circuits (drain drivers).

LCD module STN (S uper T wisted N ematic ) method or TFT (T hin F ilm T ransister ), is widely used as a display device such as a notebook personal computer.
These liquid crystal display devices include a liquid crystal display panel and a drive circuit that drives the liquid crystal display panel.
In such a liquid crystal display device, as described in, for example, Patent Document 1 below, only a digital signal (for example, display data or a clock signal) is applied only to the head drive circuit of the cascade-connected drive circuits. ) And other drive circuits are known which sequentially transfer digital signals through the drive circuit (hereinafter referred to as digital signal sequential transfer method).
In the liquid crystal display device described in Patent Document 1 below, a semiconductor integrated circuit device (IC) constituting a drive circuit is directly mounted on a glass substrate of a liquid crystal display panel. As described, there is also known a liquid crystal display device in which a semiconductor integrated circuit device (IC) constituting the drive circuit is mounted on a tape carrier package and adopts the digital signal sequential transfer method described above.
Further, in a digital signal sequential transfer type drive circuit, the following Non-Patent Document 1 is known as a known document in which the polarity of a signal is inverted and transferred to the next stage drive circuit in order to cancel the duty ratio fluctuation of the signal. However, none of the known techniques describe a clock compensation circuit that aligns the rising timing and falling timing of the clock signal.

As prior art documents related to the invention of the present application, there are the following.
JP-A-6-13724 Japanese Patent Laid-Open No. 6-3684 Sharp Technical Journal, 74th (August 1999), 31-34

As shown in FIG. 32A, in the case of the dual edge capture method in which the display data is captured at the rise time and the fall time of the display data capture clock signal, there is a margin in the setup period and the hold period. In order to have this, it is necessary that the rising time point and the falling time point of the clock signal are located at the intermediate time point when the display data is switched.
However, in the liquid crystal display device adopting the digital signal sequential transfer system as described above, the display data and the clock signal sent from the timing controller (or the display control device) are the signal lines in each drive circuit and each drive. It propagates along the transmission line between the circuits (transmission line on the glass substrate or transmission line on the tape carrier package).
That is, the display data and the clock signal sent from the timing controller are passed between the drain drivers.

For this reason, the duty ratio of the clock signal (that is, the period of the pulse signal) depends on the internal characteristics of each drain driver, for example, the fluctuation of the threshold value (Vth) of each MOS transistor in the CMOS inverter circuit, or some factor on the transmission line. The ratio of the high level period to the fluctuation of the duty ratio may vary, and the fluctuation of the duty ratio may be accumulated due to a plurality of transfers.
When the variation in the duty ratio of the clock signal increases and the phase difference from the display data increases, the setup period or hold period when the display data is captured by the clock signal decreases as shown in FIG. In the worst case, however, display data may not be captured by each drive circuit, and an erroneous display occurs on the liquid crystal display panel, resulting in a significant deterioration in display quality.
The problem described above becomes more conspicuous in the case of the method of capturing the display data at both edges of the clock signal, but the method of capturing the display data at one edge of the clock signal is no exception.

The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to compensate for variations in the duty ratio of a clock signal input to a liquid crystal driving circuit in a liquid crystal display device. It is to provide a technology that makes it possible.
Another object of the present invention is to provide a technique capable of improving the display quality of a liquid crystal display element by enabling normal capture of a video signal in a liquid crystal display device.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the present invention is a liquid crystal display device including a liquid crystal display element and a liquid crystal driving circuit, wherein the liquid crystal driving circuit switches the internal clock signal from the first level to the second level, or the second level. The video signal input to the liquid crystal driving circuit is taken into the bus at the timing of switching from the first level to the first level, the voltage for driving the liquid crystal display element is selected from the video signal taken into the bus, and the internal clock The signal is a clock signal in which the first level period and the second level period of the external clock signal input to the liquid crystal driving circuit are each set to a predetermined value by the clock compensation circuit.

  The present invention is also a liquid crystal display device comprising a liquid crystal display element and a liquid crystal drive circuit, wherein the liquid crystal drive circuit receives a video signal input to the liquid crystal drive circuit at the timing of switching of an internal clock signal. A voltage for driving the liquid crystal display element is selected from the video signal captured by the bus, and the internal clock signal is based on an external clock signal input to the liquid crystal driving circuit, a phase-locked loop circuit, Alternatively, the clock signal is generated using a delay locked loop circuit.

  The present invention is also a liquid crystal display device including a liquid crystal display element and a liquid crystal drive circuit, wherein the liquid crystal drive circuit is configured to switch the internal clock signal from the first level to the second level, and from the second level. At the timing of switching to the first level, the video signal input to the liquid crystal driving circuit is taken into an internal circuit, a voltage for driving the liquid crystal display element is selected from the video signal taken into the internal circuit, and the internal signal is selected. The clock signal is a clock signal in which the first level period and the second level period of the external clock signal input to the liquid crystal driving circuit are set to a predetermined value by the clock compensation circuit.

  The present invention is also a liquid crystal display device including a liquid crystal display element and a liquid crystal drive circuit, wherein the liquid crystal drive circuit is configured to switch the internal clock signal from the first level to the second level, and from the second level. At the timing of switching to the first level, the video signal input to the liquid crystal driving circuit is taken into two buses, and the voltage for driving the liquid crystal display element is selected from the video signals taken into the two buses The internal clock signal is a clock signal in which the first level period and the second level period of the external clock signal input to the liquid crystal driving circuit are set to predetermined values by a clock compensation circuit. And

  The present invention is also a liquid crystal display device including a liquid crystal display element and a liquid crystal drive circuit, wherein the liquid crystal drive circuit is configured to switch the internal clock signal from the first level to the second level, and from the second level. At the timing of switching to the first level, the video signal input to the liquid crystal driving circuit is taken into two buses, and the voltage for driving the liquid crystal display element is selected from the video signals taken into the two buses The internal clock signal is a clock signal generated using a phase-locked loop circuit or a delay-locked loop circuit based on an external clock signal input to the liquid crystal driving circuit.

  According to another aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal display element, a first liquid crystal driving circuit, and a second liquid crystal driving circuit, wherein the first and second liquid crystal driving circuits have a first internal clock signal. At the timing of switching to the first level or the second level, the video signal inputted to the liquid crystal driving circuit is taken into the bus, and the voltage for driving the liquid crystal display element is selected from the video signal taken into the bus, The first liquid crystal driving circuit includes an output circuit that outputs the input video signal and the internal clock signal to the second liquid crystal driving circuit, and the internal clock signal is generated by a clock compensation circuit. The first and second level periods of the external clock signal input to the liquid crystal driving circuit are clock signals each having a predetermined value.

The present invention is also a liquid crystal display device including a liquid crystal display element, a first liquid crystal drive circuit, and a second liquid crystal drive circuit, wherein the first and second liquid crystal drive circuits are included in the liquid crystal drive circuit. The video signal input to the liquid crystal driving circuit is taken into the bus at the timing of switching to the first level or the second level of the input external clock signal, and the liquid crystal display element is obtained from the video signal taken into the bus. The first liquid crystal driving circuit has an output circuit for outputting the input video signal and an internal clock signal to the second liquid crystal driving circuit, and the internal clock The signal is a clock signal in which the first level period and the second level period of the external clock signal input to the liquid crystal driving circuit are set to predetermined values by the clock compensation circuit. And it features.
In a preferred embodiment of the present invention, the clock compensation circuit includes a phase locked loop circuit or a delay locked loop circuit.

The present invention is also a liquid crystal display device comprising a liquid crystal display element, a first liquid crystal drive circuit, and a second liquid crystal drive circuit, wherein the first liquid crystal drive circuit and the second liquid crystal drive circuit are: At the timing of switching the internal clock signal from the first level to the second level and switching from the second level to the first level, the video signals input to the respective liquid crystal drive circuits are taken into two buses, A voltage for driving the liquid crystal display element is selected from the video signals taken into the two buses, and the first liquid crystal driving circuit and the second liquid crystal driving circuit are inputted to the liquid crystal driving circuits from the outside. Output to the next stage liquid crystal drive circuit through cascaded inverter circuits, and the number of inverters is in the transmission path from the clock signal input terminal to the clock signal output terminal. Wherein the logic inversion number of the clock signal by the circuit elements is set to be an odd number of times.
In a preferred embodiment of the present invention, the clock signal output circuit and the video signal output circuit of the first liquid crystal driving circuit are supplied with power from different power sources.

The present invention is also a liquid crystal display device comprising a liquid crystal display element, a first liquid crystal drive circuit, and a second liquid crystal drive circuit, wherein the first liquid crystal drive circuit and the second liquid crystal drive circuit are: The video signal input to each of the liquid crystal driving circuits is taken into the bus at at least one timing of switching from the first level to the second level of the internal clock signal or from the second level to the first level, A voltage for driving the liquid crystal display element is selected from the video signal taken into the bus, and the first liquid crystal driving circuit and the second liquid crystal driving circuit receive a first clock signal input to each of the liquid crystal driving circuits. A first clock signal system that captures the first clock signal, and a second clock signal system that captures the second clock signal obtained by inverting the first clock signal, and the first liquid crystal driving circuit. , A clock signal obtained by inverting said first clock signal, and supplying the second clock signal line of the second liquid crystal driving circuit.
In a preferred embodiment of the present invention, the first liquid crystal driving circuit supplies a clock signal obtained by inverting the second clock signal to the first clock signal system.

According to the means, in each liquid crystal driving circuit, the internal clock signal in which the first level period and the second level period of the external clock signal input to the liquid crystal driving circuit are set to predetermined values by the clock compensation circuit, respectively. Thus, it is possible to compensate for the variation in the duty ratio of the clock signal input from the outside.
As a result, display data can be accurately taken in by each liquid crystal driving circuit, so that the display quality of the liquid crystal display element can be improved.
Here, the clock compensation circuit described above is configured using a phase locked loop circuit or a delay locked loop circuit.
Furthermore, since the internal clock signal is output to the next stage liquid crystal drive circuit, the duty ratio of the clock signal is higher than when the externally input clock signal is output directly to the next stage liquid crystal drive circuit. It is possible to suppress fluctuations in

According to the above means, each liquid crystal driving circuit takes in the first clock signal and the second clock signal obtained by inverting the first clock signal, and the first clock signal is used as the next stage liquid crystal driving circuit. Since the second clock signal is supplied to the first clock signal system of the next stage liquid crystal driving circuit, the duty ratio of the clock signal input from the outside is changed. It becomes possible to compensate.
As a result, display data can be accurately taken in by each liquid crystal driving circuit, so that the display quality of the liquid crystal display element can be improved.
Further, since the power supply for the display data transfer circuit and the power supply for the clock signal transfer circuit are separated, the influence of the display data transfer circuit on the clock signal transfer circuit can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the liquid crystal display device of the present invention, the display data is transferred using the data bus in the liquid crystal driver IC. Therefore, the wiring of the printed circuit board for sending the display data to each liquid crystal driver IC in parallel is provided. It becomes unnecessary and the peripheral circuit area of the liquid crystal display device can be reduced.
(2) According to the liquid crystal display device of the present invention, it is possible to compensate for variations in the duty ratio of the clock signal input to the liquid crystal driving circuit.
(3) According to the liquid crystal display device of the present invention, it is possible to prevent erroneous display from occurring in the image displayed on the liquid crystal display element, so that the display quality of the image displayed on the liquid crystal display element can be improved. Become.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example 1]
FIG. 1 is a block diagram showing a basic configuration of a display panel of a liquid crystal display module according to Embodiment 1 of the present invention.
As shown in the figure, the liquid crystal display module of this embodiment includes a liquid crystal display panel 100, a timing controller 110, a power supply circuit 120, a drain driver 130, a gate driver 140, a flexible printed circuit board (hereinafter referred to as FPC). (Referred to as a substrate).
The liquid crystal display panel 100 includes a pixel substrate PIX, a TFT substrate on which a thin film transistor TFT and the like are formed, and a filter substrate on which a counter electrode and a color filter are formed with a predetermined gap therebetween, and a peripheral edge between the two substrates. With the seal material provided in the vicinity of the part, the substrates are bonded together, and the liquid crystal is sealed and sealed inside the seal material between the substrates from the liquid crystal sealing port provided in a part of the seal material. A polarizing plate is attached to the outside of both substrates.

Each pixel includes a pixel electrode PIX and a thin film transistor TFT, and is provided corresponding to a portion where a plurality of scanning signal lines (or gate signal lines) G and video signal lines (or drain signal lines) D intersect. In this embodiment, a storage capacitor CST is provided for each image in order to hold the potential of the pixel electrode PIX.
CL is a capacitor line for supplying the reference voltage Vcom to the storage capacitor CST. Note that the capacitor line CL can be substituted by the scanning signal line G of the previous line.
The thin film transistor TFT of each pixel has a source connected to the pixel electrode PIX, a drain connected to the video signal line D, a gate connected to the scanning signal line G, and supplies a display voltage (grayscale voltage) to the pixel electrode PIX. To function as a switch.
Note that although the names of the source and the drain may be reversed due to the bias, the one connected to the video signal line D is referred to as the drain here.

The timing controller 110, the drain driver 130, and the gate driver 140 are mounted on a transparent insulating substrate (glass substrate) that constitutes the TFT substrate of the liquid crystal display panel 100, respectively.
As described above, the digital signal (display data, clock signal, etc.) sent from the timing controller 110 and the gradation reference voltage supplied from the power supply circuit are input to the first drain driver 130, and each drain driver is supplied. The signal is propagated through the internal signal line in 130 and a transmission line (transmission line on the glass substrate) between each drain driver 130 and input to each drain driver 130.
Here, the power supply voltage of each drain driver 130 is supplied to each drain driver 130 from the power supply circuit 120 via the FPC board 150.

Similarly, a digital signal (clock signal or the like) sent from the timing controller 110 is input to the head gate driver 140, and an internal signal line in each gate driver 140 and a transmission line (glass substrate) between the gate drivers 140 are displayed. It is transmitted to the upper transmission line) and input to each gate driver 140.
However, on the gate driver side, the power supply voltage of the gate driver 140 supplied from the power supply circuit 120 is also supplied to the leading gate driver 140, and the internal power supply line in each gate driver 140 and the transmission line between each gate driver 140. It is supplied to each gate driver 140 via (transmission line on the glass substrate).

The timing controller 110 is composed of one semiconductor integrated circuit (LSI), and each display control signal and display data of a clock signal, a display timing signal, a horizontal synchronizing signal, and a vertical synchronizing signal transmitted from the computer main body side. The drain driver 130 and the gate driver 140 are controlled and driven based on the data (R, G, B).
Based on the frame start instruction signal (FLM) and the shift clock (CL3) sent from the timing controller 110, the gate driver sequentially selects the high level for each gate signal line G of the liquid crystal display panel 100 every horizontal scanning time. Supply scan voltage.
As a result, a plurality of thin film transistors (TFTs) connected to the gate signal lines G of the liquid crystal display panel 100 are conducted for one horizontal scanning time.

FIG. 2 is a block diagram showing a schematic configuration of the drain driver 130 shown in FIG. In FIG. 2, the subscript i means a signal inputted from the outside of the drain driver 130, and the subscript o means a signal propagated through the drain driver 130 and outputted from the drain driver 130 to the outside. ing.
For example, CL2i is a display data latch clock signal input from the outside, and CL2i is a display data latch clock signal that propagates through the drain driver 130 and is output to the outside (the drain driver 130 at the next stage).
In the clock compensation circuit 200 shown in the figure, an internal clock signal having a duty ratio of 50% (that is, a high level period and a low level period are equal to each other) based on a display data latch clock signal (CL2) input from the outside. Clock signal) (CLL2) is generated.
The latch circuit (1) 135 shown in FIG. 11 sequentially latches display data sent from the data fetch / calculation circuit 133 based on the data fetch signal sent from the latch address selector 132. The display data sent from the data fetch / arithmetic circuit 133 is output to the outside through the data output circuit 134.
Here, the latch address selector 132 generates a data capture signal based on the internal clock signal (CLL2) sent from the clock control circuit 131.
Based on the output timing control clock (CL 1) sent from the clock control circuit 131, the latch circuit (2) 136 takes in the display data latched by the latch circuit (1) 135 and outputs it to the decoder circuit 137.

The decoder circuit 137 selects the gradation voltage corresponding to the display data sent from the latch circuit (2) 136 from the gradation voltages of 64 gradations supplied from the gradation voltage generation circuit 139, and supplies it to the amplifier circuit 138. Output.
The amplifier circuit 138 amplifies (current amplifies) the gradation voltage sent from the decoder circuit 137 and supplies it to each drain signal line D (Yi).
With the above operation, an image is displayed on the liquid crystal display panel 100.
Note that each of the decoder circuit 137 and the amplifier circuit 138 includes a positive circuit and a negative circuit, but detailed description thereof is omitted here.
Further, the gradation voltage generation circuit 139 generates a positive gradation gradation voltage of 64 gradations based on a positive gradation reference voltage (V0 to V4) supplied from the outside, and a negative gradation step supplied from the outside. Based on the adjustment reference voltage (V5 to V9), negative gradation 64 gradation voltages are generated.

FIG. 3 is a block diagram showing an example of the clock compensation circuit 200 shown in FIG.
The clock compensation circuit 200 shown in FIG. 3 is a circuit using a phase-locked loop circuit (hereinafter simply referred to as a PLL circuit).
The clock compensation circuit using this PLL circuit has a small area occupied by the circuit, is advantageous for downsizing the drain driver, and can reduce the peripheral area of the liquid crystal display panel.
The circuit shown in FIG. 3 includes a phase comparator 210, a charge pump circuit 211, a filter circuit 212, a voltage control transmission circuit (hereinafter simply referred to as a VCO circuit) 213, and an m frequency divider 214.
In this PLL circuit, the phase comparator 210 compares the phases of the input clock signal (fi) and the output clock signal (fo) output from the m frequency divider 214.
When the phase of the input clock signal (fi) is more advanced than the output clock signal (fo) as a result of the phase comparison, the phase comparator 210 outputs a phase delay pulse (INC), and the input clock signal When the phase of (fi) is delayed from the output clock signal (fo), a phase advance pulse (DEC) is output.

The charge pump circuit 211 converts the phase delay pulse (INC) or the phase advance pulse (DEC) into current pulses, respectively, and the filter circuit 212 uses the current pulse based on the phase delay pulse (INC) to The potential of the internal capacitor is raised, and the potential of the internal capacitor is lowered by a current pulse based on the phase advance pulse (DEC).
A VCO circuit 213 composed of a ring oscillator or emitter-coupled ratio stable multivibrator circuit or the like varies the oscillation frequency of the clock signal (fm) based on the potential of the internal capacitor.
As a result, the oscillation frequency and phase of the input clock signal (fi) and the output clock signal (fo) match.

Hereinafter, the reason why an output clock signal (fo) having a duty ratio of 50% can be obtained from an input clock signal (fi) having a duty ratio not 50% by the PLL circuit shown in FIG. 3 will be described with reference to FIG.
FIG. 4 shows the timing when the VCO circuit 213 outputs a clock signal (fm) having a frequency twice that of the input clock signal (fi) and the m divider 214 is constituted by a divide by two. A chart is shown.
As shown in FIG. 4, when the input clock signal (fi) whose duty ratio is not 50% and the output clock signal (fo) are synchronized, the VCO circuit 213 has a frequency twice that of the input clock signal (fi). Clock signal (fm) is output.
This clock signal (fm) is frequency-divided by a divide-by-2 to become an output clock signal (fo). The output clock signal (fo) is at the rising (or falling) time of the clock signal (fm). Since the clock signal changes from the High level to the Low level and from the Low level to the High level, the output clock signal (fo) is a clock signal having a duty ratio of 50%.
Since the VCO circuit 213 does not necessarily obtain a clock signal (fm) having a duty ratio of 50%, the m frequency divider 214 of the PLL circuit shown in FIG. 3 finally outputs an output having a duty ratio of 50%. Provided to obtain the clock signal (fo).

FIG. 5 is a block diagram showing another example of the clock compensation circuit 200 shown in FIG.
The clock compensation circuit 200 shown in FIG. 5 is a circuit using a delay locked loop circuit (hereinafter simply referred to as a DLL circuit).
The clock compensation circuit using the DLL circuit has a delay line, and therefore the area occupied by the circuit is larger than that using the PLL circuit. However, since the high-speed signal is unnecessary, the operation is stable and the number of pixels of the liquid crystal display panel is small. Since the signal frequency does not increase even if it increases, stable operation becomes possible.
The circuit shown in FIG. 5 includes a DLL circuit 220, a frequency divider (221, 222), and an exclusive OR circuit (EOR).
6 is a circuit diagram showing a circuit configuration of the DLL circuit 220 shown in FIG. 5, and FIG. 7 is a circuit diagram showing a configuration of the delay line 310 shown in FIG. FIG. 8 is a timing chart of the circuit shown in FIG.
In the DLL circuit 220 shown in FIG. 6, when the up / down counter 312 is in a state where OUT2 (DWN) is at a high level and OUT3 (UP) is at a low level with respect to the rising edge of the input (IN), The counter value is incremented by 1 to delay the phase.
The decoder circuit 311 decodes the count value of the up / down counter 312, turns on one of the switch elements (HIZ) of the delay line 310 corresponding to the count value, and increases the delay element DEL on the signal line. The delay time of the delay line 310 is increased.

Conversely, when OUT2 (DWN) is at the low level and OUT3 (UP) is at the high level with respect to the rising edge of the input (IN), the up / down counter 312 restores the phase that has been delayed too much. Therefore, the counter value is decreased by -1.
The decoder circuit 311 decodes the count value of the up / down counter 312, turns on one of the switch elements (HIZ) of the delay line 310 corresponding to the count value, and decreases the delay element DEL on the signal line. Reduce the delay time of the delay line.
In addition, when both OUT2 (DWN) and OUT3 (UP) are in the Low level with respect to the rising edge of the input (IN), the up / down counter 312 holds the counter value as the phases match. To do.
As a result, a clock signal (ft) having a phase delayed by 180 ° with respect to the input clock signal (fi) is obtained from OUT2.

The reason why an output clock signal (fo) with a duty ratio of 50% can be obtained from an input clock signal (fi) with a duty ratio of 50% by using the circuit shown in FIG. 5 will be described below with reference to FIG.
As shown in FIG. 9, the DLL circuit 220 obtains a clock signal (ft) whose phase is delayed by 180 ° with respect to an input clock signal (fi) whose duty ratio is not 50%.
The input clock signal (fi) is input to the frequency divider 221 and the clock signal (ft) delayed in phase by 180 ° is input to the frequency divider 222 to be a frequency-divided clock signal.
In this case, as described above, the clock signal frequency-divided by the divide-by-two is changed from the high level to the low level at the time of rising (or falling) of the frequency divided by 2 (for example, the input clock signal (fi)). Since the clock signal changes from the low level to the high level, the clock signal divided by the two-frequency divider becomes a clock signal having a duty ratio of 50%.
By inputting the clock signal divided by 2 by the divide-by-2 (221, 222) to the exclusive OR circuit (EOR), the duty ratio is 50% in synchronization with the input clock signal (fi). An output clock signal (fo) is obtained.

Note that the clock compensation circuit 200 shown in FIG. 3 has a merit that the circuit scale can be reduced, but has a demerit that requires high-speed operation.
On the other hand, the clock compensation circuit 200 shown in FIG. 5 has a merit that high-speed operation is not required, but has a demerit that the circuit scale becomes large.
Therefore, when incorporating the clock compensation circuit 200 of the present invention into an actual product, it is necessary to consider the advantages and disadvantages described above.

FIG. 10 is a circuit diagram showing a circuit configuration of data fetch / arithmetic circuit 133 and data output circuit 134 shown in FIG.
In FIG. 10, the data acquisition / arithmetic circuit 133 is on the left side of the dotted line (in the direction of arrow AA), and the data output circuit 134 is on the right side of the dotted line (in the direction of arrow BB).
As shown in the figure, the data fetch / arithmetic circuit 133 is composed of arithmetic circuits (21, 22, 23) and a latch circuit 31, and the data output circuit 134 is composed of arithmetic circuits (24, 25, 26), a latch circuit (32, 33), a multiplex circuit (41, 42), and a delay circuit 51.
Note that FIG. 10 illustrates a case where the internal signal line for display data transfer is also used as the internal bus line used for the liquid crystal drive voltage output of the drain driver 130.

Hereinafter, the operation of each unit will be described.
FIG. 11 is a diagram showing a circuit configuration per internal bus line in the circuit diagram shown in FIG. 10, and FIG. 12 shows the clock signal (CLL2), display data, and internal signal lines shown in FIG. It is a figure which shows the timing chart of display data.
In FIG. 11, the arithmetic circuits (21, 22, 24, 25) are omitted.
As shown in FIG. 12, display data (D1) input from the outside is taken into a D-type flip-flop circuit (hereinafter simply referred to as FF) 1 at the rising edge of the clock signal (CLL2).
At the falling edge of the clock signal (CLL2), the externally input display data (D2) is taken into the FF3 and output to the internal bus line B. At the same time, the display data (D1) taken into the FF1 is , FF2 and output to the internal bus line A.
Thus, in this embodiment, display data is sent to the internal bus line at the same timing. The reason why the internal bus line is composed of two bus lines will be described later.

The display data sent to the internal bus lines (A, B) propagates in the long side direction of the drain driver 130, that is, propagates over the long side length of the semiconductor chip. Causes a delay and causes a phase shift from the clock signal (CLL2).
Therefore, when the clock signal (CLL2) falls, the display data (D1) on the internal bus line is taken into FF4, and at the same time, the display data (D2) on the internal bus line is taken into FF5, and the phase shift described above is performed. Absorb.
Further, the display data fetched by the FF 4 and the FF 5 are alternately output to the outside by a multi-press circuit (switch circuit) 41. Thereby, the display data output to the outside is output to the outside in the order of input from the outside.

In the technique of Non-Patent Document 1 (Sharp Technical Report, No. 74 (August 1999), pages 31 to 34) that outputs the signal to be transferred to the drain driver of the next stage with the polarity inverted, the positive logic Since it is necessary to connect the drain driver and the negative logic drain driver in cascade, two types of drain drivers are required, which increases the cost of the drain driver, complicates the assembly of the liquid crystal display device, and improves the yield. There is a demerit such as not.
However, according to the present invention, since the circuit for correcting the duty of the clock signal (CL2) is provided, there is no need to invert the transfer data and only one type of drain driver is required, so that the cost of the drain driver is increased. In addition, the liquid crystal display device can be easily assembled, and the yield can be significantly improved.

In FIG. 10, the case where the internal signal line for display data transfer is also used as the internal bus line used for the liquid crystal drive voltage output of the drain driver 130 has been described. For example, as shown in FIG. An internal signal line for display data transfer may be provided separately from the internal bus line used for the liquid crystal drive voltage output of the drain driver 130.
However, in the example shown in FIG. 13, 36 internal bus lines (for example, 6 bits × 3 (R, G, B bus lines) × 2 = 36) of the self-drain driver 130 and the equivalent internal Since a signal line is required, it is disadvantageous because the area of the semiconductor chip constituting the drain driver 130 increases.
On the other hand, in this embodiment, the internal signal line for display data transfer is shared with the internal bus line used for the liquid crystal drive voltage output of the drain driver 130, so that the example shown in FIG. In comparison, the area of the semiconductor chip can be reduced.

Next, returning to FIG. 10, the operation of the arithmetic circuits (21, 22) will be described.
In the display data transmission line connecting the timing controller 110 of FIG. 1 to the leading drain driver 130 and each drain driver 130, power consumption (charging / discharging in the transmission line, etc.) due to a change in display data becomes a problem.
For example, when 9 of the display data of 3 pixels (× 6 bits = 18) are at a high level, the remaining 9 are at a low level, and the display data for the next 3 pixels is at this inversion level. All 18 display data changes, and this operation is faster, and the larger the amplitude, the higher the power consumption due to charging / discharging in the display data transmission line.
Therefore, in order to suppress the power consumption due to the above state, the timing controller 110 provides one data inversion signal (POL signal shown in FIG. 2), calculates 18 display data in advance based on the data inversion signal, The 18 display data are not changed, and only the data inversion signal is inverted and transmitted.

The arithmetic circuit 21 of each drain driver 130 calculates these signals, so that nine of the display data of three pixels (× 6 bits = 18) are at the high level and the remaining nine are at the low level. The display data for the next three pixels is a circuit that generates this inversion level, realizes the same function as when there is no data inversion signal, and suppresses power consumption.
The arithmetic circuit 21 is configured by exclusive OR, and as shown in Table 1, when the data inversion signal (POL signal in FIG. 2) is “0”, the display data is output without inversion, and the data inversion signal ( When the POL signal in FIG. 2 is “1”, the display data is inverted and output.

Next, the operation of the arithmetic circuit 22 will be described.
The liquid crystal display panel 100 is driven by an alternating drive method.
One of the AC drive methods is a common symmetry method. In the common symmetry method (for example, dot inversion method or n-line inversion method), a positive gradation voltage and a negative gradation voltage are applied to each pixel electrode. Must be applied.
FIG. 14 is a diagram showing in more detail the circuit configuration per adjacent drain signal line (Yi, Yi + 1) for each color of the drain driver 130 of this embodiment.
14, 235A and 235B indicate latch circuits of the latch circuit (1) 135 shown in FIG. 2, and 236A and 236B indicate latch circuits of the latch circuit (2) 136 shown in FIG.
Reference numerals 237A and 237B respectively denote decoder circuits of the decoder circuit 137 shown in FIG. 2, 237A is a high voltage decoder circuit for selecting a positive gradation voltage, and 237B is a low voltage for selecting a negative gradation voltage. It is a voltage decoder circuit.
Similarly, reference numerals 238A and 238B respectively denote the amplifier circuits of the amplifier circuit 138 shown in FIG. 2, 237A is a high voltage amplifier circuit that amplifies the positive gradation voltage, and 237B selects the negative gradation voltage. It is a low voltage amplifier circuit.

Thus, in this embodiment, instead of providing a positive polarity circuit and a negative polarity circuit for each drain signal line, a pair of positive polarity side circuits and a negative polarity side are provided for each drain signal line for each adjacent color. And a positive gradation voltage or a negative gradation voltage is supplied to each drain signal line for each adjacent color by switching by a switch unit 239.
For example, when a positive gradation voltage is applied to the drain signal line (Yi) and a negative gradation voltage is applied to the drain signal line (Yi + 1), the drain signal line (Yi) is set to a positive voltage by the switch unit 239. The drain signal line (Yi + 1) is connected to the amplifier circuit 238A to the low voltage amplifier circuit 238B. Conversely, the drain signal line (Yi) has a negative gradation voltage, and the drain signal line (Yi + 1) has a positive gradation. When applying a voltage, the switch unit 239 connects the drain signal line (Yi) to the low voltage amplifier circuit 238B and the drain signal line (Yi + 1) to the positive voltage amplifier circuit 238A.

However, the positive polarity side latch circuit 235 is connected to the internal bus line D shown in FIG. 10, and the negative polarity side latch circuit 235B is connected to the internal bus line E shown in FIG.
Therefore, in order to supply the positive gradation voltage to the drain signal line (Yi), the display data for selecting the positive gradation voltage for the drain signal line (Yi) to the internal bus line D, In addition, in order to supply the negative gradation voltage to the drain signal line (Yi), display data for selecting the negative gradation voltage to the drain signal line (Yi) is sent to the internal bus line E. There is a need to.
The arithmetic circuit 22 is provided to send the display data described above to the internal bus line D or the internal bus line E shown in FIG.

The arithmetic circuit 22 includes switch circuits (61, 62), and the switch circuit 61 is output from the FF 3 in accordance with the “1” or “0” level of the AC signal (M signal shown in FIG. 2). Display data or display data output from the FF 2 is selected and sent to the internal bus line D.
Similarly, the switch circuit 62 selects the display data output from the FF2 or the display data output from the FF3 according to the “0” or “1” level of the alternating signal (M signal shown in FIG. 2). To the internal bus line E.
Here, since the AC signal M supplied to the switch circuit 62 is an inverted signal of the AC signal M supplied to the switch circuit 61, the display data sent to the internal bus line D is FF3 (or FF2). ), The display data sent to the internal bus line E is the display data output from FF2 (or FF3).
The calculation contents of the calculation circuit 22 are shown in FIG.

The arithmetic circuit 24 is a circuit that performs the reverse operation of the arithmetic circuit 21.
This arithmetic circuit 24 is composed of an exclusive OR circuit provided for each of the two internal bus lines (D, E), and further inverts the display data inverted by the arithmetic circuit 21 based on the data inversion signal. The display data that has not been inverted by the arithmetic circuit 21 is output as it is.
The arithmetic circuit 25 changes the order of the display data sent on the two internal bus lines (D, E) according to the polarity of the alternating signal M, so that the order is changed to the display data input order. Therefore, the multiplex circuit 41 is a circuit for changing the selection order of FF4 and FF5.
The calculation contents of the calculation circuit 25 are shown in FIG.
As shown in FIG. 16, when the AC signal M is “0”, the arithmetic circuit 25 outputs display data in the order of the internal bus line D → the internal bus line E → the internal bus line D, and the AC signal When M is “1”, display data is output in the order of internal bus line E → internal bus line D → internal bus line E.

As described in the arithmetic circuit 24, the display data to be transferred needs to be reverse-calculated from the display data calculated by the arithmetic circuit 21.
Therefore, in this embodiment, the data inversion signal is also taken in in synchronization with the clock signal (CLL2) by FF6 to FF8, and as described above, the two internal bus lines (D , E) Since the order of the display data to be sent out has been changed, the data inversion signals output from FF7 and FF8 are converted to internal signals by the switch circuits (63, 64) of the arithmetic circuit 23 accordingly. Sort and send to line (J, K).

The data inversion signals on the internal signal lines (J, K) are respectively input to exclusive OR circuits provided for the two internal bus lines (D, E) in the arithmetic circuit 24.
At the falling edge of the clock signal (CLL2), the data inversion signal on the internal signal lines (J, K) is taken into the FF9 and FF10, and the multiplex circuit 42 causes the FF9 and FF10 to be updated by the arithmetic circuit 26. The selection order is changed, and the data inversion signal on the exchanged internal signal line (J, K) is returned to the original state in the original state.

Next, the operation of the delay circuit 51 will be described.
As shown in FIG. 17, in the case of the dual edge capture method in which the display data is captured at the rising edge and the falling edge of the clock signal, the display data is switched in order to allow a setup period and a hold period. It is necessary that the rising time point and the falling time point of the clock signal (CLL2) are located at an intermediate time point.
However, as can be seen from the timing chart shown in FIG. 12, in this embodiment, the switching time of the display data sent from the multiplex circuit 41 coincides with the rising time and falling time of the clock signal (CLL2). Yes.
In this case, the next-stage drain driver 130 cannot capture the display data in FF1 to FF3.
The delay circuit 51 is provided to delay the phase of the clock signal (CLL2) output to the outside and solve the above-described problems.

FIG. 18 is a circuit diagram showing an example of the delay circuit 51 shown in FIG.
The circuit shown in FIG. 18 is composed of n inverter circuits connected in cascade. The number of inverter circuits (n) is such that the delay amount of the clock signal (CLL2) by the inverter circuits is as shown in FIG. In addition, the delay amount (90 °) is set such that the rising point and the falling point of the clock signal (CLL2) are positioned at the intermediate point of the display data switching point.
FIG. 19 is a circuit diagram showing another example of the delay circuit 51 shown in FIG.
The circuit shown in FIG. 19 is the delay locked loop circuit described with reference to FIGS. 6 to 8. In this case, a clock signal (ft) delayed by 90 ° from OUT1 is obtained.

FIG. 20 is a schematic cross-sectional view for explaining a method of connecting the drain driver 130 and the FPC substrate 150 to the glass substrate.
As shown in FIG. 20, the drain driver 130 includes a wiring layer 320 of the FPC board 150 → a metallization layer 321 of the glass substrate SUB1 → a wiring layer 322 of the glass substrate SUB1 → a metallization layer 323 of the glass substrate SUB1 → a drain driver (semiconductor chip). ) A power supply voltage is supplied through 130 bump electrodes 324.
In this case, in this embodiment, as shown in FIG. 21, the power supplied to the display data transfer circuit (for example, the multiplex circuit 41) 331 and the clock signal transfer circuit (for example, the delay circuit 51) are provided. The power supplied to 332 is separated.
That is, power is supplied to the display data transfer circuit 331 and the clock signal transfer circuit 332 through different pad electrodes 333 and power supply lines.
FIG. 21 is a diagram showing a power supply voltage supply system to the drain driver 130 of this embodiment. In FIG. 22, the resistance R is a metallized layer 321 of the glass substrate → a wiring layer 322 of the glass substrate → a glass substrate. The resistance component between the metallized layer 323 and the bump electrode 324 of the drain driver (semiconductor chip) 130 is shown.

FIG. 22 is a diagram showing a power supply voltage supply system when the power supplied to the display data transfer circuit 331 and the power supplied to the clock signal transfer circuit 332 are not separated. In the example shown in FIG. Since the current flowing through the multiplex circuit 41 of the display data transfer circuit 331 is required by the number of bits of the display data, the voltage drop at the resistor R is large, so that the current is supplied to the clock signal transfer circuit 332. Power supply voltage decreases, and the amplitude of the clock signal (CLL2) decreases.
However, in this embodiment, since the power supplied to the display data transfer circuit 331 and the power supplied to the clock signal transfer circuit 332 are separated, the clock signal transfer circuit 332 as described above is provided. The supplied power supply voltage does not decrease and the amplitude of the clock signal (CLL2) does not decrease.
That is, in this embodiment, the influence of the display data transfer circuit 331 on the clock signal transfer circuit 332 can be reduced.

[Example 2]
FIG. 23 is a block diagram illustrating a schematic configuration of the drain driver according to the second embodiment of the present invention.
The present embodiment is different from the first embodiment in that the clock compensation circuit 200 is provided in the data output circuit 134.
In this embodiment, the clock generated by the clock compensation circuit 200 provided in the data output circuit is delayed by the delay circuit 51 and output to the drain driver 130 at the next stage.
The operation of each part in the drain driver 130 of this embodiment is not described in detail because the internal clock signal (CLL2) may be read as the clock signal (CL2) in the above description.
Further, the insertion position of the clock compensation circuit 200 is limited to the clock signal input side of the drain driver 130 as in the first embodiment or the clock signal output side of the drain driver 130 as in the present embodiment. If the above-described clock compensation circuit 200 is inserted into the transmission path until the clock signal (CLL2) input from the outside is output to the outside in the drain driver 130, the above-described operation / Needless to say, an effect can be obtained.

[Example 3]
FIG. 24 is a block diagram illustrating a schematic configuration of the drain driver according to the third embodiment of the present invention.
In this embodiment, instead of providing the clock compensation circuit 200 of each of the embodiments, as shown in FIG. 25, until the clock signal (CL2) input from the outside is output to the outside in each drain driver 130. In this transmission path, the circuit element (for example, inverter circuit) 52 inserted is set to a value such that the number of times the logic level is inverted is an odd number.
As described above, in the CMOS inverter circuit, when the threshold value (Vth) of each MOS transistor changes, the duty ratio of the output pulse signal (that is, the ratio of the high level period to the period of the pulse signal) changes.
Therefore, in the liquid crystal display device that employs the digital signal sequential transfer method, the change in the duty ratio of the clock signal (CL2) is accumulated while the clock signal (CL2) is being transmitted to each drain driver 130, and the display data is displayed. And the phase difference becomes large.

However, as described above, the number of inversions of the logic level of the clock signal (CL2) propagated by each drain driver 130 is set to an odd number, for example, the clock signal (CL2) of the previous stage drain driver 130 is changed. Even if the duty ratio changes so as to increase, the next-stage drain driver 130 changes so that the duty ratio of the clock signal (CL2) decreases.
As a result, the change in the duty ratio of the clock signal (CL2) can be reduced as a whole.
The operation of each part in the drain driver 130 of this embodiment is not described in detail because the internal clock signal (CLL2) may be read as the clock signal (CL2) in the above description.

As described above, in order to prevent variation in the duty ratio, a method of inverting display data and transferring data to the drain driver at the next stage is disclosed in Non-Patent Document 1 (Sharp Technical Report, No. 74 (1999). (August), pages 31 to 34), the present embodiment has a point that the display data is output to the next stage in synchronization with the clock signal (CL2) and the clock without inverting the display data. It differs from that described in the above document in that only the signal (CL2) is inverted.
The device described in Non-Patent Document 1 described above has no idea of outputting display data in synchronization with a clock, so that all display data must be inverted and output in order to prevent variation in duty ratio.
Therefore, since the drain driver of the next stage needs to generate the liquid crystal driving voltage based on the inverted display data, it must be a negative logic drain driver, and the number of types of drain drivers increases and the cost increases. There are disadvantages such as complicated manufacture of the liquid crystal display device and reduced yield.

On the other hand, in the present invention, since display data is output to the next drain driver in synchronization with the clock signal (CL2), it is not necessary to invert the display data and output it, and the next drain driver has the same logic. The drain driver can also be used, so that the cost is not increased, the liquid crystal display device can be easily manufactured, and the yield can be improved.
In the present invention, the clock signal (CL2) is inverted and output in order to prevent the duty ratio fluctuation. However, the drain driver at the next stage has a special control only for the clock signal (CL2). Since it is only necessary to provide a circuit, the circuit is simple, and a liquid crystal display device can be configured with one type of logic drain driver.
Specifically, in this embodiment, each drain driver is provided with a circuit that makes the timing when the start pulse of each drain driver is taken in by the clock signal (CL2) the same for the normal clock and the inverted clock.

Alternatively, as shown in FIG. 26, the display data transferred to the drain driver 130 at the next stage is delayed by a predetermined time (for example, 90 °).
In FIG. 26, the forward clock signal represents the clock signal (CL2) input to the preceding drain driver 130, and the inverted clock signal represents the clock signal (CL2) input to the subsequent drain driver 130.
In the example shown in FIG. 26, in the drain driver 130 at the previous stage, the display data (1) is taken into the drain driver 130 at the rising edge of the normal rotation clock signal, and the display data is delayed by 90 ° by a delay circuit, for example. Thus, since the next-stage drain driver 130 also transfers the display data (1) to the drain driver 130 at the rising edge of the inverted clock signal.
Even when the display data is inverted and transferred to the next-stage drain driver, each drain driver is provided with a circuit for returning the display data whose polarity has been inverted to the display data with the original polarity, and a circuit for controlling the polarity of the display data. By providing it, it is possible to share the drain driver.
However, the above-described non-patent document 1 (Sharp Technical Report, No. 74 (August 1999), pages 31 to 34) is not studied at all, and each of display data A circuit for controlling the polarity inversion for each bit is required, and there is a disadvantage that the circuit becomes large-scale.

[Example 4]
FIG. 27 is a diagram showing a simplified transmission path of the clock signal (CL2) of the embodiment.
As described above, in the technique disclosed in Non-Patent Document 1 described above, each drain driver inverts display data and transfers it to the next-stage drain driver.
Also, only one system of clock signals is provided.
In the technique of Non-Patent Document 1 described above, if the clock signal (CL2) input to the drain driver is at the H level, the clock signal (CL2) input to the drain driver at the next stage is at the L level, and further the next stage. The clock signal (CL2) input to the drain driver becomes H level. Therefore, it is necessary to prepare two types of drain drivers.
That is, it is premised that a drain driver (for example, 130a and 130c in FIG. 27) having a logic configuration on the assumption that display data and a normal signal of the clock signal (CL2) are input and an inverted signal are input. It is necessary to prepare a drain driver (for example, 130c in FIG. 27) having the above logical configuration.
Thus, the drain driver described in Non-Patent Document 1 described above has a drawback that the circuit configuration of the liquid crystal driving circuit becomes complicated.

FIG. 28 is a diagram illustrating a simplified transmission path of the clock signal (CL2) according to the fourth embodiment of the present invention.
In this embodiment, each drain driver (130a, 130b, 130c) has a forward clock (CL2 (T)) of the clock signal (CL2) and an inverted clock (CL2 (B)) of the clock signal (CL2). Entered.
Here, as in the previous embodiment, the normal rotation clock (CL2 (T)) and the inversion clock (CL2 (B)) have an odd number of logic level inversions in the transmission path in each drain driver. It is set to become.
In FIG. 28 as well, the odd number of inversion times of the logic level of the normal rotation clock (CL2 (T)) and the inversion clock (CL2 (B)) is expressed by three inverters connected in series.

Even in the present embodiment, even if the duty ratio of the forward clock (CL2 (T)) and the inverted clock (CL2 (B)) is increased in the previous drain driver (for example, 130a), the next drain In the driver (for example, 130b), both the forward rotation clock (CL2 (T)) and the reverse clock (CL2 (B)) change so that the duty ratio becomes small.
As a result, it becomes possible to reduce the change in the duty ratio of the forward clock (CL2 (T)) and the inverted clock (CL2 (B)) of the clock signal (CL2) as a whole.
Further, in this embodiment, the transmission line (transmission line on the glass substrate) between the drain drivers through which the forward clock (CL2 (T)) and the inverted clock (CL2 (B)) are transmitted is switched, The normal rotation clock (CL2 (T)) output from the drain driver (for example, 130a) is input as the inverted clock (CL2 (B)) of the next stage drain driver (for example, 130b), and the previous stage drain driver ( For example, the inversion clock (CL2 (B))) output from 130a) is input as the normal rotation clock (CL2 (T)) of the drain driver (for example, 130b) of the next stage.

By adopting such a configuration, the level of the clock signal input to the normal clock (CL2 (T)) input terminal of each drain driver (130a, 130b, 130c) is the same. There is no need to provide a special control circuit or the like only for the clock signal (CL2), and it is not necessary to prepare two types of drain drivers.
In this embodiment, as shown in FIG. 29, the forward clock (CL2 (T)) and the inverted clock (CL2 (B)) are transmitted inside each drain driver (130a, 130b, 130c). The internal signal line is switched, and the normal rotation clock (CL2 (T)) output from the previous stage drain driver (eg, 130a) is used as the inverted clock (CL2 (B)) of the next stage drain driver (eg, 130b). The inverted clock (CL2 (B)) output from the previous stage drain driver (for example, 130a) is input as the forward rotation clock (CL2 (T)) of the next stage drain driver (for example, 130b). It may be.

[Example 5]
FIG. 30 is a circuit diagram showing the circuit configuration of the data fetch / arithmetic circuit 133 and the data output circuit 134 according to the fifth embodiment of the present invention.
Also in FIG. 30, the data fetch / arithmetic circuit 133 is on the left side of the dotted line (in the direction of arrow AA), and the data output circuit 134 is on the right side of the dotted line (in the direction of arrow BB).
As shown in FIG. 30, the present embodiment is different from the data fetch / arithmetic circuit 133 and the data output circuit 134 of the first embodiment shown in FIG. 10 in that standby circuits (71, 72) are added. .
The calculation of the arithmetic circuit (21, 22, 23) described above is necessary only when the display data input from the outside is the display data fetched in the own drain driver.
Therefore, in this embodiment, when the display data input from the outside by the standby circuit (71, 72) is the display data fetched in its own drain driver, the arithmetic circuit (21, 22, 23) is validated. In other cases, the arithmetic circuit (21, 22, 23) is invalidated.

FIG. 31 is a block diagram showing a circuit configuration of standby circuit 71 shown in FIG.
As shown in FIG. 31, in the standby circuit 71, the counter circuit 350 counts the clock signal (CLL2) when a start pulse (display data capture start signal) is input.
When the counter number of the counter circuit 350 is equal to or smaller than the predetermined count number, the switch circuit 351 outputs a data inversion signal. When the counter number of the counter circuit 350 exceeds the predetermined count number, the switch circuit 351 Outputs a constant bias voltage (such as a high level voltage or a low level voltage) Vbb.
As a result, the arithmetic circuit 21 executes the arithmetic contents shown in Table 1.

Note that the standby circuit 72 has the same circuit configuration as the standby circuit 71.
According to the present embodiment, when display data input from the outside is display data that does not need to be captured in the own drain driver (in other words, display data for transfer only), it is necessary to perform an extra calculation. Therefore, power consumption can be reduced.
In each of the above embodiments, the drain driver 130 is directly mounted on the glass substrate of the liquid crystal display panel. However, the present invention is not limited to this, and the drain driver 130 may be a tape. Needless to say, the present invention can also be applied to a digital signal sequential transfer type liquid crystal display device mounted on a carrier package.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a block diagram which shows the basic composition of the display panel of the liquid crystal display module of Example 1 of this invention. FIG. 2 is a block diagram illustrating a schematic configuration of a drain driver illustrated in FIG. 1. FIG. 3 is a block diagram illustrating an example of a clock compensation circuit illustrated in FIG. 2. FIG. 4 is a diagram for explaining the reason why an output clock signal (fo) with a duty ratio of 50% is obtained from an input clock signal (fi) with a duty ratio not 50% by the circuit shown in FIG. 3. FIG. 3 is a block diagram illustrating another example of the clock compensation circuit illustrated in FIG. 2. FIG. 6 is a circuit diagram illustrating a circuit configuration of a DLL circuit illustrated in FIG. 5. FIG. 7 is a circuit diagram showing a configuration of a delay line shown in FIG. 6. It is a figure which shows the timing chart of the circuit shown in FIG. FIG. 6 is a diagram for explaining the reason why an output clock signal (fo) with a duty ratio of 50% is obtained from an input clock signal (fi) with a duty ratio that is not 50% by the circuit shown in FIG. It is a circuit diagram which shows the circuit structure of the data acquisition / arithmetic circuit which shows Example 1 of this invention, and a data output circuit. In the circuit diagram shown in FIG. 10, it is a figure which shows the circuit structure per internal bus line. It is a figure which shows the timing chart of the clock signal (CLL2) shown in FIG. 11, display data, and the display data on an internal signal line. It is a figure which shows the individuality at the time of providing the internal signal line for a display data transfer separately from an internal bus line. It is a figure which shows in more detail the circuit structure per adjacent drain signal line (Y) for every color of the drain driver of Example 1 of this invention. It is a figure which shows the calculation content of the arithmetic circuit 22 shown in FIG. It is a figure which shows the calculation content of the arithmetic circuit 25 shown in FIG. It is a figure for demonstrating the capture time of display data. FIG. 11 is a circuit diagram illustrating an example of a delay circuit illustrated in FIG. 10. FIG. 11 is a circuit diagram illustrating another example of the delay circuit illustrated in FIG. 10. It is a schematic cross section for demonstrating the connection method with the glass substrate of a drain driver and a FPC board | substrate. It is a figure which shows the power supply voltage supply system | strain to the drain driver of Example 1 of this invention. It is a figure which shows the power supply voltage supply system in the case of not isolate | separating the power supply supplied to the circuit for display data transfers, and the power supply supplied to the circuit for clock signal transfers. It is a block diagram which shows schematic structure of the drain driver of Example 2 of this invention. It is a block diagram which shows schematic structure of the drain driver of Example 3 of this invention. It is a figure for demonstrating the clock compensation method of Example 3 of this invention. It is a figure for demonstrating the relationship between the clock signal and display data of an example of Example 3 of this invention. It is a figure which simplifies and shows the transmission path | route of the clock signal (CL2) of Example 3 of this invention. It is a figure which simplifies and shows the transmission path | route of the clock signal (CL2) of Example 4 of this invention. It is a figure which simplifies and shows the modification of the transmission path | route of the clock signal (CL2) of Example 4 of this invention. It is a circuit diagram which shows the circuit structure of the data acquisition and arithmetic circuit of Example 5 of this invention, and a data output circuit. FIG. 31 is a block diagram showing a circuit configuration of a standby circuit shown in FIG. 30. It is a figure for demonstrating the setup period and hold period in a dual edge taking-in system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1-10 D type flip-flop circuit 21-26 arithmetic circuit 31-32, 235A, 235B, 236A, 236B Latch circuit 41, 42 Multiplex circuit 51 Delay circuit 52 Circuit element 61, 62, 63, 64, 351 Switch circuit 71, 72 Standby circuit 100 Liquid crystal display panel 110 Timing controller 120 Power supply circuit 130, 130a, 130b, 130c Drain driver 131 Clock control circuit 132 Latch address selector 133 Data fetch / arithmetic circuit 134 Data output circuit 135 Latch circuit (1)
136 Latch circuit (2)
137, 311, 237A, 237B Decoder circuit 138, 238A, 238B Amplifier circuit 139 Gradation voltage generation circuit 140 Gate driver 150 Flexible printed wiring board (FPC board)
200 Clock Compensation Circuit 210 Phase Comparator 211 Charge Pump Circuit 212 Filter Circuit 213 VCO Circuit 214 m Divider 220 DLL Circuit 221, 222 Divider 239 Switch Unit 310 Delay Line 312, 350 Counter 320, 322 Wiring Layer 321, 323 Metallized layer 324 Bump electrode 331 Display data transfer circuit 332 Clock signal (CL2) transfer circuit 333 Pad electrode SUB1 Glass substrate R Resistance DEL Delay element HIZ Switch element PIX Pixel electrode TFT Thin film transistor G ... Scan signal line (or gate signal line) )
D, Y Video signal line (or drain signal line)
CST holding capacitor CL capacitor line EOR Exclusive OR circuit.

Claims (6)

A liquid crystal display device comprising: a liquid crystal display element; and a liquid crystal driving circuit that supplies a gradation voltage to the liquid crystal display element,
The liquid crystal driving circuit takes in the first data input to the liquid crystal driving circuit at the timing of switching from the first level of the clock signal to the second level, and the first level from the second level of the clock signal. The second data input to the liquid crystal driving circuit at the timing of switching to the level is fetched,
Based on the alternating signal, the first data is sent to one of the first internal bus line or the second internal bus line, and the second data is sent to the first internal bus line or the Send to the other of the second internal bus lines,
A positive polarity side circuit for supplying a positive gradation voltage is connected to the first internal bus line,
A liquid crystal display device, wherein a negative polarity side circuit for supplying a negative gradation voltage is connected to the second bus line.   Based on the alternating signal, the positive polarity side circuit is connected to one of the first drain signal line or the second drain signal line, and the negative polarity side circuit is connected to the first drain signal line, or The liquid crystal display device according to claim 1, wherein the liquid crystal display device is connected to the other of the second drain signal lines.   The liquid crystal display device according to claim 1, wherein the clock signal is a clock signal in which a variation in duty ratio of an external clock signal input from the outside of the liquid crystal driving circuit is compensated.   When the liquid crystal driving circuit sends the first data and the second data input to the liquid crystal driving circuit to the first internal data bus and the second internal data bus, 4. The liquid crystal display according to claim 1, wherein an operation is performed on the first data and the second data based on a data inversion signal input from the outside. 5. apparatus.   The order of outputting the data on the first internal data bus and the data on the second internal data bus to the outside of the liquid crystal driving circuit after changing the order based on the polarity of the alternating signal. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device.   The first data and the second data input to the liquid crystal driving circuit are input via a transmission line formed on a glass substrate included in the liquid crystal display element. The liquid crystal display device according to claim 1.

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