JP2006162762A - Display apparatus, panel, module, mobile terminal, digital camera, digital video camera, display and television set - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus suppressing the occurrence of a false contour. <P>SOLUTION: The display apparatus includes at least; a first pixel in which a plurality of subframe periods appear in a first sequence; a second pixel in which a plurality of subframe periods appear in a second sequence in one frame period; a first gate line to which a transistor included in the first pixel is connected; and a second gate line to which a transistor included in the second pixel is connected. The display apparatus further includes; at least a first gate driver for controlling the first gate line; and a second gate driver for controlling the second gate driver. A part of a conductive layer composing the first gate line included in the display apparatus overlaps with a second conductive layer composing the second gate line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a display device and an electronic apparatus having a plurality of pixels. In addition, the present invention relates to a display device and an electronic device that express gradation by a time gradation method.

The display device includes a driving method using an analog video signal and a driving method using a digital video signal. In the former driving method, gradation is expressed by controlling the luminance of the light emitting element with an analog video signal. On the other hand, as one of the latter driving methods, there is a time gray scale method in which a gray scale is displayed by controlling the length of time a pixel is lit during one frame period. When displaying by the time gray scale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with the video signal, the pixels are turned on or off in each subframe period. With the above structure, the total length of the pixel lighting period can be controlled by the video signal during one frame period, and gradation can be expressed (for example, refer to Patent Document 1).
JP 2001-324958 A

When gradation is expressed by the time gradation method, there is a problem that a pseudo contour is displayed in the pixel portion depending on the frame frequency. Pseudo contour is an unnatural contour line that is often seen when intermediate gray levels are displayed by the time gray scale method, and is mainly caused by fluctuations in perceived luminance caused by human visual characteristics. . The pseudo contour includes a moving image pseudo contour generated when a moving image is displayed and a still image pseudo contour generated when a still image is displayed. In a pseudo-contour, a subframe period included in a previous frame period and a subframe period included in a subsequent frame period are visually recognized by human eyes as a continuous frame period. It happens by being done. In other words, a moving image pseudo contour is an unnatural bright line or dark line that is displayed on the pixel portion when the number of gradations different from the number of gradations that should be displayed in the original frame period is recognized by the human eye. Corresponds to a line. The generation mechanism of the still image pseudo contour is the same as that of the moving image pseudo contour. When displaying a still image, a still image pseudo-contour shows that a moving image is displayed on the pixels near the boundary because the human viewpoint slightly moves left and right and up and down at the boundary between regions with different numbers of tones. Occurs by appearing to be. In other words, a still image pseudo-contour corresponds to an unnatural bright line or dark line that appears to move around the boundary by generating a moving picture pseudo-contour at a pixel near the boundary of an area having different gradation levels. .

It is effective to increase the frame frequency in order to suppress the generation of the pseudo contour. However, as the frame frequency increases, the length of each subframe period decreases. Then, it becomes necessary to increase the drive frequency of the drive circuit in accordance with the length of the shortest subframe period. Therefore, it is not preferable to increase the frame frequency unnecessarily in consideration of the reliability and power consumption of the drive circuit. .

In addition, a method called spatial dispersion that suppresses the generation of pseudo contours is also effective. Normally, when the gradation is expressed by the time gradation method, the order in which the subframe periods appear is the same for all the pixels, but in the spatial dispersion method, the subframe period appears for each pixel. Change the order. In other words, the spatial dispersion method is a method of changing the timing at which the pixels are lit by changing the order in which the subframe periods appear for each pixel even if the same gradation is displayed. When such a spatial dispersion method is performed with a simple progressive drive panel, a method realized by switching the lighting or non-lighting state of the pixels in the same subframe period or the lighting period There is a technique realized by switching the lighting or non-lighting state of a pixel between a plurality of subframe periods having the same sum. In order to switch the lighting or non-lighting state of a pixel, it is necessary to replace the video signal input to the pixel. However, in a simple progressive drive panel, the video signal to be replaced is limited, and thus the effect is limited.

In view of the above-described problems, it is an object of the present invention to provide a display device and an electronic apparatus that do not require a high driving frequency and suppress the generation of pseudo contours by adopting a spatial dispersion method.

The display device of the present invention includes at least a plurality of pixels and a plurality of gate lines. The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order and a second pixel in which a plurality of subframe periods appear in a second order in one frame period. It is characterized by that. For example, when one frame period is divided into three subframe periods, the first pixel appears in the order of the first subframe period, the second subframe period, and the third subframe period. In the second pixel, the third subframe period, the second subframe period, and the first subframe period appear in this order. The plurality of gate lines include at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected.

In addition to the above structure, the display device of the present invention includes at least a first gate driver that controls the first gate line and a second gate driver that controls the second gate line. These gate drivers are provided in order to operate the first pixel and the second pixel so that the order of appearance of the sub-frame periods of the first pixel and the second pixel is different.

In addition, a part of the conductive layer included in the first gate line included in the display device of the present invention overlaps with the second conductive layer included in the second gate line. Thus, the spatial dispersion can be more effectively performed by devising the arrangement of the gate lines.

The display device of the present invention has at least a plurality of gate lines. The plurality of gate lines are divided into a plurality of groups (hereinafter referred to as gate line groups), and the plurality of gate lines are scanned by each gate line group.
The display device of the present invention includes at least a plurality of pixels. The plurality of pixels are divided into a plurality of groups (hereinafter referred to as pixel groups), and the operations of the plurality of pixels are controlled by each pixel group, and more specifically, the order of appearance of the subframe periods in each pixel group It is characterized by changing.

In addition to the above structure, the display device of the present invention includes a gate driver that controls a plurality of gate lines, and more specifically, a gate driver may be provided in each gate line group. In this case, gate drivers may be provided as many as the number of gate line groups. Such a plurality of gate drivers are provided to operate the plurality of pixels so that the order of appearance of the plurality of subframe periods is different.

In addition, a part of the conductive layer constituting the first gate line included in the first gate line group selected from the plurality of gate line groups has the second gate line group selected from the plurality of gate line groups. The conductive layer is included in the second gate line including the conductive layer.
In addition, a part of the conductive layer constituting at least one of the plurality of gate lines included in the first gate line group selected from the plurality of gate line groups is the second selected from the plurality of gate line groups. The gate line group overlaps with a conductive layer constituting at least one of a plurality of gate lines included in the gate line group.
Thus, the spatial dispersion can be more effectively performed by devising the arrangement of the gate lines.

Each of the plurality of pixels included in the display device of the present invention can express all the gradations of the total number of gradations in one frame period, and is selected by a video signal in the plurality of subframe periods. A pixel is turned on in the sub-frame period to express a desired gradation. Each of the plurality of pixels has at least one switching element. Each of the plurality of pixels includes a light emitting element, a switching transistor that controls input of a video signal to the pixel, and a driving transistor that controls a current value of the light emitting element.

The present invention provides a panel using the display device having the above structure. A panel is in a state in which a plurality of pixels are sealed, and in many cases, corresponds to a state in which a plurality of pixels are sealed with a pair of substrates.

The present invention provides a module using the display device configured as described above. A module is a state in which a printed circuit board is connected to the above-described panel, and a plurality of IC chips corresponding to a controller circuit and a power supply circuit are mounted on the printed circuit board.

The present invention provides a portable terminal using the display device configured as described above. The portable terminal corresponds to a cellular phone device (also referred to as a cellular phone or a cellular phone), a PDA, an electronic notebook, a portable game machine, and the like.

The present invention provides a digital camera using the display device configured as described above. The configuration of the display device of the present invention is used as a display unit of a digital camera.

The present invention provides a digital video camera using the display device configured as described above. As the display unit of the digital video camera, the configuration of the display device of the present invention is used.

The present invention provides a display using the display device configured as described above. The display corresponds to a display used as a personal computer monitor or an advertisement display monitor.

The present invention provides a television apparatus using the display device having the above structure.

According to the present invention having the above-described configuration, more effective spatial dispersion is possible, so that the generation of pseudo contours can be suppressed. In addition, since it is not necessary to increase the drive frequency of the drive circuit, the power consumption of the drive circuit does not increase and the reliability of the drive circuit is not impaired.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
The structure of the display device of the present invention will be described with reference to FIG. The display device of the present invention includes a pixel portion 102 provided with a plurality of pixels 101, a source driver 103, and gate drivers 104 and 105. The plurality of pixels 101 are arranged in a matrix from coordinates (1, 1) to coordinates (x, y) (x and y are natural numbers). The pixel portion 102 is provided with a plurality of source lines S1 to Sx, a plurality of gate lines G1 to Gy, and a plurality of power supply lines V1 to Vy. Power supply voltage is supplied.

The present invention is characterized in that a plurality of gate lines G1 to Gy are divided into a plurality of gate line groups. In addition, the pixel 101 is divided into a plurality of pixel groups. Each pixel group corresponds to each gate line group. More specifically, pixels including transistors connected to the gate lines of the same gate line group are the same pixel group.
Note that a gate driver for scanning a gate line is preferably provided for each gate line group, but may be shared by a plurality of gate line groups. When a gate driver is shared by a plurality of gate line groups, it is necessary to provide a switching circuit that switches supply of the output of the gate driver. The plurality of gate drivers are provided to operate the plurality of pixels so that the order of appearance of the plurality of subframe periods is different.

Further, the present invention is characterized in that control of a plurality of pixels is performed independently in each pixel group, and specifically, the order of appearance of subframe periods is changed in each pixel group. .
In other words, the present invention includes at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which a plurality of subframe periods appear in a second order in one frame period; It is characterized by having. For example, when one frame period is divided into three subframe periods, the first pixel appears in the order of the first subframe period, the second subframe period, and the third subframe period. In the second pixel, the third subframe period, the second subframe period, and the first subframe period appear in this order. The plurality of gate lines include at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected.
The present invention having the above features can realize spatial dispersion and suppress the generation of pseudo contours.

In this embodiment, a mode in which a plurality of gate lines G1 to Gy are divided into two gate line groups and a gate driver is provided in each gate line group will be described. Specifically, a plurality of gate lines G1, G3,..., G (y−1) arranged in odd rows are set as one gate line group, and a plurality of gate lines G2 arranged in even rows. , G4,..., Gy are divided into another gate line group, and two gate drivers 104 for scanning odd-numbered gate lines and gate drivers 105 for scanning even-numbered gate lines are provided. A form is demonstrated. The gate driver 104 and the gate driver 105 operate independently except for the limitation by the source driver 103.

In this embodiment, the pixel 101 including transistors connected to the plurality of gate lines G1, G3,..., G (y−1) is defined as one pixel group, and the plurality of gate lines G2, G4,. .., Pixel 101 including the transistor connected to Gy is another pixel group. Control of the plurality of pixels 101 is performed independently for each pixel group.

Next, the structure of the gate driver 104 included in the display device of the present invention will be described with reference to FIG. Each of the gate drivers 104 includes shift registers 202 and 203, AND circuits 204 and 205, an OR circuit 206, and a buffer circuit 207.

The outputs of the shift registers 202 and 203 are input to AND circuits 204 and 205, respectively. The pulse width control signals PWC 1 and PWC 2 are signals for preventing the output periods of the AND circuits 204 and 205 from overlapping, and the outputs of the AND circuits 204 and 205 are input to the OR circuit 206. The output pulse of the OR circuit 206 is current-amplified by the buffer circuit 207 and is output to the gate lines G1, G3,..., G (y−1). The gate driver 105 has the same configuration as that of the gate driver 104 except that the output of the buffer circuit 207 is output to the gate lines G2, G4,.

Next, the structure of the shift registers 202 and 203 will be described with reference to FIG. The shift registers 202 and 203 have a plurality of flip-flop circuits 208 and an AND circuit 209. The shift registers 202 and 203 can have the same configuration, but may have different configurations.

Various control signals such as a clock signal (GCLK) and a start pulse signal (GSP) are input to the shift register 210. The output pulse of the previous stage having the length of one cycle of the clock signal is shifted by the flip-flop circuit 208 by the length of the half cycle of the clock signal and output. Next, an AND circuit 209 ANDs the output pulse and the previous stage output to generate a pulse having a half cycle length of the clock signal.

Next, the structure of the source driver 103 included in the display device of the present invention will be described with reference to FIG. The source driver 103 includes a shift register 210, latch circuits 211 and 212, and a selection circuit 213.

Various control signals such as a clock signal (CLK) and a start pulse signal (SP) are input to the shift register 210. When the clock signal (CLK) and the start pulse signal (SP) are input, a timing signal is generated in the shift register 210. The generated timing signals are sequentially input to the first stage latch circuit 211. When a timing signal is input to the latch circuit 211, video signals are sequentially written and held in the latch circuit 211 in synchronization with the pulse of the timing signal. Note that although video signals are sequentially written in the latch circuit 211 in this embodiment mode, the present invention is not limited to this structure. A so-called divided drive may be performed in which the latch circuits 211 of a plurality of stages are divided into several groups and video signals are input in parallel for each group. Further, a period until one video signal is completely written to the latch circuits of all stages of the latch circuit 211 is referred to as a row selection period. Actually, the row selection period may include a period in which a horizontal blanking period is added to the row selection period. When the row selection period ends, a latch signal corresponding to one of the control signals is supplied to the second-stage latch circuit 212, and the video signal held in the latch circuit 211 in synchronization with the latch signal is 212 are written all at once. In the latch circuit 211 that has finished sending the video signal to the latch circuit 212, the video signal of the next bit is sequentially written in synchronization with the timing signal from the shift register 210 again. During the second row selection period of one row, a video signal written and held in the latch circuit 212 is input to the selection circuit 213. The selection circuit 213 selects whether to output a video signal or an erasing signal, and the selected video signal or erasing signal is input to the pixel portion 102. Note that the video signal output from the source driver 103 is a signal for the pixel 101 to display an image in the pixel portion 102. Further, the erase signal output from the source driver 103 is a signal supplied to the pixel 101 when setting a lighting period that is not an integral multiple of one horizontal period.

The structure of the display device of the present invention is not limited to the above structure, and the type, number, and arrangement of wirings for supplying various signal voltages or power supply voltages to each pixel 101 are appropriately changed according to the structure of the pixel 101. Is possible. Further, the configuration of the source driver 103 and the gate drivers 104 and 105 is not limited to the above configuration, and can be changed as appropriate in accordance with the configuration of the pixel portion 102. The shift registers 202, 203, and 210 are circuits that output timing signals for selecting a plurality of gate lines in order. Instead of the shift registers 202, 203, and 210, a plurality of gate lines are randomly selected. A circuit (for example, a decoder) that outputs a timing signal may be used. The source driver 103 and the gate drivers 104 and 105 may be formed on the same substrate as the pixel portion 102 or may be formed on different substrates.

Next, a specific configuration of the pixel portion 102 will be described with reference to FIG. Each of the plurality of pixels 101 included in the pixel portion 102 includes a light-emitting element 804, a switching transistor 805, a driving transistor 806, and a capacitor 807.

A video signal and an erase signal are input by the source driver 103 to the source line Sn (n is a natural number, 1 ≦ n ≦ x). The switching transistor 805 controls the supply of the potential of the video signal or the erasing signal to the gate electrode of the driving transistor 806 in accordance with a selection signal input to the gate line Gk (k is a natural number). The driving transistor 806 controls supply of current to the light-emitting element 804 in accordance with the potential of the video signal or the erase signal. Switching of the switching transistor 805 is controlled by a selection signal input to the gate line Gk. The capacitor 807 holds the gate voltage of the driving transistor 806. Note that in the case where the gate voltage of the driving transistor 806 can be covered by the gate capacitance of the driving transistor 806 or other parasitic capacitance, the capacitor 807 is not necessarily provided.

Next, arrangement of gate lines in the pixel portion 102 will be described. In the pixel unit 102 in which normal progressive driving is adopted, the gate lines arranged in the odd-numbered rows (G (2k−1) rows) are arranged in the odd-numbered rows ((2k−1) rows). Connected to the switching transistor 805 of the pixel 101 (k = 1, 2,..., Y / 2). The gate lines arranged in the even-numbered rows (G (2k) rows) are connected to the switching transistors 805 of the pixels 101 arranged in the even-numbered rows ((2k) rows). That is, the odd-numbered gate line is connected to the switching transistor 805 of the odd-numbered pixel, and the even-numbered gate line is connected to the switching transistor 805 of the even-numbered pixel.

On the other hand, in the pixel portion 102 of the display device of the present invention, the gate lines arranged in the odd-numbered rows (G (2k−1) th row) are the odd-numbered columns ((n−1) th row) and the odd-numbered rows. The switching transistor 805 of the pixel 101 arranged in the ((2k−1) th row) and the switching transistor 805 of the pixel 101 in the even-numbered row (n-th column) and the even-numbered row (2k-th row). .
The gate lines arranged in the even-numbered rows (G (2k) rows) are switches of the pixels 101 arranged in the odd-numbered rows ((2k-1) rows) in the even-numbered columns (n-th column). And the switching transistor 805 of the pixel 101 arranged in the even-numbered row (2k row) in the odd-numbered column ((n-1) th column).
That is, in the present invention, the gate lines in the odd rows are connected to the switching transistors 805 included in the pixels 101 arranged at the coordinates (odd number, odd number) and the coordinates (even number, even number). The even-numbered gate line is connected to the switching transistor 805 included in the pixel 101 arranged at coordinates (even, odd) and coordinates (odd, even). In order to connect the gate line and the pixel 101 as described above, a part of the conductive layer constituting the gate line of the odd-numbered row (G (2k-1) th row) is formed in the even-numbered row (2k-th row). It overlaps with a part of the conductive layer constituting the gate line. Thus, by devising the arrangement of the gate lines, the spatial dispersion can be more effectively performed and the generation of the pseudo contour can be suppressed.

Note that the arrangement of the gate lines is not limited to this method. For example, even if the switching transistor 805 of the pixel 101 arranged in another row for every three pixels is turned on and off in accordance with three subpixels corresponding to any of red, green, and blue included in the pixel 101, Good.

Next, an example of a timing chart in the case of performing 4-bit display (display of the total number of gradations 32) in one frame period will be described with reference to FIG. One frame period is divided into four subframe periods.

A period Tw1A to Tw4A is a period during which the gate line of the G (2k-1) th row is scanned, and represents a period during which the source driver 103 supplies a video signal to the pixel 101 (see FIG. 4, timing chart 401). In each of the periods Tw1A to Tw4A, the number of data for one row is sampled y / 2 times, and the sampled data is output to the source line. The period Tw1A is a period for outputting the least significant bit (first bit) data, the period Tw2A is a period for outputting the second bit data from the bottom, and the period Tw3A is the third bit data from the bottom. This is a period for outputting, and a period Tw4A is a period for outputting the most significant bit (fourth bit) data.

A period Tw1B to Tw4B is a period during which the gate line of the G (2k) th row is scanned, and represents a period during which the source driver 103 supplies a video signal to the pixel 101 (see FIG. 4, timing chart 402). In each of the periods Tw1B to Tw4B, the number of data for one row is sampled y / 2 times, and the sampled data is output to the source line. The period Tw1B is a period for outputting the least significant bit (first bit) data, the period Tw2B is a period for outputting the second bit data from the bottom, and the period Tw3B is the third bit data from the bottom. The period Tw4B is a period for outputting the most significant bit (fourth bit) data.

A period Te1A to Te2A is a period during which the gate line of the G (2k−1) th row is scanned, and represents a period during which the source driver 103 supplies an erasing signal to the pixel 101 (see the timing chart 403 in FIG. 4). In each of the periods Te1A to Te2A, the number of pixels corresponding to y / 2 rows are turned off. The period Te1A corresponds to the erasure of the least significant bit data, and the period Te4A corresponds to the erasure of the second bit from the bottom.

A period Te1B to Te2B is a period during which the gate line of the G (2k) -th row is scanned and represents a period during which the source driver 103 supplies an erasing signal to the pixel 101 (see FIG. 4, timing chart 404). In each of the periods Te1B to Te2B, the number of pixels corresponding to y / 2 rows are set to a non-lighting state. The period Te1B corresponds to erasure of the least significant bit data, and the period Te4B corresponds to erasure of the second bit from the bottom.

The periods Ti1A to Ti4A and the periods Ti1B to Ti4B represent periods in which the pixels 101 are actually turned on. Periods Ti1A to Ti4A represent periods in which the pixels 101 are turned on in accordance with the video signals output to the source lines in the periods Tw1A to Tw4A. Periods Ti1B to Ti4B represent periods in which the pixels 101 are lit according to the video signal output to the source line in the periods Tw1B to Tw4B.

Therefore, in FIG. 4, the lighting timing chart 405 of the pixel 101 including the transistor switched by the first row gate line G1 and the (y−1) th row gate line G (y−1) are switched. A lighting timing chart 416 of the pixel 101 including a transistor is shown. In addition, a lighting timing chart 417 of the pixel 101 including the transistor switched by the gate line G2 in the second row and a lighting timing chart 418 of the pixel 101 including the transistor switched by the gate line Gy in the y row are shown. . Thus, in the two groups, the same bit data lighting period, that is, the period Ti1A and the period Ti1B, the period Ti2A and the period Ti2B, the period Ti3A and the period Ti3B, and the period Ti4A and the period Ti4B appear in one frame period. Since the timing is different, the present invention can realize spatial dispersion and suppress the generation of pseudo contours.

Further, one frame period is divided into a plurality of subframe periods, and each of the plurality of subframe periods has a writing period and a lighting period, but the total writing period in one frame period of the display device of the present invention is: Since it is not different from the total writing period in one frame period of a simple progressive driving panel, it is not necessary to increase the driving frequency. Therefore, the frequency of the drive circuit does not increase, and the reliability of the drive circuit is not impaired.
(Embodiment 2)

The structure of the display device of the present invention will be described with reference to FIG. The display device of the present invention includes a pixel portion 102 provided with a plurality of pixels 101, a source driver 103, and gate drivers 104 and 105. The pixel portion 102 includes a plurality of source lines Sn (n is a natural number, 1 ≦ n ≦ y), a plurality of gate lines Ga (2k), Gb (2k) (k is a natural number, 1 ≦ k ≦ y / 2), A plurality of power supply lines Vn are provided, and voltages of various signals or power supply voltages are supplied to each pixel 101 through these wirings.

The present invention is characterized in that a plurality of gate lines are divided into a plurality of gate line groups. A plurality of pixels 101 are divided into a plurality of pixel groups corresponding to the plurality of gate line groups. The plurality of pixels are controlled independently in each pixel group. Specifically, the order of appearance of subframe periods is changed in each pixel group.

In this embodiment, a mode in which a plurality of gate lines Ga (2k) and Gb (2k) are divided into two groups and a gate driver is provided in each group will be described. Specifically, a plurality of gate lines Ga1, Ga3,..., Ga (2k−1), Ga (2k + 1),. Gb1, Gb3,..., Gb (2k-1), Gb (2k + 1),..., Gb (y-1) as one group, and a plurality of gate lines Ga2, Ga4 arranged in even rows , ..., Ga (2k), Ga (2K + 2), ..., Gay, and gate lines Gb2, Gb4, ..., Gb (2k), Gb (2K + 2), ..., Gby One group. Two gate drivers 104 for scanning odd-numbered gate lines and gate drivers 105 for scanning even-numbered gate lines are provided.

The present invention is characterized in that the control of each pixel group is performed independently in each pixel group, and specifically, the order of appearance of subframe periods is changed in each pixel group. And
In other words, the present invention includes at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which a plurality of subframe periods appear in a second order in one frame period; It is characterized by having. The plurality of gate lines include at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected.

The pixel 101 includes a light-emitting element 804, a switching transistor 805, a driving transistor 806, a capacitor 807, and an erasing transistor 808. This configuration is obtained by adding an erasing transistor 808 to the configuration shown in FIG. With the arrangement of the erasing transistor 808, a period in which no current flows through the light-emitting element 804 can be forcibly formed, so that the duty ratio can be improved.

Next, the configuration of the gate driver 104 will be described with reference to FIG. Each of the gate drivers 104 includes a shift register 701, a selection circuit 702, a switch 703, a level shifter circuit 704, and a buffer circuit 705. A level shifter circuit 704 and a buffer circuit 705 are provided corresponding to each gate line.

The shift register 701 sequentially outputs timing pulses to a lower circuit in accordance with a control signal (such as a clock signal) supplied from the outside. The selection circuit 702 is a circuit that supplies a control signal to the switch 703. The switch is brought into conduction with the gate line Ga1 or the gate line Gb1 in accordance with a signal output from the selection circuit 702. The configuration of the gate driver 105 is the same as the configuration of the gate driver 104 except that the output of the buffer circuit 705 is output to the gate lines Ga2, Ga4,..., Gan, and the gate lines Gb2, Gb4,. It is.

This embodiment mode can be freely combined with the above embodiment modes. Further, in this embodiment, a method realized by switching the lighting or non-lighting state of a pixel in a subframe period with the same lighting period, or a pixel between a plurality of subframe periods having the same sum of lighting periods You may use in combination with the method implement | achieved by replacing the lighting or non-lighting state of.
(Embodiment 3)

A panel mounted with a pixel portion 40, a first gate driver 41, a second gate driver, and a source driver 43, which is an embodiment of the display device of the present invention, will be described. Over the substrate 20, a pixel portion 40 including a plurality of pixels including the light-emitting element 13, a first gate driver 41, a second gate driver 42, a source driver 43, and a connection film 407 are provided (see FIG. 7A). ). The connection film 407 is connected to an external circuit (IC chip).

FIG. 7B is a cross-sectional view taken along the line AB of the panel, and shows a driving transistor 12, a light emitting element 13, a capacitor 16 provided in the pixel portion 40, and a CMOS circuit 410 provided in the source driver 43. .
A sealant 408 is provided around the pixel portion 40, the first gate driver 41, the second gate driver 42, and the source driver 43, and the light emitting element 13 is sealed with the sealant 408 and the counter substrate 406. This sealing process is a process for protecting the light emitting element 13 from moisture. Here, a method of sealing with a cover material (glass, ceramics, plastic, metal, etc.) is used, but a thermosetting resin or ultraviolet light is used. A method of sealing with a curable resin or a method of sealing with a thin film having a high barrier ability such as a metal oxide or a nitride may be used. The element formed on the substrate 20 is preferably formed of a crystalline semiconductor (polysilicon) having favorable characteristics such as mobility as compared with an amorphous semiconductor, so that monolithic formation on the same surface can be achieved. Realized. Since the number of external ICs to be connected is reduced, the panel having the above configuration can be made small, light, and thin.

In the configuration shown in FIG. 7, the pixel electrode of the light-emitting element 13 has a light-transmitting property, and the counter electrode of the light-emitting element 13 has a light-shielding property. Therefore, the light emitting element 13 performs bottom emission.
As a structure different from the above, the pixel electrode of the light-emitting element 13 may have a light-shielding property, and the counter electrode of the light-emitting element 13 may have a light-transmitting property (see FIG. 8A). In this case, the light emitting element 13 performs top emission.

Further, as a structure different from the above, there are cases where both the pixel electrode of the light-emitting element 13 and the counter electrode of the light-emitting element 13 have a light-transmitting property (see FIG. 8B). In this case, the light emitting element 13 performs double-sided emission.

In the configuration illustrated in FIG. 7, an insulating layer is provided over the source / drain wiring of the driving transistor 12, and the pixel electrode of the light-emitting element 13 is provided over the insulating layer. However, the present invention is not limited to this configuration, and the pixel electrode of the light-emitting element 13 is provided in the same layer as the source / drain wiring of the driving transistor 12 as in the configuration shown in FIGS. Also good. In addition, in the portion where the source / drain wiring of the driving transistor 12 and the pixel electrode of the light emitting element 13 are stacked, as shown in FIG. The pixel electrode of the light emitting element 13 may be the lower layer and the source / drain wiring of the driving transistor 12 may be the upper layer, as shown in FIG. 8B.

Note that the pixel portion 40 is constituted by a TFT using an amorphous semiconductor (amorphous silicon) formed on an insulating surface as a channel portion, and includes a first gate driver 41, a second gate driver, and a source driver 43. May be constituted by an IC chip. The IC chip may be bonded onto the substrate 20 by the COG method, or may be bonded to the connection film 407 connected to the substrate 20. An amorphous semiconductor can be easily formed on a large-area substrate by using the CVD method and does not require a crystallization step, so that an inexpensive panel can be provided. At this time, if a conductive layer is formed by a droplet discharge method typified by an ink jet method, a cheaper panel can be provided.

The light-emitting element included in the display device of the present invention includes, in its category, an element whose luminance is controlled by current or voltage. Specifically, the light-emitting element is used for OLED (Organic Light Emitting Diode) and FED (Field Emission Display). MIM type electron source elements (electron emitting elements) and the like are included. An OLED that is one of light-emitting elements includes a layer containing an electroluminescent material (hereinafter, abbreviated as an electroluminescent layer) from which luminescence generated by applying an electric field is obtained, an anode, and a cathode. Yes. The electroluminescent layer is provided between the anode and the cathode, and is composed of a single layer or a plurality of layers. In some cases, these layers contain an inorganic compound. Luminescence in the electroluminescent layer includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

As the transistor used in the display device of the present invention, a polycrystalline semiconductor, a microcrystalline semiconductor (including a semi-amorphous semiconductor), or a thin film transistor using an amorphous semiconductor can be used, but the transistor is used in the display device of the present invention. The transistor is not limited to a thin film transistor. A transistor formed using single crystal silicon or a transistor using SOI may be used. Further, a transistor using an organic semiconductor or a transistor using carbon nanotubes may be used. In addition, the transistor provided in the pixel of the display device of the present invention may have a single gate structure, a double gate structure, or a multi-gate structure having more gate electrodes.
(Embodiment 4)

One mode of an electronic device using the display device of the present invention will be described with reference to FIGS. The electronic device illustrated here is a mobile phone device, and includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 9). The panel 2701 has a pixel portion in which a plurality of pixels are arranged in a matrix, and the pixel portion is sealed with a pair of substrates. The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of IC chips corresponding to a central processing circuit (CPU), a controller circuit, and a power supply circuit are mounted on the printed wiring board 2703. A module corresponds to a state in which a printed wiring board 2703 is mounted on a panel.

The panel 2701 is integrated with the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel portion included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone device, and the electronic device according to this embodiment can be transformed into various modes depending on functions and uses. Therefore, an example of an aspect of the electronic device will be described below with reference to FIG.

A cellular phone device which is a portable terminal includes a pixel portion 9102 and the like (see FIG. 10A). A portable game device which is a portable terminal includes a pixel portion 9801 and the like (see FIG. 10B). The digital video camera includes pixel portions 9701, 9702, and the like (see FIG. 10C). A PDA (personal digital assistant) which is a portable information terminal includes a pixel portion 9201 and the like (see FIG. 10D). The television device includes a pixel portion 9301 and the like (see FIG. 10E). The monitor device includes a pixel portion 9401 and the like (see FIG. 10F).

The present invention relates to a mobile phone device (also referred to as a mobile phone or a mobile phone) which is a mobile terminal, a PDA, an electronic notebook, a portable game machine, a television device (also referred to as a television or a television receiver), a display (a monitor device). It can also be applied to various electronic devices such as a digital camera, a digital video camera, a sound reproduction device such as a car audio, and a home game machine. This embodiment mode can be freely combined with the above embodiment modes.

FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 9 illustrates an electronic device. FIG. 9 illustrates an electronic device.

Claims (15)

Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines include at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. Display device. 2. The display device according to claim 1, further comprising: a first gate driver that controls at least the first gate line; and a second gate driver that controls the second gate line. 2. The display device according to claim 1, wherein a part of the conductive layer constituting the first gate line overlaps with the second conductive layer constituting the second gate line. A plurality of gate lines and a plurality of pixels;
The plurality of gate lines are divided into a plurality of gate line groups,
The plurality of pixels are divided into a plurality of pixel groups corresponding to each of the gate line groups,
The order of appearance of the plurality of subframe periods in the first pixel group selected from the plurality of pixel groups is the order of appearance of the plurality of subframe periods in the second pixel group selected from the plurality of pixel groups. A display device characterized by being different from the above. In claim 4,
The conductive layer constituting at least one of the plurality of gate lines included in the first gate line group selected from the plurality of gate line groups is a second gate line selected from the plurality of gate line groups. A display device characterized by overlapping with a conductive layer constituting at least one of a plurality of gate lines included in a group. In claim 4,
A display device comprising a plurality of gate drivers for controlling each of the plurality of gate line groups. In any one of Claims 1 thru | or 6,
Each of the plurality of pixels has at least one switching element. In any one of Claims 1 thru | or 6,
Each of the plurality of pixels includes a light emitting element, a switching transistor for controlling input of a video signal to the pixel, and a driving transistor for controlling a current value of the light emitting element. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A panel characterized by using. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A module characterized by being used. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A portable terminal characterized by being used. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A digital camera characterized by using. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A digital video camera characterized by being used. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A display characterized by being used. Having a plurality of pixels and a plurality of gate lines;
The plurality of pixels include at least a first pixel in which a plurality of subframe periods appear in a first order, and a second pixel in which the plurality of subframe periods appear in a second order;
The plurality of gate lines includes a display device having at least a first gate line to which a transistor included in the first pixel is connected and a second gate line to which a transistor included in the second pixel is connected. A television device characterized by being used.

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