JP2006157335A - Analog front-end circuit for image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To amplify an image sensor output signal at a high amplification factor with low power consumption and high quality, and to enable adaptation to high-speed operation. <P>SOLUTION: A correlative double-sampling amplifying circuit 15 is constituted by cascading two stages of amplifying circuits 1 and 2 having the same constitution and take partial charge of the amplification factor, respectively. The amplifying circuits 1 and 2 are each achieved by an inverter type amplifier comprising a small number of elements and the amplification factor of the amplifying circuit 2 of the second stage is set low to secure offset removing performance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for amplifying an image sensor output signal with high quality in an analog front end circuit when a camera system is configured using various image sensors such as a CCD and a CMOS sensor.

  Conventionally, as a pre-process for performing various image processing of output signals of an image sensor such as a CCD or CMOS sensor by digital signal processing in a camera system, a correlated double sampling circuit (hereinafter referred to as a CDS circuit) is generally used. An analog front-end circuit having a variable amplifier and an AD converter has been used.

  The role of the CDS circuit is to remove the low-frequency capacitive noise contained in the image sensor output signal by calculating the difference voltage between the black level during the feedthrough period of the image sensor output signal and the signal level during the charge signal output period. The signal is extracted as a signal, and at that time, basic amplification is also performed to enable good signal amplification with a variable amplifier at the subsequent stage.

  The output signal of the CDS circuit is appropriately amplified by a variable amplifier so as to be optimal for the input dynamic range of the AD converter, and then converted into a digital signal by the AD converter. The output of the variable amplifier is clamped to an appropriate voltage by clamp control so that the digital signal value when the image sensor is optically shut off matches the black level value of the system.

  On the other hand, the image sensor output signal outputs a certain amplitude as an offset when optically blocked. If this offset is large, when high amplification is applied by the variable amplifier at the rear stage of the CDS circuit, the follow-up performance of the clamp control is deteriorated, causing random fluctuations in the black level of the processing system. Cause noise. A technique for avoiding this problem has already been proposed (see Patent Document 1).

  According to this proposal, an offset removal is applied to the input signal of the CDS circuit so as to cancel the amplitude of the output signal of the CDS circuit in an optically interrupted state, thereby making it variable for the signal from which the offset is removed. It is amplified and the stability of clamp control can be maintained.

  The amplification factor of the CDS circuit necessary for optimally processing the image sensor output signal is usually about 4 dB to 6 dB, and this amplification factor is such that the saturation output voltage of the conventional image sensor is about 500 mV to 1 V, The amplification is determined to be optimal for the dynamic range of the subsequent analog processing.

  In recent years, a high number of pixels of several million pixels has been used as the number of pixels of an image sensor, and the demand for higher image quality has increased with the refinement of images. The operating frequency is, for example, 19 MHz for 2 million pixels and about 25 MHz for 3 million pixels. As the number of pixels increases, it is necessary to increase the frequency band of each amplifier constituting the analog front-end circuit. In a system using a conventional image sensor, the CDS circuit has an amplification factor that is not so high as described above. Therefore, a CDS circuit that satisfies the S / N ratio and the frequency characteristics for high-speed processing accompanying an increase in the number of pixels. The realization of is easy without significant disadvantages.

  On the other hand, recently, camera functions have been installed in mobile devices, and in addition to improving image quality, there has been a strong demand for low power consumption. To meet these demands, we have specialized in low power consumption. A new high-pixel image sensor has been developed.

  The main features of this image sensor are that it has a higher sensitivity and lower power consumption than a CCD, and an output signal amplitude of 100 mV or less, which is smaller than that of a conventional image sensor. Therefore, in order to construct a system using this image sensor, it is first necessary to have a high amplification of about 18 dB as the amplification factor of the CDS circuit.

Therefore, realization of a low power consumption and low noise CDS circuit capable of responding to a system operating frequency of several million pixels with a high amplification factor has become a concern.
International Publication No. 99/23819 Pamphlet

  As a method that suppresses the degradation of the S / N ratio of the image sensor and supports high-speed operation while raising the amplification factor especially higher than that of the conventional CDS circuit, high-performance amplification at the first stage of the conventional analog front-end circuit A method of adding a circuit is conceivable.

  However, it is difficult to realize with a simple circuit configuration due to the high required performance, and there are great demerits due to the increase in circuit scale and power consumption of the amplifier circuit.

  In addition, in the method of simply increasing the amplification factor of the conventional CDS circuit, it is difficult to ensure the operating frequency characteristics under the constraint of low power, and the output settling deteriorates. Therefore, at high speed operation, randomness is caused by jitter at the sampling point of the variable amplifier. Causes noise. In addition, even if the above-described offset removal means, which is a conventional image quality improvement technique, is provided, the feedback loop gain for offset removal increases as the amplification factor of the CDS circuit increases, and the accuracy of the offset removal means remaining at the input of the CDS circuit. The following slight error is amplified by the amplification factor of the CDS circuit, and the stability of feedback deteriorates. Therefore, there is a possibility that an offset that cannot be ignored remains in the output of the CDS circuit. Then, when the set amplification factor of the subsequent stage variable amplifier is high, the tracking stability of the clamp control may be impaired.

  The present invention proposes an analog front-end circuit that realizes a CDS circuit with a high amplification factor that solves these problems while suppressing an increase in power consumption and circuit scale as compared with a conventional method.

  In order to solve the above problems, the analog front end circuit according to the present invention has a two-stage CDS circuit. That is, a first amplifier circuit that amplifies and outputs a difference voltage between the black level of the feedthrough period of the output signal of the image sensor and the signal level of the charge signal output period at a predetermined amplification rate, and the first amplifier circuit In a signal output, a difference signal between a first voltage level corresponding to the black level in the feedthrough period of the output signal of the image sensor and a second voltage level corresponding to the signal level in the charge signal output period is a predetermined amplification factor. A second amplifier circuit that amplifies and outputs a predetermined reference voltage as a reference is connected in cascade.

  The first and second amplifier circuits are configured such that the voltage difference between the black level in the feedthrough period of the output signal of the image sensor and the signal level in the charge signal output period when the image sensor is optically cut off. The offset removing means for removing the offset voltage corresponding to the above is combined with the CDS circuit.

  Further, the first and second CDS circuits have the same circuit configuration, and are configured to have as few elements as possible in order to reduce noise particularly.

  As another implementation method, the amplification factor of the second amplification circuit is set lower than the amplification factor of the first amplification circuit, the offset removal means of the first amplification circuit is omitted, and only the second amplification circuit is offset. There is also a method of including removal means.

  The newly developed image sensor includes a type in which the output signal waveform is output downward from the reference voltage and a type in which the output signal waveform is output upward. A method corresponding to this utilizes the fact that polarity inversion is possible by switching the positive and negative of the differential input of a general differential amplifier, and the difference signal between the signal output of the CDS circuit and the predetermined reference voltage is obtained. A variable amplifier that amplifies at a variable amplification factor is composed of a differential amplifier with an input polarity switching function.

  According to the analog front end circuit of the present invention, even when the amplification factor is increased as compared with the case of the conventional image sensor, the amplification factor per stage is increased by the first and second amplification circuits of the CDS circuit. And can be operated at high speed with low power consumption.

  Further, the deterioration of the offset removal performance due to the increase in the amplification factor of the CDS circuit can maintain the same performance as the conventional system, and a system that can fully utilize the characteristics of the image sensor can be configured.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration example of an analog front end circuit according to the present invention. In FIG. 1, the correlated double sampling amplifier circuit 15 includes a first stage amplifier circuit 1 and a second stage amplifier circuit 2. The CDS circuit 4a constituting the first stage amplifier circuit 1 amplifies the difference voltage between the black level in the feedthrough period of the output signal of the image sensor 11 and the signal level in the charge signal output period with a predetermined amplification factor. First, the first-stage offset removal circuit 5a performs the black level and charge signal output period of the feedthrough period of the output signal of the image sensor 11 from the output signal of the first-stage CDS circuit 4a in a state where the image sensor 11 is optically cut off. The offset voltage corresponding to the difference voltage from the signal level of the first is detected, and the offset is removed from the input signal of the first stage CDS circuit 4a. At this time, the offset removal circuit 5b constituting the second stage amplifier circuit 2 also simultaneously receives the voltage level corresponding to the black level of the feedthrough period of the output signal of the previous stage CDS circuit 4a from the output signal of the second stage CDS circuit 4b and the charge signal. An offset voltage corresponding to the voltage difference from the voltage level corresponding to the signal level in the output period is detected, and the offset is removed from the input signal of the second-stage CDS circuit 4b.

  The amplification factor of the correlated double sampling amplifier circuit 15 is obtained by multiplying the amplification factors of the two CDS circuits 4a and 4b. The amplification factor of the first stage CDS circuit 4a is multiplied by the amplification factor of the second stage CDS circuit 4b. Assign as high as possible.

  The signal from which the offset is removed by the first-stage offset removal circuit 5a is input to the second-stage CDS circuit 4b. However, since the amplification factor of the first-stage CDS circuit 4a is very high, the offset removal performance is deteriorated and slightly increased. An offset remains. However, since the amplification factor of the second stage CDS circuit 4b is low, the subsequent stage offset removal circuit 5b functions well, and the output offset of the second stage CDS circuit 4b can be minimized.

  The output signal of the correlated double sampling amplifier circuit 15 is amplified by the variable amplifier (GCA) 3 to the optimum amplitude for the input dynamic range of the AD converter (ADC) 12, and the AD converter 12 corresponding to the black level of the image sensor 11 is amplified. The output of the variable amplifier 3 is clamped to a desired voltage by the clamp circuit 14 so that the output value matches the desired digital value.

  FIG. 2 shows a detailed configuration of the first-stage and second-stage amplifier circuits 1 and 2 in FIG. As an actual application method of the correlated double sampling amplifier circuit 15 of FIG. 1, first, the output signal of the image sensor 11 is first received by a capacitor 13 as an external component, and the AC component is transmitted by this external capacitor 13. It is. The output signal of the capacitor 13 is biased to an appropriate DC voltage by the bias circuit 9 and input to the first stage amplifier circuit 1 via the source follower buffer 10.

  The CDS circuit 4 a in the first stage amplifier circuit 1 is an inverter type switched capacitor circuit including a sampling capacitor Cs 1, a feedback capacitor Cf 1, an inverter type amplifier 6 a, switches S 1 to S 3, and a reference voltage source 7. By using an inverter type circuit with a very small number of elements, an effect of reducing power and noise can be obtained. An offset removal capacitor Coff1 is interposed between the output of the offset removal circuit 5a and the input of the inverter type amplifier 6a.

  The CDS circuit 4b in the second stage amplifier circuit 2 is also a similar inverter type switched capacitor circuit, where Cs2 is a sampling capacitor, Cf2 is a feedback capacitor, 6b is an inverter type amplifier, S4 to S6 are switches, and 8 is a reference voltage source. It is. An offset removal capacitor Coff2 is interposed between the output of the offset removal circuit 5b and the input of the inverter type amplifier 6b.

  FIG. 3 is a timing chart showing the operation of the circuit of FIG. Here, the control of the switches S1 to S6 is closed in the H period and opened in the L period.

  The switch S2 is opened and the switches S1 and S3 are closed within the feedthrough period of the input N1 of the first stage amplifier circuit 1. Therefore, since the input and output of the first stage inverter type amplifier 6a are short-circuited via S3, the input N2 of the second stage amplifier circuit 2 is balanced with the switching voltage Vb of the first stage inverter type amplifier 6a. The sampling capacitor Cs1 holds a charge corresponding to the difference voltage between the black level and Vb. The feedback capacitor Cf1 holds a charge corresponding to the voltage difference between the voltage of the reference voltage source 7 and Vb.

  Next, when S1 and S3 are opened and S2 is closed, the amplification operation of the inverter-type amplifier 6a becomes possible, and charge redistribution of Cs1 and Cf1 acts according to the voltage change amount of N1, and the signal of N1 is applied to N2. A signal whose polarity is inverted and is amplified at a ratio of Cs1 / Cf1 is output as an input N2 of the second-stage amplifier circuit 2 with reference to the voltage of the reference voltage source 7.

  On the other hand, the first-stage offset removal circuit 5a detects the difference voltage between the signal level of the charge signal output period of N2 and N4 as an offset when the image sensor 11 is optically cut off, and removes the offset from the signal amplitude of N1. It works to remove the offset by extracting the charge through the capacitor Coff1. The second-stage offset removal circuit 5b detects the difference voltage between the signal level of the charge signal output period of N3 and N5 as an offset when the image sensor 11 is optically cut off, and removes the offset from the signal amplitude of N2. It works to remove the offset by removing the charge through the capacitor Coff2.

  Since the second-stage amplifier circuit 2 has the same circuit configuration as the first-stage amplifier circuit 1, the operation mechanism is the same as described above. However, since the first stage amplifier circuit 1 and the second stage amplifier circuit 2 are operated at the same switch control timing, both ends of the sampling capacitor Cs2 of the second stage amplifier circuit 2 are connected to the inverter switching voltage Vb during the feedthrough period. Is different from the state of Cs1. The amplification factor (Cs2 / Cf2) of the second-stage amplifier circuit 2 is set as small as possible from the amplification factor (Cs1 / Cf1) of the first-stage amplifier circuit 1.

  By the correlated double sampling amplifier circuit 15 having the above-described two-stage configuration, the signal amplitude of the image sensor 11 is multiplied by (Cs1 / Cf1) × (Cs2 / Cf2) and the offset is removed, and the second-stage amplifier circuit The voltage of the two reference voltage sources 8 is applied to the input of the variable amplifier 3. The variable amplifier 3 amplifies the difference between the two to an optimum amplitude for the input dynamic range of the AD converter 12.

  FIG. 4 shows a configuration example of the variable amplifier 3 in FIGS. 1 and 2. The variable amplifier 3 in FIG. 4 includes switches Sp and Sn for switching between positive and negative of an input signal and a differential amplifier AMP. When the polarity of the output signal of the image sensor 11 is input with a reverse polarity, This can be handled by switching the switches Sp and Sn.

  FIG. 5 shows a modification of the analog front end circuit of FIG. If it is clear that the black level offset is originally small as a characteristic of the image sensor 11, the offset removal circuit of the first stage amplifier circuit 1 can be omitted, and further, the circuit scale and power consumption can be reduced. According to FIG. 5, since the first stage amplifier circuit 1 does not include an offset removal circuit, unlike the embodiment of FIG. 1, a signal including an offset is input to the input of the second stage CDS circuit 4b. . However, in order not to degrade the performance of the offset removal circuit 5b in the second stage amplifier circuit 2, here too, as a shared assignment between the amplification factor of the first stage CDS circuit 4a and the amplification factor of the second stage CDS circuit 4b, two stages are used. The amplification factor of the eye CDS circuit 4b is set to be as low as possible. As a result, high amplification is possible while the offset removal functions well.

  FIG. 6 shows a detailed configuration of the first-stage and second-stage amplifier circuits 1 and 2 in FIG. The CDS circuits 4a and 4b constituting both amplifier circuits 1 and 2 are formed of inverter-type switched capacitor circuits as described above. The explanation of the operation is equivalent to that described above, and will be omitted.

  The present invention relates to analog processing in the process of converting the output of various image sensors such as CCD and CMOS sensors into digital signals, and enables signal amplification with low power consumption and high amplification factor. It can be applied to a camera system or the like.

It is a block diagram which shows the example of schematic structure of the analog front end circuit based on this invention. FIG. 2 is a circuit diagram illustrating a detailed configuration of a first stage and a second stage amplifier circuit in FIG. 1. FIG. 3 is a timing chart showing the operation of the circuit of FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a variable amplifier in FIGS. 1 and 2 having an input polarity switching function. It is a block diagram which shows the modification of FIG. FIG. 6 is a circuit diagram illustrating a detailed configuration of the first-stage and second-stage amplifier circuits in FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st stage amplifier circuit 2 2nd stage amplifier circuit 3 Variable amplifier 4a, 4b CDS circuit 5a, 5b Offset removal circuit 6a, 6b Inverter type amplifier 7 1st stage reference voltage source 8 2nd stage reference voltage source 9 Bias circuit 10 Source follower buffer 11 Image sensor 12 AD converter 13 External capacitor 14 Clamp circuit

Claims (5)

A first amplifying circuit for amplifying a difference voltage between a black level of a feedthrough period of an output signal of the image sensor and a signal level of a charge signal output period at a predetermined amplification rate and outputting a predetermined first reference voltage as a reference; A first voltage level corresponding to a black level of a feedthrough period of an output signal of the image sensor in a signal output of the first amplifier circuit, and a second voltage level corresponding to a signal level of the charge signal output period; A correlated double sampling amplifying circuit having a second amplifying circuit that amplifies the difference signal at a predetermined amplification factor and outputs the difference signal based on a predetermined second reference voltage;
A variable amplifier for amplifying a difference signal between the signal output of the correlated double sampling amplifier circuit and the predetermined second reference voltage with a variable amplification factor;
An AD converter for converting the analog signal output of the variable amplifier into a digital signal;
An analog front end comprising: a clamp circuit that clamps to a voltage correlated with a reference voltage of the AD converter so that an output value of the AD converter corresponding to the black level matches a desired value circuit.   At least the second amplifier circuit of the first and second amplifier circuits includes a black level and a charge signal of a feedthrough period of an output signal of the image sensor in a state where the image sensor is optically cut off. 2. The analog front-end circuit according to claim 1, further comprising offset removing means for removing an offset voltage corresponding to a voltage difference from the signal level in the output period.   3. The analog front end circuit according to claim 1, wherein the first amplifier circuit and the second amplifier circuit have the same circuit configuration.   3. The analog front end circuit according to claim 1, wherein an amplification factor of the second amplifier circuit is set smaller than an amplification factor of the first amplifier circuit.   5. The analog front end circuit according to claim 1, wherein the variable amplifier includes a differential amplifier and includes a function of switching between positive and negative of a differential input. 6.

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