JP2006156568A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor device excellent in drain current characteristics in a semiconductor device having the field effect transistor of an LD structure. <P>SOLUTION: The semiconductor device includes a field effect transistor formed on the principal surface of a semiconductor substrate and an insulating film for generating stress in a channel formation region of the field effect transistor by film stress. In the semiconductor device, a drain region of the field effect transistor includes a first semiconductor region separated away from a gate electrode of the field effect transistor and provided on the principal surface of the semiconductor substrate; and a second semiconductor region provided, in contact with the first semiconductor region, on the principal surface of the semiconductor substrate between the gate electrode and the first semiconductor region, and formed with lower impurity concentration than the first semiconductor region. The insulating film involves the gate electrode therein and covers a part of the second semiconductor region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a field effect transistor having an LD (Laterally Diffused) structure.

  With the rapid spread of mobile communication device terminals in recent years, there has been an increasing demand for power amplifiers for portable terminals with lower power consumption and higher efficiency. As a power amplification element for this application, there are a bipolar transistor using a silicon (Si) substrate, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a transistor using a compound semiconductor substrate typified by GaAs. In particular, an LD structure MOSFET using a silicon substrate is advantageous for high output because it is easy to increase the breakdown voltage, and is highly reliable because it is thermally stable, and has a circuit configuration because it is voltage driven. There is an advantage such as simplicity, and it is the mainstream of the amplifying element. The LD structure MOSFET is disclosed in, for example, Japanese Patent Laid-Open No. 2002-94054 (Publication 1). One of the features of the LD structure is that an offset structure for increasing the breakdown voltage is provided between the gate electrode and the drain electrode.

  On the other hand, as a means for increasing the operation speed of a MOSFET in recent years, a method of inducing strain in silicon in the channel portion of the MOSFET has been proposed. It has been known that the mobility (effective mass) of electrons changes when the silicon crystal is distorted. In Japanese Patent Application Laid-Open No. 11-340337 (publicly known document 2), silicon is used as a base film for forming a MOSFET. A method has been disclosed in which silicon germanium having a larger lattice constant is used and a silicon layer is epitaxially grown thereon, thereby straining the silicon serving as a channel portion to increase mobility and increase the speed of the transistor. Yes.

  In addition, there is also shown a method of increasing the drain current of the MOSFET by straining the channel portion by controlling the stress of the silicon nitride (SiN) film for self-aligned contact formed on the upper surface of the MOSFET. For example, F. Ootsuka, et al., IEDM Tech Digest, (2000) pp575-578 (Publication 3).

  Here, in an insulated gate field effect transistor, a gate insulating film made of a silicon oxide film is generally called a MOSFET. A gate insulating film made of an insulating film such as a silicon oxide film or an oxynitride film is called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). A channel portion (channel formation region) refers to a region where a current path (channel) that connects a source region and a drain region is formed. Further, a current flowing in the plane direction (surface direction) of the semiconductor substrate is called a horizontal type (lateral type), and a current flowing in the thickness (depth) direction of the semiconductor substrate is called a vertical type (vertical type). In addition, an electron channel (conductive path) formed in a channel formation region between the source region and the drain region (under the gate electrode) is an n channel conductivity type (or simply n type), and a hole channel is What is formed is called p-type (or p-channel conductivity type). The one that drain current flows for the first time by applying a voltage higher than the threshold voltage to the gate electrode is called enhancement type (or E type or normally-on type), and drain current can flow without applying voltage to the gate electrode. Is called depletion type (or D type or normally-on type).

JP 2002-94054 A Japanese Patent Laid-Open No. 11-340337 F.Ootsuka, et al., IEDM Tech Digest, (2000) pp575-578

  As described above, in recent semiconductor devices, the drain current has been increased to increase the device speed. Also in the LD structure MOSFET, an increase in drain current is one of the development issues in order to increase the device speed.

  However, the present inventors have clarified that when the above-described film stress control technique for the self-aligned contact SiN film is applied to the LD structure MOSFET, the expected increase in drain current may not be obtained.

  FIG. 2 shows a cross-sectional structure in the case where a stress control film (self-aligned contact film) 13b made of silicon nitride (SiN) having a tensile stress is applied to an n-channel conductivity type MOSFET having an LD structure as a conventional technique. In the case of an n-channel conductivity type MOSFET, if the film stress of the stress control film (self-aligned contact film) is a tensile stress, the drain current can be increased (for example, the above-mentioned known document 3). In the LD structure of FIG. 2 as well, the stress (strain) in the direction parallel to the direction in which the channel current flows (direction along the gate length direction) becomes tensile stress (strain), and the drain current can be increased. . However, the stress generated in the drain offset region (stress in the direction parallel to the direction of current flow), which is a structure peculiar to LD-MOS, is compressed by the influence of the stress control film (self-aligned contact film) of tensile stress. It changes to the stress (strain) side.

  It is known that this diffusion layer resistance also has stress dependence. For example, it is described in Richard C. Jaeger, et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 1, JANUARY 2000. This is known as the piezoresistive effect. In the case of an n-type silicon semiconductor, when a tensile stress (strain) is applied to the resistor in parallel to the direction in which the current flows, the resistance decreases. Conversely, when compressive stress (strain) is applied, the resistance increases.

  For this reason, when the stress control film (self-aligned contact film) 13b for tensile stress is formed on the n-channel conductivity type MOSFET having the LD structure, the stress of the drain offset structure portion becomes a compressive stress. The inventors of the present invention have revealed that there is a problem that the expected current cannot be obtained as a whole of the LD structure MOSFET.

  Such a problem occurs even when a stress control film (self-aligned contact film) made of compressive stress silicon nitride (SiN) is applied to a p-channel conductivity type MOSFET having an LD structure.

  In the case of a p-channel conductivity type MOSFET, if the film stress of the stress control film is a compressive stress, the drain current can be increased. Even in the p-channel conductivity type MOSFET having the LD structure, the stress (strain) in the direction parallel to the direction in which the channel current flows (direction along the gate length direction) becomes compressive stress (strain), which may increase the drain current. It becomes possible. However, the stress generated in the drain offset region (stress in the direction parallel to the direction of current flow), which is a structure peculiar to LD-MOS, is reversed due to the influence of the stress control film (self-aligned contact film) of compressive stress. It changes to the stress (strain) side. In the case of a p-type silicon semiconductor, when a compressive stress (strain) is applied to the resistor in parallel with the direction in which the current flows, the resistance decreases. Conversely, when tensile stress (strain) is applied, the resistance increases.

  Therefore, when the stress control film of compressive stress is formed on the p-channel conductivity type MOSFET having the LD structure, the stress of the drain offset structure portion becomes a tensile stress. As a result, the resistance of the offset structure increases, and the entire MOSFET having the LD structure increases. There is a problem that the expected current cannot be obtained.

An object of the present invention is to provide a semiconductor device having excellent drain current characteristics in a semiconductor device having a field effect transistor having an LD structure.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

(1) A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor includes a first semiconductor region (contact region) provided on a main surface of the semiconductor substrate and spaced from the gate electrode of the field effect transistor, the gate electrode, and the first semiconductor A second semiconductor region (drain offset region) provided in contact with the first semiconductor region on the main surface of the semiconductor substrate between the region and a lower impurity concentration than the first semiconductor region; Have
The insulating film is formed so as to include the gate electrode and cover a part of the second semiconductor region.

When the field effect transistor is an n-channel conductivity type, the film stress of the insulating film is a tensile stress,
When the field effect transistor is a p-channel conductivity type, the film stress of the insulating film is a compressive stress.

  According to the means (1), when the field effect transistor is an n-channel conductivity type, compressive stress generated in the drain offset region due to the film stress of the insulating film can be suppressed. In the case of the channel conductivity type, since the tensile stress generated in the drain offset region due to the film stress of the insulating film can be suppressed, the increase in resistance of the offset structure can be suppressed. As a result, the drain current (Ids) of the field effect transistor can be increased, so that a semiconductor device having excellent drain current characteristics can be obtained.

  Preferably, the insulating film covers the gate electrode side of the second semiconductor region (drain offset region) and is not provided on the first semiconductor region side of the second semiconductor region.

  The insulating film is preferably not installed (meaning that it does not exist completely) on the second semiconductor region. In this case, since the stress due to the insulating film (compressive stress in the case of n-type field effect transistor and tensile stress in the case of p-type field effect transistor) does not occur in the drain offset region, the resistance of the offset structure is increased. Therefore, the drain current of the field effect transistor can be increased.

(2) A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor includes a first semiconductor region (contact region) provided on a main surface of the semiconductor substrate and spaced from the gate electrode of the field effect transistor, the gate electrode, and the first semiconductor A second semiconductor region (drain offset region) provided in contact with the first semiconductor region on the main surface of the semiconductor substrate between the region and a lower impurity concentration than the first semiconductor region; Have
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
Further, in the insulating film, the film stress in the portion on the second semiconductor region is lower than the film stress in the portion on the gate electrode.

When the field effect transistor is an n-channel conductivity type, the film stress of the portion of the insulating film on the second semiconductor region is closer to the compressive stress than the film stress of the portion of the insulating film on the gate electrode. ,
When the field effect transistor is of a p-channel conductivity type, the film stress in the portion of the insulating film on the second semiconductor region is on the tensile stress side relative to the film stress of the portion of the insulating film on the gate electrode. .

(3) A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
Further, the insulating film includes a first portion located on the gate electrode and a second portion located on the second semiconductor region and having a higher element concentration in the film than the first portion. Have.

  The second portion of the insulating film includes at least one of silicon (Si), nitrogen (N), oxygen (O), argon (Ar), helium (He), and germanium (Ge). It contains more than the 1st part of.

(4) A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor due to film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is selectively formed on the gate electrode side on the second semiconductor region except on the gate electrode.

When the field effect transistor is n-channel conductivity type, the film stress of the insulating film is a tensile stress,
When the field effect transistor is a p-channel conductivity type, the film stress of the insulating film is a compressive stress.

(5) A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
The insulating film further includes a first portion located on the gate electrode and a second portion located on the second semiconductor region and having a thickness smaller than that of the first portion.

When the field effect transistor is n-channel conductivity type, the film stress of the insulating film is a tensile stress,
When the field effect transistor is a p-channel conductivity type, the film stress of the insulating film is a compressive stress.
In the means (2) to (5), the same effect as the means (1) can be obtained.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, a semiconductor device having excellent drain current characteristics can be realized in a semiconductor device having a field effect transistor having a drain offset structure.

  Hereinafter, embodiments (examples) of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(First embodiment)
In the first embodiment, an example in which the present invention is applied to a semiconductor device having a MISFET having an LD structure as a field effect transistor will be described.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention (cross-sectional view taken along line AB in FIG. 2).
FIG. 2 is a schematic cross-sectional view of a conventional semiconductor device,
FIG. 3 is a schematic plan view of a semiconductor device according to the first embodiment of the present invention,
4 to 9 are schematic cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view of a semiconductor device which is a modification of the first embodiment of the present invention.
FIG. 24 is a schematic plan layout diagram of the semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device according to the first embodiment is mainly composed of a semiconductor substrate 1. The semiconductor substrate 1 is formed by, for example, a low-resistance p-type support substrate 1a made of p-type silicon having a specific resistance of about 10 [Ωcm] and an epitaxial growth method on the support substrate 1a, and has a specific resistance of 30 [Ωcm]. And a high resistance p-type epitaxial layer 1b made of p-type silicon.

  As shown in FIG. 1, a p-type well region 4 and an n-channel conductivity type MISFET (hereinafter simply referred to as an n-type MISFET) -Q are formed on the main surface of the semiconductor substrate 1 (main surface of the epitaxial layer 1b). Has been. The semiconductor device of Example 1 has a multi-cell structure in which a plurality of transistor cells made of n-type MISFET-Q shown in FIG. The cross-sectional schematic diagram shown in FIG. 1 is an AB cross section (A-B cross section shown in FIG. 24) of the plan schematic diagram shown in FIG. 3, and the semiconductor device of the first embodiment has a period of the AB cross section. Structure. FIG. 24 is a schematic plan view showing the position where the stress control film 13a is formed, and the number of MISFETs formed in the active region 20 is not limited to the illustrated number.

  The n-type MISFET-Q has an LD (Laterally Diffused) structure, and mainly has a channel formation region, a gate insulating film 5, a gate electrode 6, a source region, and a drain region as shown in FIG. Yes. The gate insulating film 5 is provided on the main surface of the semiconductor substrate 1. The gate electrode 6 is provided on the main surface of the semiconductor substrate 1 with a gate insulating film 5 interposed therebetween. The channel formation region is provided on the main surface of the semiconductor substrate 1 immediately below the gate electrode 6, and the p-type well region 4 is provided in this channel formation region. The source region and the drain region are formed on the main surface of the semiconductor substrate 1 so as to sandwich the channel formation region in the channel length (gate length) direction of the channel formation region.

Examples of the gate insulating film 5 include a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), and tantalum pentoxide (Ta _2). It consists of a dielectric film such as O ₅ ) or a laminated structure thereof. The gate electrode 6 is made of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced, a metal film such as tungsten (W), platinum (Pt), ruthenium (Ru), or a laminated structure thereof.

Side walls 7 and 9 made of silicon nitride (SiN) or silicon oxide film (SiO ₂ ) are formed on the side walls of the gate electrode 6, and a field plate made of, for example, polycrystalline silicon is formed on the drain region side. 10 is formed.

  The source region of the n-type MISFET-Q includes an n-type semiconductor region 8a and an n-type semiconductor region 11a having a higher impurity concentration than the n-type semiconductor region 8a. The n-type semiconductor region 8a is provided in alignment with the gate electrode 6 on the main surface of the semiconductor substrate 1, specifically in the p-type well region. The n-type semiconductor region 11 a is provided in the main surface of the semiconductor substrate 1, specifically, in the p-type well region 4 in alignment with the sidewall 9 provided on the side wall of the gate electrode 6.

  The drain region of the n-type MISFET-Q has an n-type semiconductor region 8b that is a drain offset region and an n-type semiconductor region 11b that is a contact region. The n-type semiconductor region 11b is spaced from the gate electrode 6 and provided on the main surface of the semiconductor substrate 1, specifically on the main surface of the p-type epitaxial layer 1b. The n-type semiconductor region 8b is provided on the main surface of the semiconductor substrate 1 between the gate electrode 6 and the n-type semiconductor region 11b, specifically, on the main surface of the p-type well region 1b. The n-type semiconductor region 8 b is provided in alignment with the gate electrode 6, and is further provided in contact with the n-type semiconductor region 11 b and the p-type well region 4.

  The n-type semiconductor region 11b that is a contact region has a higher impurity concentration (low resistance) than the n-type semiconductor region 8b for the purpose of reducing contact resistance with the wiring, and the n-type semiconductor region 8b that is a drain offset region. Has a lower impurity concentration (high resistance) than the n-type semiconductor region 11b for the purpose of increasing the breakdown voltage of the drain region.

  On the upper surfaces of the n-type semiconductor region 11a, the gate electrode 6 and the field plate 10, for example, a silicide film 12 such as cobalt silicide or nickel silicide is formed.

  An interlayer insulating film 14 is provided on the main surface of the semiconductor substrate 1 so as to cover the n-type MISFET-Q, and an interlayer insulating film 16 is further provided on the interlayer insulating film 14. As the interlayer insulating films 14 and 16, for example, a BPSG (Boron-doped Phospho Silicate Glass) film, an SOG (Spin On Glass) film, a TEOS (Tetra-Ethyl-Ortho-Silicate) film, or the like is used. It is formed by a phase growth (CVD: Chemical Vapor Deposition) method or a sputtering method.

  The semiconductor substrate 1 is provided with a p-type reach-through layer 3 made of, for example, polycrystalline silicon and reaching the p-type support substrate 1a from the main surface of the p-type epitaxial layer 1b.

  A first contact hole that reaches the silicide film 12 on the n-type semiconductor region 11a from the surface of the interlayer insulating film 14 is provided on the n-type semiconductor region 11a that is the source region. A contact plug 15 is embedded in the inside. The n-type semiconductor region 11 a is electrically connected to a wiring 17 a extending on the interlayer insulating film 14 via the contact plug 15 in the first contact hole and the silicide film 12.

  A second contact hole that reaches the n-type semiconductor region 11b from the surface of the interlayer insulating film 14 is provided on the n-type semiconductor region 11b that is a drain region, and a contact is formed in the second contact hole. A plug 15 is embedded. The n-type semiconductor region 11b is electrically connected to the wiring 17b extending on the interlayer insulating film 14 via the contact plug 15 in the second contact hole.

  A third contact hole that reaches the silicide film 12 on the p-type reach-through layer 3 from the surface of the interlayer insulating film 14 is provided on the p-type reach-through layer 3. Is embedded with a contact plug 15. The p-type reach-through layer 3 is electrically connected to the wiring 17a extending on the interlayer insulating film 14 via the contact plug 15 in the third contact hole and the silicide film 12.

  On the main surface of the semiconductor substrate 1, specifically, between the n-type MISFET-Q and the interlayer insulating film 14, a stress control film 13a for generating stress in the channel formation region of the n-type MISFET-Q is provided. It has been. The stress control film 13a of the first embodiment is a silicon nitride film having a film stress that generates a tensile stress along the gate length direction (drain current direction) in the channel formation region under the gate electrode 6 of the n-type MISFET-Q. Is formed.

  The stress control film 13a having a film stress of tensile stress is formed so as to include the gate electrode 6, cover the source region, and further cover a part of the n-type semiconductor region 8b that is the drain offset region. In the first embodiment, the stress control film 13a for tensile stress covers a portion on the gate electrode side of the n-type semiconductor region 8b on the drain region and is not installed from this portion to the n-type semiconductor region 11b side. It is formed to become. That is, the stress control film 13a terminates at the gate electrode side portion of the drain offset region.

  As shown in FIG. 24, the stress control film 13a is formed in the active region 20 so as not to be placed on the drain region. The stress control film 13a is formed in a region outside the active region 20 (an element mainly made of silicon oxide). On the separation area), it does not necessarily have to be non-installed.

The manufacturing process of the semiconductor device of the first embodiment is as follows, for example.
(1) An n-type MISFET-Q having an LD structure is formed on the main surface of the semiconductor substrate 1 (FIG. 4).
(2) A silicon nitride (SiN) film that becomes the stress control film 13a is formed on the entire main surface of the semiconductor substrate 1 so as to cover the n-type MISFET-Q, for example, by sputtering or chemical vapor deposition. (FIG. 5).
(3) A mask 50 is formed at least in a portion excluding the contact plug formation portion and the drain offset region (n-type semiconductor region 8b) (FIG. 6).
(4) The stress control film 13a on the drain offset region (n-type semiconductor region 8b) and the contact plug formation portion is removed by, for example, anisotropic etching (FIG. 7).
(5) The mask 50 is removed, and the interlayer insulating film 14 is formed (FIG. 8).
(6) A contact hole is formed in a portion where the contact plug 15 is formed (FIG. 9).
(7) Contact plugs 15, wirings 17 and the like are formed (FIG. 10).
Thereby, the semiconductor device having the structure shown in FIG. 1 is formed.

In the first embodiment, the stress control film 13a is used as means for improving the characteristics of the n-type MISFET having the LD structure by stress control. Other parts may be structures and materials other than the first embodiment of the present invention. For example, the field plate 10 may be omitted.
The operation and effect of the semiconductor device according to the first embodiment of the present invention will be described below.

  In recent semiconductor devices, in order to increase the device speed, a device speed-up technology using strain of Si crystal that does not depend on a fine processing technology has been developed. These techniques are disclosed in, for example, the aforementioned publicly known document 3. On the other hand, even in an LD structure MOSFET used as a power amplifying element for a mobile communication device terminal, a technology for increasing the device speed without relying only on miniaturization is required.

  FIG. 2 shows an n-type MOSFET having an LD structure to which a conventional device speed-up technique using self-aligned contact film stress is applied. In order to increase the drain current of the n-type MOSFET as disclosed in the aforementioned known document 3, a tensile stress SiN film is used as the self-aligned contact film. 2 is an example in which a stress control film (self-aligned contact film) 13b for tensile stress is formed on the entire upper surface of the LD-MOS structure, the source region, and the drain offset region.

  The tensile stress control film (self-aligned contact film) 13b generates tensile stress (strain) in the direction parallel to the drain current and compressive stress (strain) in the direction perpendicular to the Si substrate surface in the MOSFET channel. . In particular, the compressive stress in the vertical direction of the substrate surface is large, which is caused by the tensile stress of the stress control film on the side surface portion of the gate electrode. The drain current of the n-type MOSFET increases due to the tensile stress (strain) in the direction parallel to the drain current of the channel portion and the compressive stress (strain) in the direction perpendicular to the Si substrate surface. The relationship between the direction of stress and the drain current is disclosed in, for example, “Kumaya et al., Proceedings of the Japan Society of Mechanical Engineers Material Mechanics Division, (2003) pp577-578”.

  However, as shown in FIG. 2, the inventors of the present application may not be able to obtain an expected increase in drain current when applying a conventional self-aligned contact film stress control technique to an n-type MOSFET having an LD structure. It revealed that.

  That is, in the LD structure MOSFET in which the stress control film (self-aligned contact film) 13b of tensile stress is formed, the stress (strain) of the channel portion is tensile stress in the drain current parallel direction and in the normal direction of the Si substrate surface. Compressive stress is generated and the drain current can be increased. However, the stress in the offset structure portion, which is a structure peculiar to the LD-MOS, changes to the compressive stress (strain) side as a reaction due to the formation of the stress control film 13b of tensile stress on the upper surface.

  The diffusion layer resistance also has a stress dependency known as a piezoresistance effect. When compressive stress is applied to n-type silicon in the direction parallel to the current, the resistance increases. For this reason, in the structure of FIG. 2, the resistance of the offset structure increases, and although the drain current can be increased by controlling the stress in the channel portion, the expected drain current for the LD-MOS structure as a whole. The inventors of the present application have clarified that there is a possibility that the effect of increase in the number may not be obtained.

  Therefore, in the first embodiment, the stress control film 13a for tensile stress encloses the gate electrode 6, covers the entire source region, and further, the portion on the gate electrode 6 side of the n-type semiconductor region 8b which is the drain contact region. The cover is formed so as not to be installed from this portion to the n-type semiconductor region 11b. By adopting such a configuration, the compressive stress generated in the n-type semiconductor region (drain offset region) 8b by the stress control film 13a having a tensile stress can be suppressed, so that the offset structure (drain offset region). The increase in resistance can be suppressed. As a result, since the drain current (Ids) of the n-type MISFET having the LD structure can be increased, a semiconductor device having excellent drain current characteristics can be obtained.

  In addition, since the stress control film 13a is mainly made of silicon nitride (SiN), an interlayer made of a silicon oxide film for electrical connection from the upper wiring to the source / drain region after the formation of the interlayer insulating film 14 is formed. An effect is obtained that it can also be used as an etch stop when a contact hole is opened in the insulating film 14.

  In the manufacturing method shown in the first embodiment, the stress control film 13a formed on the drain offset region is etched simultaneously with the formation of the contact hole of the self-aligned contact film. For this reason, it is not necessary to prepare a new mask, and an effect of obtaining a highly reliable semiconductor device with reduced manufacturing cost can be obtained.

  Note that the removal of the stress control film may be performed not only on the drain offset region but also on the source region as shown in FIG. In this case, an increase in the diffusion layer resistance of not only the drain offset region but also the source region can be suppressed, and a compressive stress acts on the channel portion in the normal direction of the substrate surface by the stress control film 13c on the side wall portion of the gate electrode. As a result, the drain current can be increased.

  In the first embodiment, the example in which the gate electrode side of the drain offset region is selectively covered with the stress control film 13a on the drain offset region (on the n-type semiconductor region 8b) has been described. For example, the stress control film may be formed so as not to selectively cover the central portion of the drain offset region. In short, the portion where the drain offset region is not covered with the stress control film is made as wide as possible.

  However, in order to effectively generate stress in the channel formation region under the gate electrode, it is necessary to leave a stress control film on the side wall of the gate electrode. Therefore, the portion on the gate electrode side of the drain contact region is a stress control film. It is desirable to cover.

  In the first embodiment, an example in which the present invention is applied to an n-type MISFET having an LD structure has been described. However, the present invention can also be applied to a p-type MISFET having an LD structure.

  In the case of a p-type MISFET, the drain current can be increased by using a stress control film whose film stress is compressive stress. Even in the p-type MISFET having the LD structure, the stress (strain) in the direction parallel to the direction in which the channel portion current flows (the direction along the gate length direction) becomes compressive stress (strain), and the drain current can be increased. Become. However, the stress generated in the drain offset region (stress in the direction parallel to the direction of current flow), which is a structure peculiar to LD-MOS, is reversed due to the influence of the stress control film (self-aligned contact film) of compressive stress. It changes to the stress (strain) side. In the case of a p-type silicon semiconductor, when a compressive stress (strain) is applied to the resistor in parallel with the direction in which the current flows, the resistance decreases. Conversely, when tensile stress (strain) is applied, the resistance increases.

  Accordingly, even in the p-type MISFET having the LD structure, the stress control film having the compressive stress is configured in the same manner as in the first embodiment, so that the tensile stress generated in the drain offset region by the stress control film having the compressive stress is generated. Since stress can be suppressed, an increase in resistance of the offset structure can be suppressed. As a result, since the drain current (Ids) of the p-type MISFET having the LD structure can be increased, a semiconductor device having excellent drain current characteristics can be obtained.

(Second embodiment)
FIG. 11 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.
12 to 16 are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.
FIG. 17 is a schematic cross-sectional view of a semiconductor device which is a modification of the second embodiment of the present invention.

  The difference between the second embodiment and the first embodiment is that, instead of removing the stress control film made of silicon nitride (SiN) on the drain offset region, the composition of the SiN film is changed to the portion including the gate electrode and the drain. The difference is that the part on the offset area is different.

  As shown in FIG. 11, the stress control film 13d made of a silicon nitride film has a first portion 13d1 and a second portion 13d2. The film stress of the first part 13d1 is a tensile stress, and the film stress of the second part 13d2 is smaller than that of the first part 13d1. That is, the film stress of the second portion 13d2 is closer to the compressive stress than the film stress of the first portion 13d1.

  The first portion 13d1 of the stress control film 13d includes the gate electrode 6, covers the source region, and further covers a portion of the drain offset region on the gate electrode 6 side. The second portion 13d2 of the stress control film 13d is formed so as to cover the drain offset region except for the portion of the drain offset region on the gate electrode 6 side. In the second embodiment, the contact region (n-type semiconductor region 11b) of the drain region is also covered with the second portion 13d2.

  The composition of the silicon nitride film differs between the first portion 13d1 and the second portion 13d2 of the stress control film 13d. In such a stress control film 13d, after a silicon nitride film having a tensile stress is formed, a predetermined portion (formation region of the second portion) of the silicon nitride film is silicon (Si), nitrogen (N). , Oxygen (O), germanium (Ge), argon (Ar), and helium (He) can be formed by ion implantation so as to contain at least one of them in excess.

  The second embodiment is an example in which the composition of the SiN film is changed as means for increasing the drain current by the stress control film in the n-type MISFET having the LD structure, and other parts are made of other structures and materials. It doesn't matter.

The manufacturing process of the semiconductor device of the second embodiment is as follows, for example.
(1) An MISFET-Q having an LD structure is formed on the main surface of the semiconductor substrate 1 (FIG. 12).
(2) A stress control film 13d made of a silicon nitride (SiN) film having a tensile stress is formed on the entire main surface of the semiconductor substrate 1 so as to cover the n-type MISFET-Q having the LD structure, for example, by sputtering or A film is formed by chemical vapor deposition or the like (FIG. 13).
(3) A mask 51 covering the source region and the gate electrode of the n-type MISFET-Q and having an opening on the drain offset region of the drain region is formed (FIG. 14), and then the stress in the opening of the mask 51 An inert element such as silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), or argon (Ar) is ion-implanted into the control film 13d (FIG. 15). In this step, the first portion 13d1 having a membrane stress of tensile stress and the second portion of the membrane stress having a smaller tensile stress than the first portion 13d1 (compressive stress side of the membrane stress of the first portion 13d1) A stress control film 13 having 13d2 is formed.
(4) After removing the mask 51 (FIG. 16), the interlayer insulating film 14 and the like are formed. Thereby, the semiconductor device having the structure shown in FIG. 11 is manufactured.
Next, functions and effects of the semiconductor device according to the second embodiment of the present invention will be described.

  In the second embodiment, after the stress control film 13 made of a silicon nitride film having a film stress of tensile stress is formed, impurities are ion-implanted into the stress control film 13 on the drain offset region, so that the first portion 13d1 In addition, the second portion 13d2 having a small film stress (a compressive stress side with respect to the film stress of the first portion 13d1) is formed. As a result, the atomic density of the film of the second portion 13d2 becomes dense compared to that before ion implantation, and the bonds of atoms in the silicon nitride film are cut by the implanted ions, so that the second portion 13d2 Tensile stress relaxes.

  Accordingly, the stress in the drain offset region temporarily becomes a compressive stress by the stress control film 13d of the tensile stress, but the stress is relaxed in the second portion 13d2 of the stress control film 13d by the ion implantation, so that the stress is generated in the drain offset region. Compressive stress is also relieved. For this reason, the drain current can be increased without causing an increase in the diffusion resistance of the drain offset region due to stress.

  Also in the second embodiment, as in the first embodiment, the stress control film 13d can be used as a self-aligned contact film.

  Note that an inert element such as silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), or argon (Ar) is ion-implanted into the stress control film 13d only on the drain region. Instead, it may be on the source region as shown in FIG. In this case, it is possible to prevent an increase in the diffusion layer resistance of the source region as well as the drain offset region.

  In the second embodiment, an example in which the present invention is applied to an n-type MISFET having an LD structure has been described. However, the present invention can also be applied to a p-type MISFET having an LD structure. In the case of a p-type MISFET having an LD structure, a silicon nitride film having a compressive stress is formed so as to cover the p-type MISFET having an LD structure, and then a portion of the silicon nitride film where the compressive stress is to be relaxed (at least A stress control film is formed by ion-implanting an inert element such as silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), or argon (Ar) into the drain offset region. Form. The stress control film thus formed has a first portion where the membrane stress is a compressive stress and a membrane stress whose compressive stress is smaller than that of the first portion, that is, a membrane stress whose tensile stress is higher than that of the first portion. Side second portion.

(Third embodiment)
FIG. 18 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention.
FIG. 19 to FIG. 21 are schematic cross-sectional views showing the manufacturing steps of the semiconductor device according to the third embodiment of the present invention.

  The difference between the third embodiment and the first embodiment described above is that the stress control film 13f made of a silicon nitride (SiN) film having a tensile stress is formed on the two side surfaces of the gate electrode 6 in the gate length direction. It is selectively formed and formed so as not to be installed on the other part of the source and drain regions except the part on the gate electrode side and on the gate electrode 6.

The manufacturing process of the semiconductor device of the third embodiment is as follows, for example.
(1) An n-type MISFET-Q having an LD structure is formed on the main surface of the semiconductor substrate 1 (FIG. 19).
(2) A stress control film 13f made of a silicon nitride (SiN) film having a tensile stress is formed on the entire main surface of the semiconductor substrate 1 so as to cover the n-type MISFET-Q, for example, by sputtering or chemical vapor deposition. A film is formed by a growth method or the like (FIG. 20).
(3) The stress control film 13f on the source and drain regions and on the gate electrode 6 is removed by anisotropic etching (FIG. 21).
(4) The interlayer insulating film 14 and the like are formed. Thereby, the semiconductor device having the structure shown in FIG. 18 is manufactured.

The third embodiment of the present invention is an example in which the stress control film 13f is used as the drain current increasing means in the n-type MISFET-Q having the LD structure. Other parts may be structures and materials other than the third embodiment of the present invention.
Next, functions and effects of the semiconductor device according to the third embodiment of the present invention will be described.

  According to the third embodiment of the present invention, the stress control film 13f for tensile stress is formed on the entire main surface of the semiconductor substrate 1 so as to cover the n-type MISFET-Q having the LD structure. The stress control film on the drain region is removed, leaving only the side surface portion of the gate electrode. Since the tensile stress of the stress control film on the side wall of the gate electrode gives a compressive stress in the normal direction of the Si substrate surface in the channel formation region, the drain current can be increased, and the stress of the tensile stress on the source / drain region Since the control film is not formed, the effect that the diffusion layer resistance does not increase is obtained.

  In addition, according to the third embodiment, the stress control film 13f is processed by general anisotropic etching, which is used for etching the sidewall structure, and thus can be manufactured without using a new mask. Therefore, the effect that a semiconductor device excellent in manufacturing cost can be obtained can be obtained.

  In the third embodiment, an example in which the present invention is applied to an n-type MISFET-Q having an LD structure has been described. However, the present invention can also be applied to a p-type MISFET having an LD structure. In the case of a p-type MISFET having an LD structure, a stress control film made of a silicon nitride film having a compressive stress is formed on the entire main surface of the semiconductor substrate 1 so as to cover the p-type MISFET having an LD structure. The stress control film 13f on the source region, the drain region, and the gate electrode 6 is removed so that the portion of the drain region on the gate electrode side remains selectively.

(Fourth embodiment)
FIG. 22 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 23 is a schematic cross-sectional view of a semiconductor device which is a modification of the fourth embodiment of the present invention.

  The difference between the fourth embodiment and the first embodiment described above is that the stress control film 13g made of a silicon nitride (SiN) film having a film stress of tensile stress is not installed on the drain offset region, but on the gate electrode. The film thickness is thinner than that.

  The manufacturing method of the semiconductor device according to the fourth embodiment is, for example, the time when the thickness is reduced without removing all of the stress control film on the drain offset region in the manufacturing method described in the first embodiment. Then, the etching may be finished.

The fourth embodiment of the present invention is an example in which the stress control film 13g is used as the drain current increasing means in the LD structure MISFET. Other parts may be structures and materials other than the third embodiment of the present invention.
Next, functions and effects of the semiconductor device according to the fourth embodiment of the present invention will be described.

  According to the fourth embodiment of the present invention, after the stress control film 13g for tensile stress is formed on the entire upper surface, the stress control film 13g on the drain offset region is thinned. For this reason, the compressive stress due to the stress control film 13g generated in the drain offset region is reduced, and an effect of preventing an increase in diffusion layer resistance due to the stress can be obtained.

  In addition, according to the fourth embodiment, unlike the first embodiment, the stress control film 13g is also left on the drain offset region, so that it can be used as an etch stopper when forming a contact hole. The effect is obtained.

  In the fourth embodiment, the stress control film 13g is made thinner than the thickness on the gate electrode not only on the drain region but also on the source region as shown in FIG. good. In this case, it is possible to prevent an increase in the diffusion layer resistance of the source region as well as the drain offset region.

  In the fourth embodiment, the example in which the present invention is applied to the n-type MISFET-Q has been described. However, the present invention can also be applied to a p-type MISFET. In the case of a p-type MISFET, a stress control film 13 made of a silicon nitride film having a compressive stress is formed on the entire main surface of the semiconductor substrate 1 so as to cover the p-type MISFET, and then stress control on the drain offset region is performed. The film 13g is thinned. By doing so, since the tensile stress generated in the drain offset region can be reduced by the stress control film of compressive stress, an increase in the diffusion layer resistance of the drain offset region due to the stress can be suppressed. can get.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a cross-sectional schematic diagram of a conventional semiconductor device. 1 is a schematic diagram showing a planar layout of a semiconductor device according to a first embodiment of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram which shows another form (modification) of the semiconductor device which is 1st Example of this invention. It is a cross-sectional schematic diagram of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram which shows another form (modification) of the semiconductor device which is 2nd Example of this invention. It is a cross-sectional schematic diagram of the semiconductor device which is 3rd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 3rd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 3rd Example of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device which is 3rd Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 4th Example of this invention. It is a cross-sectional schematic diagram which shows another form (modification) of the semiconductor device which is 4th Example of this invention. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 1a ... p-type support substrate 1b ... p-type epitaxial layer 3 ... p-type reach through layer 4 ... p-type well region 5 ... Gate insulating film 6 ... Gate electrode 7, 9 ... Side wall 8a ... N-type semiconductor region 8b ... n-type semiconductor region (drain offset region)
DESCRIPTION OF SYMBOLS 10 ... Field plate 11a ... N-type semiconductor region 11b ... N-type semiconductor region (drain contact region)
DESCRIPTION OF SYMBOLS 12 ... Silicide film 13a, 13b, 13c, 13d, 13f, 13g ... Stress control film 14, 16 ... Interlayer insulating film 15 ... Contact plug 17a, 17b ... Wiring 20 ... Active region 50, 51 ... Mask

Claims (15)

A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The semiconductor device is characterized in that the insulating film includes the gate electrode and covers a part of the second semiconductor region. The semiconductor device according to claim 1,
The field effect transistor is of an n-channel conductivity type;
The semiconductor device according to claim 1, wherein the film stress of the insulating film is a tensile stress. The semiconductor device according to claim 1,
The field effect transistor is p-channel conductivity type,
2. The semiconductor device according to claim 1, wherein the film stress of the insulating film is a compressive stress. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor region is a contact region, and the second semiconductor region is an offset region. A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
Further, in the semiconductor device, the film stress of the portion on the second semiconductor region is lower than the film stress of the portion on the gate electrode. The semiconductor device according to claim 5,
The field effect transistor is of an n-channel conductivity type;
2. The semiconductor device according to claim 1, wherein a film stress of a portion of the insulating film on the second semiconductor region is on a compressive stress side of a film stress of a portion of the insulating film on the gate electrode. The semiconductor device according to claim 5,
The field effect transistor is p-type,
2. The semiconductor device according to claim 1, wherein a film stress of a part of the insulating film on the second semiconductor region is on a tensile stress side with respect to a film stress of a part of the insulating film on the gate electrode. A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
Further, the insulating film includes a first portion located on the gate electrode and a second portion located on the second semiconductor region and having a higher element concentration in the film than the first portion. A semiconductor device comprising: A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The semiconductor device is characterized in that the insulating film is selectively formed on a side wall of the gate electrode except on the gate electrode. The semiconductor device according to claim 9.
The field effect transistor is of an n-channel conductivity type;
The semiconductor device according to claim 1, wherein the film stress of the insulating film is a tensile stress. The semiconductor device according to claim 9.
The field effect transistor is p-channel conductivity type,
2. The semiconductor device according to claim 1, wherein the film stress of the insulating film is a compressive stress. A semiconductor device having a field effect transistor formed on a main surface of a semiconductor substrate and an insulating film that generates stress in a channel formation region of the field effect transistor by film stress,
The drain region of the field effect transistor is spaced apart from the gate electrode of the field effect transistor, and is provided between the first semiconductor region provided on the main surface of the semiconductor substrate and between the gate electrode and the first semiconductor region. A second semiconductor region provided on the main surface of the semiconductor substrate in contact with the first semiconductor region and having a lower impurity concentration than the first semiconductor region;
The insulating film is formed so as to cover the gate electrode and the second semiconductor region,
Further, the insulating film has a first portion located on the gate electrode and a second portion located on the second semiconductor region and having a thickness smaller than that of the first portion. A featured semiconductor device. The semiconductor device according to claim 12,
The field effect transistor is of an n-channel conductivity type;
The semiconductor device according to claim 1, wherein the film stress of the insulating film is a tensile stress. The semiconductor device according to claim 12,
The field effect transistor is p-channel conductivity type,
2. The semiconductor device according to claim 1, wherein the film stress of the insulating film is a compressive stress. The semiconductor device according to any one of claims 1, 5, 8, 9, and 12,
The semiconductor device according to claim 1, wherein the insulating film is a self-aligned contact insulating film made of a silicon nitride film.

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