JP2006155679A - Data inversion control circuit, storage device provided with the data inversion control circuit and data inversion control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data inversion control circuit for inputting data while inverting or non-inverting them accompanying the twist of a bit line and a bit auxiliary line to a storage device provided with a LOW side redundant word line and a HIGH side redundant word line and also provided with the bit line and the bit auxiliary line having a twist structure, the storage device provided with the data inversion control circuit, and a data inversion control method, wherein the efficiency of data inversion control is made high. <P>SOLUTION: In the case that an L shift setting address which is the origin of shifting the address of a word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line is larger than an H shift setting address which is the origin of shifting the address of the word line in the direction of the HIGH side redundant word line so as to use the HIGH side redundant word line, the address data of the L shift setting address and the H shift setting address are replaced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data inversion control circuit, a storage device having the data inversion control circuit, and a data inversion control method.

  2. Description of the Related Art Conventionally, a storage device having memory cells arranged in a matrix by bit lines having bit complementary lines and word lines, such as a dynamic random access memory (DRAM), is known.

  In such a memory device, in particular, a DRAM, a regulated capacity due to capacitive coupling occurs between adjacent bit lines and bit complementary lines, and the potential difference between the bit lines and the bit complementary lines constituting the pair. It is also known that when data is read by differential amplification with a sense amplifier circuit, the value of the read data may change due to the difference in the regulation capacity generated in each bit line and each bit complementary line.

  Therefore, a twist structure has been proposed in which the arrangement of bit lines and bit complement lines forming a pair is alternately switched. By adopting this twist structure, the restriction capacities of the bit line and the bit complementary line forming the pair can be made substantially the same, and the possibility that the value of the read data changes is eliminated.

  Further, in such a memory device, there are cases where accurate writing of data in the memory cells and accurate reading of data from the memory cells may not be possible due to manufacturing defects during the manufacturing process. In the event that a defective memory cell cannot be read or written accurately, a spare memory cell to be used in place of the defective memory cell is provided in advance, and a spare memory cell is provided in place of the defective memory cell. It is used (for example, refer patent document 1).

  As a method of providing such a spare memory cell, a redundant word line is provided as a spare word line in parallel with the word line, and a redundant memory cell is provided. In terms of structure, one or a plurality of word lines are provided for one unit of word lines composed of a plurality of word lines such as 4 units, 8 units, or 16 units. Thus, a redundant unit block is formed by a plurality of word lines and one or a plurality of redundant word lines.

  In particular, when two redundant word lines are provided in one redundant unit block, the word line designated by the smallest word line designation address in the word line designation address designating each word line is set as the LOW side redundant word line. The word line designated by the largest word line designated address is used as a HIGH-side redundant word line, and the word line designated by the word line designated address between them is used as a word line for one unit.

  In the following, the word line of the word line designated address near the LOW side redundant word line is referred to as the “LOW side” word line with respect to the word line of the predetermined word line designated address, and the word line near the HIGH side redundant word line. The word line of the designated address is called a “HIGH side” word line.

  If there is a word line connected to the defective memory cell, shift redundancy that shifts only one LOW side word line including the word line to a LOW side address, or HIGH including the word line Shift redundancy is performed in which only one side word line is shifted to a HIGH side address.

  If there is only one defective memory cell, use either the LOW side redundant word line or the HIGH side redundant word line, and if there are two defective memory cells, Both the LOW side redundant word line and the HIGH side redundant word line are used.

  At this time, when the LOW side redundant word line is used by shifting to the LOW side due to the presence of the defective memory cell, the defective memory cell is connected to the defective memory that is the starting point of the shift in the LOW side redundant word line direction. The address of the word line is referred to as “L shift setting address”. When the high-side redundant word line is used by shifting to the high-side due to the presence of a defective memory cell, the high-side redundant word line direction is used. The address of the word line connected to the defective memory which is the starting point of the shift is referred to as “H shift set address”.

  As described above, when one redundant unit block is formed by providing a LOW-side redundant word line and a HIGH-side redundant word line before and after one unit of word lines, shift redundancy for shifting the address of the word line is performed. Since the twist structure of the bit line and the bit complementary line is physically fixed, the corresponding bit line and bit complementary line may be switched with the shift of the address of the word line. .

  Therefore, in the storage device having the twist structure and the redundant unit block as described above, the twist structure according to the presence / absence of shift redundancy when data is input to or output from the memory cell. A data inversion control circuit is provided in order to input / output data while taking this into consideration.

  In this data inversion control circuit, as shown in the flowchart of FIG. 3, the redundant unit block first checks whether the LOW side redundant word line and / or the HIGH side redundant word line are used. Confirmation is made (step T1), and when one or both of the LOW side redundant word line and the HIGH side redundant word line are used, the LOW side redundant word line and / or the HIGH side used. The address of the redundant word line is input (step T2), and the redundant address is set based on the input address of the LOW side redundant word line and / or the HIGH side redundant word line (step T3).

  Next, the data inversion control circuit determines whether or not it is necessary to change the setting for a predetermined twist area in the twist structure based on the set redundant address (step T4).

  If the data inversion control circuit determines that the setting for the twist area needs to be changed, the data inversion control circuit generates twist area change information (step T5), and generates final twist area information based on the twist area change information. (Step T6) The data inversion control circuit generates and outputs a data inversion instruction signal based on the final twist area information (Step T7).

  On the other hand, if the number of redundant uses is “0” in step T1 and if it is not necessary to change the setting for the twist area in step T4, the data inversion control circuit sets the data inversion set in advance. An instruction signal is generated and output (step T8).

Then, based on this data inversion instruction signal, data is input to the memory cell or data is output from the memory cell while performing inversion or non-inversion of the data.
Japanese Patent Laid-Open No. 06-314498

  However, when both the LOW-side redundant word line and the HIGH-side redundant word line are used, for example, the address of the word line relatively close to the LOW-side redundant word line is used as the H-shift setting address, and the shift redundancy to the HIGH side is performed. , The redundancy of the word line relatively close to the HIGH-side redundant word line must be used as the L-shift setting address and shift redundancy to the LOW side must be performed, and vice versa. Shift redundancy to the LOW side is performed using the address of the near word line as the L shift set address, and then shift redundancy to the HIGH side is performed using the address of the word line relatively close to the LOW side redundant word line as the H shift set address. When the L shift setting address is larger than the H shift setting address In the word line between the L shift setting address and the H shift setting address, the shift redundancy to the LOW side is performed after the shift redundancy to the HIGH side, or conversely, Since the shift redundancy to the HIGH side is performed after the shift redundancy is performed, there is a problem that the shift redundancy processing is performed even though the address change is not substantially required. There has been a problem that the circuit control of the data inversion control circuit for executing the redundancy processing becomes complicated.

  Therefore, in the data inversion control circuit of the present invention, a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a twisted bit line and a bit complementary line, In a data inversion control circuit for inputting data while inverting or not inverting data in accordance with the twist of a bit line and a bit complementary line, the word line specified by the smallest word line specified address in the redundant unit block is set to the LOW side redundant word line. And the word line designated by the largest word line designation address in the redundant unit block is a HIGH side redundant word line, and both the LOW side redundant word line and the HIGH side redundant word line are used. The word line address is assigned to the LOW side redundant word so that the side redundant word line is used. The L shift setting address that is the starting point for shifting in the line direction is higher than the H shift setting address that is the starting point for shifting the word line address in the HIGH side redundant word line direction so that the HIGH side redundant word line is used. Is larger, the address data replacing means for replacing the address data of the L shift setting address and the H shift setting address is provided.

  The data inversion control circuit of the present invention includes a redundant unit block composed of a plurality of word lines and two redundant word lines, and a storage device having a bit line and a bit complementary line having a twist structure. In a data inversion control circuit for outputting data while inverting or not inverting data in accordance with the twist of a bit line and a bit complementary line, the word line specified by the smallest word line specified address in the redundant unit block is the LOW side redundant word line. And the word line designated by the largest word line designation address in the redundant unit block is a HIGH side redundant word line, and both the LOW side redundant word line and the HIGH side redundant word line are used. The word line address is assigned to the LOW side redundant word so that the side redundant word line is used. The L shift setting address that is the starting point for shifting in the line direction is higher than the H shift setting address that is the starting point for shifting the word line address in the HIGH side redundant word line direction so that the HIGH side redundant word line is used. Is larger, the address data replacing means for replacing the address data of the L shift setting address and the H shift setting address is provided.

  The memory device having the data inversion control circuit of the present invention has a redundant unit block composed of a plurality of word lines and two redundant word lines, and has a bit line and a bit complementary line having a twist structure. In a storage device having a data inversion control circuit that inputs data while inverting or not inverting with the twist of a bit line and a bit complementary line, the data inversion control circuit is the smallest in the redundant unit block The word line specified by the word line specified address is a LOW side redundant word line, the word line specified by the largest word line specified address in the redundant unit block is a HIGH side redundant word line, This is a case where the HIGH side redundant word line is used together, and the LOW side redundant word line is used. The address of the word line is set so that the L shift setting address, which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the word line, uses the HIGH side redundant word line. Is greater than the H shift set address which is the starting point for shifting in the HIGH-side redundant word line direction, the address data replacing means is provided for switching the address data of the L shift set address and the H shift set address.

  The data inversion control circuit of the present invention is a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and a bit line and a bit complementary line having a twist structure. In the memory device having the data inversion control circuit that outputs the data while inverting or not inverting the data according to the twist of the bit line and the bit complementary line, the data inversion control circuit has the smallest word line designation address in the redundant unit block. The word line specified by 1 is the LOW side redundant word line, the word line specified by the largest word line specified address in the redundant unit block is the HIGH side redundant word line, and the LOW side redundant word line and the HIGH side redundant word are Use a redundant word line on the LOW side. Thus, the L shift setting address, which is the starting point for shifting the word line address in the LOW side redundant word line direction, shifts the word line address in the HIGH side redundant word line direction so that the HIGH side redundant word line is used. In the case where it is larger than the H shift set address that is the starting point, an address data replacing means for switching the address data of the L shift set address and the H shift set address is provided.

  In the data inversion control method of the present invention, a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure, In a data inversion control method for inputting data while inverting or not inverting data according to the twist of a bit line and a bit complementary line, a word line specified by the smallest word line specified address in a redundant unit block is set as a LOW side redundant word line And the word line designated by the largest word line designation address in the redundant unit block is a HIGH side redundant word line, and both the LOW side redundant word line and the HIGH side redundant word line are used. Word line address is set to LOW side redundant word so that side redundant word line is used The L shift setting address that is the starting point for shifting in the direction is higher than the H shift setting address that is the starting point for shifting the address of the word line in the direction of the HIGH side redundant word line so that the HIGH side redundant word line is used. If it is larger, the address data of the L shift setting address and the H shift setting address are exchanged.

  Further, in the data inversion control method of the present invention, from a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure, In a data inversion control method for outputting data while inverting or not inverting data according to a twist of a bit line and a bit complementary line, a word line specified by the smallest word line specified address in a redundant unit block is a LOW side redundant word line And the word line designated by the largest word line designation address in the redundant unit block is a HIGH side redundant word line, and both the LOW side redundant word line and the HIGH side redundant word line are used. The word line address is assigned to the LOW side redundant word so that the side redundant word line is used. The L shift setting address that is the starting point for shifting in the line direction is higher than the H shift setting address that is the starting point for shifting the word line address in the HIGH side redundant word line direction so that the HIGH side redundant word line is used. Is also larger, the address data of the L shift setting address and the H shift setting address are exchanged.

  According to the present invention, when both the LOW side redundant word line and the HIGH side redundant word line are used, the address of the word line is shifted in the direction of the LOW side redundant word line so as to use the LOW side redundant word line. When the L shift setting address that is the starting point of the shift is larger than the H shift setting address that is the starting point of shifting the address of the word line in the direction of the HIGH side redundant word line so that the HIGH side redundant word line is used. By exchanging the address data of the L shift setting address and the H shift setting address, the word line shift redundancy processing at the address between the L shift setting address and the H shift setting address is prevented from being executed. Inversion control can be executed promptly.

  In particular, since it is possible to prevent execution of ineffective shift redundancy processing, it is possible to prevent the circuit control of the data inversion control circuit from becoming complicated.

  A data inversion control circuit, a memory device having the data inversion control circuit, and a data inversion control method according to the present invention include a redundant unit block including a plurality of word lines and two redundant word lines, and a twist structure. Shift redundancy using redundant word lines, bit lines and bit complementary lines, when data is input to a memory device having bit lines and bit complementary lines, or when data is output from such memory devices. The data is inverted or non-inverted in accordance with the twist.

  In particular, in a data inversion control circuit that performs data inversion or non-inversion control, the word line designated by the smallest word line designation address in the redundant unit block is the LOW side redundant word line and the largest in the redundant unit block. The word line designated by the word line designation address is used as a HIGH-side redundant word line, and both the LOW-side redundant word line and the HIGH-side redundant word line are used, and the LOW-side redundant word line is used. The address of the word line is set to the HIGH side redundant word line direction so that the L shift setting address which is the starting point for shifting the address of the word line in the LOW side redundant word line direction uses the HIGH side redundant word line. If it is larger than the H shift set address that is the starting point for shifting to So that switch the address data of the L shift setting address and H shift setting address by less data interchanging section.

  As described above, when the L shift setting address is larger than the H shift setting address, conversely, when the H shift setting address is smaller than the L shift setting address, the addresses of the L shift setting address and the H shift setting address. Even if the shift redundancy processing is performed by exchanging data, the result is the same as the case where the shift redundancy processing is performed without exchanging the address data between the L shift setting address and the H shift setting address, By exchanging address data between the L shift setting address and the H shift setting address, shift redundancy processing is not performed on the word line of the address data between the L shift setting address and the H shift setting address. The shift redundancy process can be executed promptly.

  In addition, since the number of word lines that must be subjected to shift redundancy processing can be reduced, the control mechanism for shift redundancy processing can be prevented from becoming complicated, and the data inversion control circuit can be simply configured, thereby reducing the cost. Can also be planned.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the storage device of this embodiment.

  In the storage device of this embodiment, the data signal 10s input from the data input terminal 10 is input to the input data inversion circuit 11, and the data inversion instruction input from the data inversion control circuit 20 in the input data inversion circuit 11 Based on the signal 20s, the input data is inverted or non-inverted and input to the write buffer 12, and the bit line signal 14s to be input to the bit line 14 in the write buffer 12 and the bit line signal 14s Of the bit complementary line 15s to be input to the bit complementary line 15, and a plurality of the bit line signal 14s and the bit complementary line signal 15s are generated via the write gate circuit 13. The data is input to a memory circuit 30 configured by arranging memory cells in an array.

  The write gate circuit 13 is a bit line pair designation address inputted from a bit line pair designation address signal input terminal 40 to which a bit line pair designation address signal 40s for designating a predetermined pair of bit lines 14 and bit complementary lines 15 is inputted. Based on the signal 40s, the input of the bit line signal 14s and the bit complementary line signal 15s to the designated bit line pair is controlled.

  That is, the bit line pair designation address signal 40s inputted from the bit line pair designation address signal input terminal 40 is first inputted to the bit line pair designation address signal input buffer 41 and then inputted to the decoder circuit 42 for decoding. The generated decode signal 42s and the bit line pair designation control signal 44s input from the bit line pair designation control signal input terminal 44 are input to the bit line pair designation control circuit 43 to obtain the gate control signal 43s. The gate control signal 43s is generated and input to the write gate circuit 13 to control the input of the bit line signal 14s and the bit complementary line signal 15s to the designated bit line pair.

  Further, when outputting the required data from the memory circuit 30, based on the gate control signal 43s input from the bit line pair designation control circuit 43, the read gate circuit 51 reads the data of a predetermined bit line pair, A bit line output signal of the read bit line 14 and an inverted signal of this bit line output signal, which are input to the bit complementary line output signal output from the bit complementary line 15 and input to the read amplifier circuit 52 for amplification. The output signal generated from the bit line output signal and the bit complementary line output signal is input to the output data inversion circuit 53, and the data inversion instruction input from the data inversion control circuit 20 in the output data inversion circuit 53 Based on the signal 20s, the output data is inverted or non-inverted, input to the output buffer 54, and output from the output terminal 55 as the final output signal 55s.

  The required data inversion control signal 21s is input from the data inversion control signal input terminal 21 to the data inversion control circuit 20 which is a main part of the present invention, and is used for the generation processing of the data inversion instruction signal 20s in the data inversion control circuit 20. It has been. The data inversion control signal 21s includes redundancy setting information, twist area information obtained by twisting the bit line 14 and the bit complementary line 15, and the like.

  In the data inversion control circuit 20 of FIG. 1, as shown in the flowchart of FIG. 2, the redundant unit block first checks whether to use the LOW side redundant word line and / or the HIGH side redundant word line. The number is confirmed (step S1). When both the LOW side redundant word line and the HIGH side redundant word line are used, that is, when the redundant usage number is “2”, the LOW side redundant word line and the HIGH side redundant word line are used. The address of the word line is input (step S2), and then the L shift setting address and the H shift setting address are compared. If the L shift setting address is larger than the H shift setting address (step S3) The data inversion control circuit 20 replaces the address data of the L shift setting address and the H shift setting address (step S4). .

  In this way, when the L shift setting address is larger than the H shift setting address, the L shift setting address and the H shift setting address are exchanged by exchanging the address data of the L shift setting address and the H shift setting address. The data inversion control in the data inversion control circuit 20 can be promptly executed by preventing the shift redundancy processing of the word lines at the addresses in between.

  In step S3, if the L shift set address is smaller than the H shift set address, the process proceeds to step S7 described later.

  On the other hand, if the redundant use number is not “2” in step S1, the data inversion control circuit 20 determines whether one of the LOW side redundant word line and the HIGH side redundant word line is used ( Step S5) When either one of the LOW side redundant word line and the HIGH side redundant word line is used, that is, when the redundant use number is “1”, the LOW side redundant word line used or The address of the HIGH side redundant word line is input (step S6), and the redundant address is set based on the input address of the LOW side redundant word line and / or the HIGH side redundant word line (step S7).

  Next, the data inversion control circuit 20 determines whether it is necessary to change the setting for a predetermined twist area in the twist structure based on the set redundant address (step S8).

  When the data inversion control circuit 20 determines that the setting change for the twist area is necessary, the data inversion control circuit 20 generates twist area change information (step S9), and generates final twist area information based on the twist area change information. The data inversion control circuit 20 generates and outputs a data inversion instruction signal 20s based on the final twist area information (step S11).

  On the other hand, if the number of redundant uses is “0” in step S5 and if no change in the setting for the twist area is required in step S8, the data inversion control circuit 20 sets the preset data. The inversion instruction signal 20s is generated and output (step S12).

  Based on the data inversion instruction signal 20s, data is input to the memory circuit 30 or data is output from the memory circuit 30 while performing inversion or non-inversion of data.

1 is a block diagram of a storage device according to the present invention. 4 is a control flowchart in the data inversion control circuit according to the present invention. It is a control flowchart in the conventional data inversion control circuit.

Explanation of symbols

10 Data input terminal
11 Input data inversion circuit
12 Write buffer
13 Light gate circuit
14 bit line
15 bit complement
20 Data inversion control circuit
21 Data inversion control signal input pin
30 Memory circuit
40 Bit line pair designation address signal input pin
41 Input buffer for bit line pair specified address signal
42 Decoder circuit
43 Bit line pair designation control circuit
44 Bit line pair designation control signal input pin
51 Read gate circuit
52 Read amplifier circuit
53 Data inversion circuit for output
54 Output buffer
55 Output terminal
10s data signal
14s Bit line signal
15s bit complementary signal
20s Data inversion instruction signal
21s Data inversion control signal
40s Bit line pair specified address signal
42s decode signal
44s Bit line pair designation control signal
43s Gate control signal
55s Final output signal

Claims (6)

A storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line having a twist structure and a bit complementary line, and a twist of the bit line and the bit complementary line. In the data inversion control circuit for inputting data while inverting or non-inverting the data,
The word line designated by the smallest word line designation address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designation address in the redundancy unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A data inversion control circuit comprising address data replacement means for switching the address data of the L shift setting address and the H shift setting address. A twist of the bit line and the bit complementary line from a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure. In the data inversion control circuit for outputting the data while inverting or not inverting the data,
The word line designated by the smallest word line designation address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designation address in the redundancy unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A data inversion control circuit comprising address data replacement means for switching the address data of the L shift setting address and the H shift setting address. A storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure,
In a memory device having a data inversion control circuit for inputting data while inverting or non-inverting data according to the twist of the bit line and the bit complement line,
The data inversion control circuit includes:
The word line designated by the smallest word line designation address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designation address in the redundancy unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A storage device comprising address data replacement means for switching address data of the L shift setting address and the H shift setting address. A storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure,
In a memory device having a data inversion control circuit for outputting data while inverting or non-inverting data according to the twist of the bit line and the bit complement line,
The data inversion control circuit includes:
The word line designated by the smallest word line designation address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designation address in the redundancy unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A storage device comprising address data replacement means for switching address data of the L shift setting address and the H shift setting address. A storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line having a twist structure and a bit complementary line, and a twist of the bit line and the bit complementary line. In the data inversion control method for inputting data while inverting or not inverting the data,
The word line designated by the smallest word line designation address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designation address in the redundancy unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A data inversion control method, wherein the address data of the L shift setting address and the H shift setting address are exchanged. A twist of the bit line and the bit complementary line from a storage device having a redundant unit block composed of a plurality of word lines and two redundant word lines, and having a bit line and a bit complementary line having a twist structure. In the data inversion control method for outputting data while inverting or not inverting the data,
The word line designated by the smallest word line designated address in the redundant unit block is set as the LOW side redundant word line, and the word line designated by the largest word line designated address in the redundant unit block is set as the HIGH side redundant word line. age,
When both the LOW side redundant word line and the HIGH side redundant word line are used,
The L shift setting address which is the starting point for shifting the address of the word line in the direction of the LOW side redundant word line so as to use the LOW side redundant word line uses the HIGH side redundant word line. When the address of the word line is larger than the H shift setting address that is the starting point for shifting in the HIGH side redundant word line direction,
A data inversion control method, wherein the address data of the L shift setting address and the H shift setting address are exchanged.

Images