JP2006154852A - Driving method and driving device of plasma display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably achieve such driving that a cell to be lighted is correctly lighted and a non-lighting cell is not correctly lighted based on a display data. <P>SOLUTION: Erase discharge is performed respectively by applying pulse voltages of waveforms different from each other in a first erase discharge period when the lighting cell held lighted in the previous sustain discharge period is a target and a second erase discharge period when the non-lighting cell held not lighted in the previous sustain discharge period is a target, in a reset period after the end of the sustain discharge period. As a result, the slight wall charges failing of be completely erased in the first erase discharge period, e.g. the slight wall charges accumulated in the non-lighting cell by receiving the influence of the lighting cell can be erased in the second erase discharge period and the lighting of the non-lighting cell which is intrinsically not ought to be lighted in the next address period and the sustain discharge period is prevented and thereby the improvement in a driving voltage margin is made possible. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a driving method and a driving apparatus for an AC driving type plasma display.

  In recent years, plasma display panels (PDPs) are self-luminous display devices that have good visibility, are thin and can display large screens, and are therefore attracting attention as next-generation display devices that replace CRTs. Has been. In particular, since the AC drive type PDP can have a large screen, there is an increasing expectation as a display device compatible with high-definition digital broadcasting, and a higher image quality than the CRT is required.

  FIG. 8 is a diagram illustrating an overall configuration of an AC drive type PDP device. In FIG. 8, the AC drive type PDP1 is provided with scanning electrodes Y1 to Yn and a common electrode X which are parallel to each other on one surface, and an address in the direction orthogonal to these electrodes Y1 to Yn and X is provided on the opposite surface. Electrodes A1 to Am are provided. The common electrode X is provided corresponding to each of the scanning electrodes Y1 to Yn and close thereto, and one end thereof is connected in common with each other.

  The common end of the common electrode X is connected to the output end of the X driver 2, and each scanning electrode Y 1 to Yn is connected to the output end of the Y driver 3. The address electrodes A1 to Am are connected to the output terminal of the address driver 4. These X driver 2, Y driver 3 and address driver 4 are controlled by control signals from the control circuit 5.

  The control circuit 5 generates the control signal based on the external display data D, the clock CLK indicating the read timing of the display data D, the horizontal synchronization signal HS, and the vertical synchronization signal VS, and generates the X driver 2, the Y driver 3, and This is supplied to the address driver 4.

  FIG. 9 is a diagram illustrating a cross-sectional configuration of the cell Cij in the i-th row and the j-th column which is one pixel. In FIG. 9, the common electrode X and the scanning electrode Yi are formed on the front glass substrate 11. A dielectric layer 12 for insulating the discharge space 17 is deposited thereon, and a MgO (magnesium oxide) protective film 13 is further deposited thereon.

  On the other hand, the address electrode Aj is formed on the rear glass substrate 14 disposed so as to face the front glass substrate 11, and the phosphor 15 is deposited thereon. On the rear glass substrate 14 and the address electrodes Aj, ribs 16 for preventing color mixing between cells and for maintaining a discharge gap are formed at pixel boundaries. Ne + Xe penning gas is sealed in the discharge space 17 between the MgO protective film 13 and the phosphor 15.

  FIG. 10 is a voltage waveform diagram showing an example of a driving method of the AC drive type PDP, and shows one subfield of a plurality of subfields constituting one frame. One subfield is divided into a reset period including an entire writing period and an entire erasing period, an address period, and a sustain discharge period.

  In the reset period, all the scan electrodes Y1 to Yn are first set to the ground level (0 V), and at the same time, a full-surface write pulse composed of the voltage Vs + Vw (about 330 V) is applied to the common electrode X. At this time, the potentials of the address electrodes A1 to Am are all Vaw (about 100 V). As a result, regardless of the previous display state, discharge is performed in all cells of all display lines, and wall charges are formed.

  Next, when the potentials of the common electrode X and the address electrodes A1 to Am become 0V, the voltage of the wall charges themselves exceeds the discharge start voltage in all the cells, and the discharge is started. In this discharge, since there is no potential difference between the electrodes, no wall charge is formed, and the space charge self-neutralizes and the discharge ends. This is so-called self-erasing discharge. By this self-erasing discharge, the state of all the cells in the panel becomes a uniform state without wall charges. This reset period has the effect of making all the cells the same regardless of the lighting state of each cell in the previous subfield, thereby enabling the next address (write) discharge to be performed stably. .

  Next, in the address period, in order to turn on / off each cell in accordance with display data, address discharge is performed in a line sequential manner. That is, first, a scan pulse of −Vy level (about −150 V) is applied to the scan electrode Y1 corresponding to the first display line, and a sustain discharge occurs in each address electrode A1 to Am, that is, a cell to be lit. An address pulse of voltage Va (about 50 V) is selectively applied to the corresponding address electrode Aj.

  As a result, a discharge occurs between the address electrode Aj of the cell to be lit and the scan electrode Y1, and this is used as a priming (fire) to immediately discharge the common electrode X and the scan electrode Y1 at the voltage Vx (about 50V). Transition. As a result, wall charges of an amount capable of the next sustain discharge are accumulated on the surface of the MgO protective film 13 on the common electrode X and the scan electrode Y1 of the selected cell. Thereafter, the same processing is performed for the scanning electrodes Y2 to Yn corresponding to the other display lines, and new display data is written in all the display lines.

  Thereafter, during the sustain discharge period, the sustain pulses composed of the voltage Vs (about 180 V) are alternately applied to the scan electrodes Y1 to Yn and the common electrode X to perform the sustain discharge, and the video display of one subfield is performed. . Note that the luminance of the video is determined by the length of the sustain discharge period, that is, the number of sustain pulses.

  In the above driving method, each subfield in one frame has a reset period, and full-surface write discharge is performed by applying a full-surface write pulse in each subfield. For this reason, light emission in the reset period that does not originally contribute to video display occurs in each subfield, which is a cause of lowering the contrast of the displayed video.

  In order to solve this problem, the present inventor has invented a driving method for achieving high contrast by reducing the number of full-surface write discharges per frame, and has already filed an application (Japanese Patent Laid-Open No. 5-313598). In this driving method, the full-surface write discharge in the reset period is performed only in a part of the subfields in one frame, and only the erase discharge is performed in the reset period in the other subfields.

  In such a high-contrast driving method, as shown in FIG. 11, after the end of the sustain discharge (sustain) period of the nth subfield SFn, the erase discharge is immediately performed in the reset period of the next subfield SFn + 1. The Here, by applying an erasing pulse composed of a narrow pulse (for example, a pulse width of 2 μs or less) to the common electrode X, the wall charge of each electrode is applied only to the cell that has been lit in the immediately preceding subfield SFn. Erasing is performed.

  By the way, the voltage value of various pulses for realizing the driving in which the ON cell is properly lit based on the display data and the OFF cell is not lit is an allowable range (a voltage range from the minimum value to the maximum value is referred to as a drive voltage margin). ) Exists. However, when performing the narrow erase discharge during the reset period, if the discharge start is earlier than expected due to the non-uniformity of the pixels and the change of the temperature condition, not only the necessary wall charges can be erased but also the common electrode X and There is a possibility that wall charges having an inversion polarity with respect to the state of the wall charges before erasure are formed on the scan electrode Y, which causes a decrease in the drive voltage margin.

  In order to solve such a problem, the applicant further applies an erase pulse (Slope Erase Pulse: SEP) that rises with a gentle slope after applying a narrow pulse during the reset period. A new driving method has been invented and filed (Japanese Patent Application No. Hei 10-196016) which can bring the defective state closer to the complete erase state.

  An example of this driving method is shown in FIG. FIG. 12 is a drive waveform diagram showing a part of the reset period in a certain subfield. In the lighted cell that has undergone the final sustain discharge in the immediately preceding subfield, positive charge is accumulated in the common electrode X and negative charge is accumulated in the scan electrode Y. In such a state, as shown in FIG. 12, the wall charges of the lighted cells are erased by applying an erase pulse of voltage Vs consisting of a narrow pulse to the common electrode X.

  The narrow pulse described above terminates the application of the pulse voltage immediately after the discharge is formed, and most of the charged particles generated during the discharge remain in the discharge cell space, and remain static on the wall charge of the panel dielectric layer. It is adsorbed by the electric attractive force and recombined on the wall surface to be erased. However, when strong discharge by the rectangular wave is performed in this way, wall charges having an inversion polarity with respect to the state of wall charges before erasure may be formed on the common electrode X and the scan electrode Y as described above. .

  Therefore, after performing the erasing discharge by the narrow pulse, an erasing pulse that rises with a gentle slope to the voltage Vs (hereinafter referred to as a positive blunt wave) and an erasing pulse that falls with a gentle slope to the voltage −Vy ( Hereinafter, this is referred to as a negative dull wave). As a result, a positive blunt wave that gradually changes over time, such as wall charges with reversed polarity remaining due to excessive reaction by narrow pulses, or wall charges that could not be completely erased by erase discharge by narrow pulses. And it is erased by reacting with each potential of negative blunt wave.

  That is, the amount of wall charges accumulated in the cells that have been lit in the immediately preceding subfield is not necessarily the same in all cells, and therefore the discharge start voltage of each cell varies. When a blunt wave is applied in this state, the pulse voltage during the rising of the positive blunt wave and the falling of the negative blunt wave is discharged sequentially from the cell that has reached the discharge voltage, so it is practically optimal for each cell. A voltage (a voltage approximately equal to the discharge start voltage) is applied. Thereby, the residual charge can be erased.

  However, in the above conventional technique, in the subfield other than the specific subfield in the high-contrast driving method, the erasing discharge is performed only for the cell that is lit in the immediately preceding subfield. Under the influence of the wall charge accumulated in the cell, the charge is accumulated in the non-lighted cell that was not originally lit, and it may remain without being erased. FIG. 13 is a diagram illustrating a state in which charges are accumulated in the non-lighted cells.

  As shown in FIG. 13A, in the lighted cell that has undergone the final sustain discharge in the immediately preceding subfield, positive charges are accumulated in the address electrode A and the common electrode X, and negative charges are accumulated in the scan electrode Y. . Further, even in the non-lighting cell adjacent to the lighting cell, positive and weak wall charges are accumulated in the address electrode A and the scanning electrode Y of the non-lighting cell under the influence of the wall charge accumulated in the lighting cell, Negative weak wall charges are accumulated in the common electrode X.

  In this state, when an erasing discharge by a narrow pulse is performed in the reset period of the next subfield, as shown in FIG. 13B, the state of wall charges before erasing on the common electrode X and the scanning electrode Y is shown. As a result, wall charges having an inverted polarity may be formed. Then, when the erasing discharge by the blunt wave as shown in FIG. 12 is performed thereafter, the wall charges accumulated on the lighted cells are erased and there is no residual charge as shown in FIG. 13C. .

  With respect to the lighting cell, charges that can start discharge sufficiently by the pulse voltage during the rising of the positive blunt wave and the falling of the negative blunt wave are accumulated, so by applying these positive and negative blunt waves It is possible to cause discharge and erase the residual charge. However, for non-lighted cells, the wall charge accumulated under the influence of adjacent lighted cells is weak, so even if the pulse voltage of the blunt wave is changed to the voltage Vs or -Vy, the discharge start voltage of the non-lighted cells The wall charge remains without being erased.

  In this case, for example, when a non-lighted state continues for several frames in the cell, such as a still image or a background portion of a moving image, the amount of residual charge accumulated in the non-lighted cell gradually increases. End up. When a sufficient amount of residual charge is accumulated in the non-lighted cell, but the non-lighted cell that should not be lit is lit up due to the residual charge. As a result, there is a problem that the drive voltage margin is reduced.

  FIG. 14 is a diagram for explaining this conventional problem. That is, as shown in FIG. 14, normally, in the address period, a scan pulse of −Vy level is applied to the scan electrodes Yi and Yi + 2 of the cells to be turned on according to the display data, and the addresses corresponding to the cells to be turned on. By selectively applying a Va level address pulse to the electrode A, light emission of the cell to be lit is realized.

  However, if a sufficient amount of residual charge is accumulated in a non-lighted cell that is not desired to be lit, an address pulse is applied by the positive charge on the address electrode A and a scan pulse is applied by the negative charge on the scan electrode Yi + 1. The operation is the same as the above, and a mis-discharge occurs in the non-lighted cell and a wall charge is formed. Therefore, in the next sustain discharge period, the sustain discharge is performed in the non-lighted cells, and the non-lighted cells that should not be lighted are lit.

  The present invention has been made to solve such a problem. The drive voltage margin during driving of the PDP is improved, and the cells to be lit are correctly lit based on the display data. It is an object to ensure that driving that does not light up correctly can be realized.

  In the plasma display driving method of the present invention, one frame is composed of a plurality of subfields, and each subfield performs an erasing discharge that makes the wall charge distribution in each cell uniform, and a display. A plasma display driving method comprising: an address period in which wall charges are formed in a cell to be lit according to data; and a sustain discharge period in which cells in which the wall charges are formed during the address period are discharged and emitted. The reset period includes a first erasing discharge period in which an erasing pulse for erasing and discharging the lighted cell in the immediately preceding subfield is applied to the first or second sustain discharge electrode, and the applied voltage is positive with time. A positive blunt wave pulse that continuously changes in the direction is applied to the first sustain discharge electrode, and the applied voltage continuously changes in the negative direction over time. A second erasing discharge period in which a negative blunt wave pulse is applied to the second sustain discharge electrode, and a potential difference between the arrival potential of the positive blunt wave pulse and the arrival potential of the negative blunt wave pulse is the first It is characterized by being in the vicinity of the discharge start voltage between the second sustain discharge electrode and the second sustain discharge electrode.

  Note that the present invention can be applied to a so-called high-contrast driving method. In that case, the erase discharge performed separately in the first erase discharge period and the second erase discharge period is other than a specific subfield. In the sub-field.

  In addition, the plasma display driving apparatus according to the present invention corresponds to a reset period for performing an erasing discharge for making the wall charge distribution in each cell uniform in each of a plurality of subfields constituting one frame, and display data. The plasma display panel is driven by an address period in which wall charges are formed in the cells to be lit and a sustain discharge period in which the cells in which the wall charges are formed during the address period are discharged. In the driving device, in the reset period, in the first erasing discharge period, an erasing pulse for erasing and discharging the lighted cells in the immediately preceding subfield is applied to the first or second sustain discharge electrode, Positive blunt wave pulse in which the applied voltage continuously changes in the positive direction as time passes during the second erase discharge period after the first erase discharge period Control means for controlling to apply to the second sustain discharge electrode a negative blunt wave pulse that is applied to the first sustain discharge electrode and the applied voltage continuously changes in the negative direction over time; The potential difference between the arrival potential of the positive blunt wave pulse and the arrival potential of the negative blunt wave pulse is in the vicinity of the discharge start voltage between the first sustain discharge electrode and the second sustain discharge electrode.

  Since the present invention comprises the above technical means, for example, in the reset period after the end of the sustain discharge period, the erasing discharge is performed in the first erasing discharge period for the lighted cells that were lit in the previous sustain discharge period. As a result, the wall charges on the lighted cell are erased. Furthermore, even for non-lighted cells that were not lit in the previous sustain discharge period, erasing discharge is performed based on a pulse voltage having a waveform different from that of the lit cells in the second erasing discharge period, Even weak wall charges on the non-lighted cells accumulated under the influence of the lighted cells can be erased.

  For example, in an erasing discharge intended for a non-lighted cell, a first erasing pulse whose applied voltage continuously changes in the positive direction with the lapse of time is applied to the first electrode, and the applied voltage is negative with the lapse of time. This is performed by applying a second erasing pulse that continuously changes to the second electrode. As a result, the potential difference between the first electrode and the second electrode is increased, so that even weak wall charges accumulated in the non-lighted cell due to the influence of the lighted cell can be erased.

  As described above, in the present invention, in the reset period, the erasing discharge for the lit cell and the non-lit cell is performed in the first erasing discharge period and the second erasing discharge period, respectively. The weak wall charges that cannot be completely erased during the erase discharge period, that is, the weak wall charges accumulated in the non-lighted cells under the influence of the lit cells can be erased during the second erase discharge period. As a result, it is possible to prevent non-lighted cells that should not be lit in the next address period and sustain discharge period from being turned on, and to improve the drive voltage margin.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  This embodiment shows an example in which the present invention is applied to a high-contrast driving method. In a subfield other than a specific subfield (for example, the first field in one frame), the entire writing is performed in the reset period. No discharge is performed, and only an erasing discharge is performed.

  The overall configuration of the AC drive type PDP apparatus according to this embodiment and the cross-sectional configuration of one cell are as shown in FIGS. 8 and 9, and the control means of the present invention includes the control circuit 5 of FIG. . FIG. 1 is a diagram for explaining the driving method of the PDP according to the present embodiment, and shows the configuration of subfields.

  In this embodiment, the subfield is divided into a reset period, an address period, and a sustain discharge (sustain) period. Further, the reset period is erased for a cell that has been lit in the sustain discharge period of the immediately preceding subfield. Walls accumulated in non-lighted cells under the influence of adjacent lighted cells, including cells that were not lighted during the first erasing discharge period during which discharge is performed and the sustain discharge period of the immediately preceding subfield It is divided into a second erasing discharge period in which charge erasing discharge is performed.

  In the first erasing discharge period and the second erasing discharge period, residual charges of the lit cell and the non-lit cell are erased by different applied waveforms. In the first erasing discharge period, after applying a narrow pulse to the common electrode X, an erasing pulse (hereinafter referred to as a first positive blunt wave) that gradually rises to a voltage Vs with a gradual slope is applied to the scanning electrode Y. As a result, the wall charges accumulated in the lighting cell by the sustain discharge in the immediately preceding subfield are erased by the erase discharge.

  On the other hand, in the second erasing discharge period, an erasing pulse that gradually rises to a voltage Vax with a gradual slope (this corresponds to the first erasing pulse of the present invention, which is hereinafter referred to as a second positive dull pulse). Is applied to the common electrode X (the first electrode of the present invention) and an erasing pulse that gradually falls to a voltage −Vy with a gentle slope (this corresponds to the second erasing pulse of the present invention). In the following description, this is referred to as a negative blunt wave) and applied to the scan electrode Y (second electrode of the present invention), so that the wall charges remaining in the non-lighted cells due to the influence of the adjacent lighted cells. Is erased by erasing discharge.

  FIG. 2 is a diagram showing a detailed example of the drive waveform of the AC drive type PDP according to the present embodiment, and shows one subfield other than the specific subfield in the high contrast drive method.

  As described above, in the first erasing discharge period, first, the scanning electrode Y is set to the ground level (0 V), and at the same time, a narrow pulse composed of the voltage Vs (about 180 V) is applied to the common electrode X to turn on the light. Eliminate cell wall charges. Further, after performing the erasing discharge by such a narrow pulse, the first positive blunt wave gradually rising with a gentle slope to the voltage Vs is applied to the scanning electrode Y, thereby causing an excessive reaction by the narrow pulse. Therefore, the wall charges having the inverted polarity remaining due to the cracks, the wall charges that could not be completely erased by the erasing discharge by the narrow pulse, and the like are erased from the lighting cells.

  Next, in the second erasing discharge period, a negative blunt wave gradually falling with a gentle slope to the voltage −Vy (about −150 V) is applied to the scan electrode Y, and gradually rising with a gentle slope to the voltage Vax. A second positive blunt wave is applied to the common electrode X. Thus, by applying the second positive blunt wave to the common electrode X in accordance with the application of the negative blunt wave to the scan electrode Y, the voltage difference between the X and Y electrodes can be increased, and the non-lighted cell Even weak wall charges remaining on the surface can be erased by erasing discharge.

  As described above, since the residual charge of the non-lighted cell can be erased before entering the address period, an address pulse is selectively applied to the address electrode A and a scan pulse is applied to the scan electrode Y in the next address period based on the display data. Thus, when address discharge is performed line-sequentially, it is possible to prevent a misdischarge from occurring in a non-lighted cell. Thereby, it is possible to prevent a non-lighted cell that should not be lit up from being lighted due to a sustain discharge being performed in the non-lighted cell during the subsequent sustain discharge period.

  Here, the timing at which the second positive blunt wave is applied is the same as the timing at which the negative blunt wave is applied, for example. The pulse widths (rise time and fall time) of the second positive blunt wave and negative blunt wave sufficiently reach the ultimate voltages Vax and −Vy under the resistance in the circuit that generates the respective blunt waves. Have the time span necessary for When the inclination of the obtuse wave becomes steep, the erase discharge to be executed becomes a strong discharge. Therefore, the resistance of the circuit that generates the second positive obtuse wave and the negative obtuse wave is changed gradually. Each value is set to any value. Even under such a resistance value, the rise / fall time is set to, for example, 100 μsec or more so that each blunt wave finally reaches a necessary voltage.

  In addition, the voltage Vax that the second positive blunt wave should finally reach has a potential difference from the negative blunt wave arrival voltage −Vy that discharges regardless of the presence or absence of wall charges. In the vicinity of (voltage), the voltage value is set to be lower than the discharge start voltage. This is because complete discharge occurs when the voltage difference between the X and Y electrodes becomes equal to or higher than the discharge start voltage.

  In order to match the potential difference between the voltage Vax of the second positive blunt wave applied to the common electrode X and the voltage -Vy of the negative blunt wave applied to the scan electrode Y to the vicinity of the discharge start voltage, this embodiment Then, as shown in FIG. 3, the value of the ultimate voltage Vax of the second positive blunt wave can be increased or decreased. A configuration example for this is shown in FIG. FIG. 4 shows a part of the AC drive type PDP apparatus shown in FIG. 8 and shows the voltage setting means of the present invention.

  In FIG. 4, 21 is a positive obtuse wave generating circuit for generating the second positive obtuse wave, and 22 is a negative obtuse wave generating circuit for generating the negative obtuse wave. The driver 2 and the Y driver 3 are provided. These positive obtuse wave generation circuit 21 and negative obtuse wave generation circuit 22 are connected to the common electrode X and the scan electrode Y of the AC drive type PDP 1, respectively.

  The positive blunt wave generation circuit 21 is provided with a resistor 23 for determining the rising slope of the second positive blunt wave, and the negative blunt wave generation circuit 22 has a falling slope of the negative blunt wave. A resistor 24 is provided for determining. In the present embodiment, the second positive blunt wave resistor 23 is constituted by a variable resistor, and the resistance value Rx can be increased or decreased to thereby increase the value of the second positive blunt wave ultimate voltage Vax. Can be increased or decreased. Note that the resistor 24 in the negative blunt wave generation circuit 22 may also be configured by a variable resistor so that the resistance value Ry can be increased or decreased.

  Here, the negative blunt wave and the second positive blunt wave have the same timing for starting the application, but the final ultimate voltages are different from each other, so that the resistance values Rx and Ry cannot be the same. . Further, if the second positive blunt wave is raised too steeply, the residual charge reacts excessively. Conversely, if it is too gentle, the desired voltage is not reached. Therefore, the resistance value Rx for the second positive blunt wave needs to be optimized in consideration of these.

  FIG. 5 is a diagram illustrating a state of wall charges accumulated on the address electrode A, the common electrode X, and the scan electrode Y when the PDP driving method according to the present embodiment is applied. The charge accumulation states shown in FIGS. 5A to 5C are the same as the states shown in FIGS. 13A to 13C. That is, here, the wall charges accumulated on the lighted cell at the end of the sustain discharge period are applied to the narrow pulse and the first positive blunt wave in the first erase discharge period, and in the second erase discharge period. Erasing by application of negative blunt wave.

  In this embodiment, in addition to this, as shown in FIG. 5D, by applying a second positive blunt wave in accordance with the application of the negative blunt wave in the second erasing discharge period, a lighting cell is obtained. The weak residual charge accumulated on the non-lighted cells under the influence of the above can be erased. As a result, it is possible to prevent non-lighted cells that should not be lit in the next address period and sustain discharge period from being lit, and to improve the drive voltage margin.

  In the above embodiment, during the reset period, as the erasing pulse in which the applied voltage gradually changes with the passage of time, the blunt wave in which the change rate per unit time gradually changes is represented by the common electrode X and the scanning electrode Y. However, the present invention is not limited to this. For example, as shown in FIG. 6, a triangular wave or the like in which the applied voltage gradually changes while the rate of change per unit time is constant may be applied.

  In the above-described embodiment, an example in which the rising start of the second positive blunt wave and the start of falling of the negative blunt wave are the same timing is shown, but the present invention is not limited to this. That is, as shown in FIG. 7, the start timing of the second positive blunt wave applied to the common electrode X is delayed from the start timing of the negative blunt wave applied to the scan electrode Y, and the second The pulse width of the positive blunt wave may be narrowed.

  In the above-described embodiment, as the obtuse wave applied to the common electrode X, the positive obtuse wave rising in the positive direction is applied in accordance with the negative obtuse wave with respect to the scan electrode Y. However, the first positive wave with respect to the scan electrode Y is applied. You may make it apply the negative blunt wave which falls in a negative direction according to a blunt wave. However, this is limited to the case where there is a time margin from the falling of the narrow pulse to the application of the negative positive / dull wave (for example, when an interval of 10 μs or more is provided). This is because if the interval between the narrow pulse and the negative positive blunt wave is 10 μs or less, the erase operation is performed while the charge state remains unstable.

  In the above embodiment, the description is based on the high contrast driving method. That is, in the first subfield of each frame, the entire writing and erasing are performed during the reset period, and the driving method as described above is performed after the second subfield. The principle is not necessarily limited to the high contrast driving method.

  For example, in the case where full-surface writing / narrow width erasing discharge is performed in the reset period of all subfields, the same driving method as in the present embodiment is applied to all subfields. The same effect as the embodiment can be expected. The present invention is also effective when narrow erase discharge is performed without performing full-surface write discharge in the reset period of all subfields.

  The plasma display driving method according to the present invention includes not only the method described in claim 1 but also the following modes.

  For example, full write discharge and full erase discharge are performed within a reset period only in a specific subfield among a plurality of subfields in one frame, and the full write discharge is performed within the reset period in other subfields. , An erasing discharge for erasing wall charges accumulated in the cell is performed, and the erasing discharge divided into the first erasing discharge period and the second erasing discharge period is performed as described above. Implement in subfields other than subfields.

  In the erase discharge in the second erase discharge period, the first erase pulse in which the applied voltage continuously changes in the positive direction with the passage of time is applied to the first electrode, and the applied voltage is negative with the passage of time. The second erasing pulse that continuously changes in the direction may be applied to the second electrode.

  Further, the pulse widths of the first and second erase pulses have a time width necessary to reach the ultimate voltage of the first and second erase pulses.

  The waveforms of the first and second erase pulses may be waveforms in which the rate of change of applied voltage per unit time changes with time.

  The waveforms of the first and second erase pulses may be waveforms having a constant rate of change of applied voltage per unit time.

  Further, the potential difference between the ultimate voltage of the first erase pulse and the ultimate voltage of the second erase pulse is greater than the discharge start voltage in the vicinity of the discharge start voltage between the first electrode and the second electrode. It may be a small value.

  Further, at least one of the ultimate voltage of the first erase pulse and the ultimate voltage of the second erase pulse may be variable.

  Further, the rising start timing of the first erase pulse may be the same timing as or the timing later than the falling start timing of the second erase pulse.

  The plasma display driving apparatus according to the present invention includes not only the apparatus described in claim 2 but also the following aspects.

  For example, the control means performs full write discharge and full erase discharge within a reset period only in a specific subfield among a plurality of subfields in one frame, and within the reset period in other subfields. An erasing discharge for erasing the wall charges accumulated in the cell is performed without performing the full-surface writing discharge, and an erasing discharge performed separately in the first erasing discharge period and the second erasing discharge period. , Control is performed so as to be performed in subfields other than the specific subfield.

  In the second erasing discharge period, the control means applies a first erasing pulse whose applied voltage continuously changes in the positive direction over time to the first electrode, and the applied voltage is lapsed over time. At the same time, by applying a second erase pulse that continuously changes in the negative direction to the second electrode, erase discharge for the non-lighted cell may be performed.

  The control means may apply a pulse voltage having a waveform in which the rate of change per unit time of the applied voltage changes with time as the first and second erase pulses.

  Further, the potential difference between the ultimate voltage of the first erase pulse and the ultimate voltage of the second erase pulse is set to be greater than the discharge start voltage in the vicinity of the discharge start voltage between the first electrode and the second electrode. You may have a voltage setting means to set to a small value.

  The voltage setting means may be a means for varying at least one of the arrival voltage of the first erase pulse and the arrival voltage of the second erase pulse.

  Further, at least one of the first resistor in the pulse generation circuit that generates the first erase pulse and the second resistor in the pulse generation circuit that generates the second erase pulse is configured by a variable resistor. The voltage setting means may be configured accordingly.

  The resistance value of the first resistor and the resistance value of the second resistor may be different from each other.

  Further, the control means may set the rising start timing of the first erase pulse to the same timing as or a timing later than the falling start timing of the second erase pulse.

It is a block diagram of the subfield for demonstrating the drive method of AC drive type PDP by this embodiment. It is a figure which shows the detailed example of the drive waveform of AC drive type PDP by this embodiment. It is a figure which shows a mode that the ultimate voltage Vax of a 2nd positive blunt wave is made variable. It is a figure which shows the hardware structural example for making the ultimate voltage Vax of the 2nd positive blunt wave variable. It is a figure which shows the state of the wall charge accumulate | stored on each electrode when the drive method of AC drive type PDP by this embodiment is applied. It is a figure which shows the other example of the drive waveform of AC drive type PDP by this embodiment. It is a figure which shows the other example of the starting timing of the 2nd positive blunt wave applied in this embodiment. It is a figure which shows the whole structure of an alternating current drive type plasma display apparatus. It is a figure which shows the cross-sectional structure of the cell Cij of the i-th row | line | column j which is 1 pixel. It is a wave form diagram which shows the example of the drive method of the conventional alternating current drive type PDP. It is a block diagram of the subfield for demonstrating the drive method of the conventional alternating current drive type PDP. It is a wave form diagram which shows the example of the drive method of the conventional alternating current drive type PDP. It is a figure which shows the state of the wall charge accumulate | stored on each electrode at the time of completion | finish of a sustain discharge and a reset period when the drive method of the conventional alternating current drive type PDP is applied. It is a figure for demonstrating the problem at the time of applying the drive method of the conventional alternating current drive type PDP.

Explanation of symbols

1 AC drive type PDP
2 X driver 3 Y driver 21 Positive obtuse wave generation circuit 22 Negative obtuse wave generation circuit 23, 24 Resistance

Claims (4)

One frame is composed of a plurality of subfields, and each subfield has a reset period in which an erasing discharge is performed to make the wall charge distribution in each cell uniform, and a cell to be turned on in accordance with display data A plasma display driving method having an address period in which wall charges are formed therein and a sustain discharge period in which cells in which the wall charges are formed during the address period are discharged.
The reset period includes a first erasing discharge period in which an erasing pulse for erasing and discharging the lighted cells in the immediately preceding subfield is applied to the first or second sustain discharge electrode;
Applying a positive blunt wave pulse whose applied voltage continuously changes in the positive direction over time to the first sustain discharge electrode, and applying a negative blunt wave pulse whose applied voltage continuously changes in the negative direction over time A second erase discharge period applied to the second sustain discharge electrode,
The plasma characterized in that the potential difference between the arrival potential of the positive blunt wave pulse and the arrival potential of the negative blunt wave pulse is in the vicinity of the discharge start voltage between the first sustain discharge electrode and the second sustain discharge electrode. How to drive the display. The first erasing discharge period includes a period in which a positive blunt wave pulse whose applied voltage continuously changes in the positive direction as time passes is applied to the second sustain discharge electrode,
2. The method for driving a plasma display according to claim 1, wherein the second erasing discharge period is a period in which erasing discharge is performed for a non-lighted cell. In each of a plurality of subfields constituting one frame, a reset period for performing an erasing discharge for uniform distribution of wall charges in each cell, and wall charges in the cells to be turned on according to display data. A plasma display driving apparatus configured to drive a plasma display panel in an address period to be formed and a sustain discharge period in which a cell in which wall charges are formed during the address period is discharged and emitted.
In the reset period, in the first erasing discharge period, an erasing pulse for erasing and discharging the lighted cells in the immediately preceding subfield is applied to the first or second sustain discharge electrode,
In the second erasing discharge period after the first erasing discharge period, a positive blunt wave pulse whose applied voltage continuously changes in the positive direction as time passes is applied to the first sustain discharge electrode, and the applied voltage Control means for controlling to apply a negative blunt wave pulse that continuously changes in the negative direction over time to the second sustain discharge electrode,
The plasma characterized in that the potential difference between the arrival potential of the positive blunt wave pulse and the arrival potential of the negative blunt wave pulse is in the vicinity of the discharge start voltage between the first sustain discharge electrode and the second sustain discharge electrode. Display drive device. The control means includes a control for applying a positive blunt wave pulse whose applied voltage continuously changes in the positive direction as time passes to the second sustain discharge electrode during the first erasing discharge period,
4. The plasma display driving apparatus according to claim 3, wherein the second erasing discharge period is a period in which erasing discharge is performed on a non-lighted cell.

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