JP2006154483A - Drive circuit for display device and flexible printed wiring board, and active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust the sampling timing of a video signal in a drive circuit for an LCD display device. <P>SOLUTION: Drive signals from a driving IC 11 and a reference power source 12 are supplied to an LCD panel 16 through an FPC 14. The FPC 14 generates a switching signal by branching one of a high-potential voltage signal and a low-potential voltage signal VSS according to propagation delay characteristics of the LCD panel 16 and supplies the switching signal to a phase switching circuit in the driving IC 11. The phase switching circuit in the driving IC 11 outputs one of two clock signals having different phases selectively according to the switching signal and supplies it to the LCD panel 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to timing adjustment of a sampling clock signal for driving an active matrix display device such as a display device drive circuit, particularly a liquid crystal display device.

  Liquid crystal display devices are used in many devices because they are thin, lightweight and have low power consumption.

  In general, in an active matrix liquid crystal display device, a video signal (analog video signal or digital video signal) or a clock signal is supplied from a drive IC, and a drive voltage signal is supplied from a power supply via an FPC (flexible printed wiring board). In the liquid crystal panel, a thin film transistor (TFT) as a switching element is provided in each pixel, and the on / off state of the pixel TFT is controlled by a gate line extending in the row direction, and a data line extending in the column direction via the pixel TFT. Display data is supplied to each pixel. Around the display unit of the liquid crystal panel, a vertical driver (V driver) for sequentially controlling the gate lines and a horizontal driver (H driver) for supplying display data to the data lines at a predetermined timing are provided. The H driver is controlled to be turned on / off by a horizontal shift register (HSR) that sequentially shifts a horizontal start signal (HST) according to a horizontal clock signal (HCLK) and a start signal from each horizontal register, and outputs a video signal at a desired timing. It has a TFT to sample. Since the signal propagation characteristics in the liquid crystal panel differ from one liquid crystal panel to another due to variations in transistor characteristics, the video signal sampling timing differs even when the same clock signal is supplied from the drive circuit to the liquid crystal panel. If the signal propagation delay amount of the liquid crystal panel is set, for example, so that the sampling timing is approximately in the middle of the optimal sampling period of the video signal, sampling is performed within the optimal sampling period even if there is some variation in delay characteristics. The timing can be positioned, and the sample hold margin can be widened to cope with a liquid crystal panel having various signal propagation characteristics.

  The following patent document does not relate to a technique for adjusting a sampling timing when a video signal is sampled and supplied to the pixel TFT, but as a similar technique, an analog video signal is converted into a digital signal. A technique for adjusting the sampling timing of A / D is described. Signals of four different phases are output from the phase control circuit to the A / D within one period of the sampling clock. A / D samples an analog video signal with sampling clocks having different phases, and outputs an 8-bit digital signal to a video processing circuit. A sampling clock having an optimum phase is selected from the four phases and set to the optimum sampling phase.

WO99 / 42989

  However, in recent years, particularly in liquid crystal panels and the like, there has been a demand for higher driving frequency, and the optimal sampling period of video signals has been gradually shortened in response to the demand for higher driving frequency. It has been difficult to maintain the sampling timing, and there has been a problem in that the image quality is lowered and the yield is lowered due to the deviation of the sampling timing.

  One solution to this problem is to provide a sample hold switch that adjusts the phase of the clock signal in the driver IC that generates the clock signal and supplies it to the panel, thereby adjusting the phase of the clock signal. . However, even if the sample hold switch can be adjusted on the user side so that the optimum phase can be set for each panel model, such as phase φ1 for the A model panel and phase φ2 for the B model panel, In some cases, high resolution cannot be obtained even if sampling is performed at a set phase for each model, and as a result, the panel must be processed as a defective product. . Therefore, it is required that the phase of the clock signal can be adjusted according to each panel, not for each model, but providing a circuit for adjusting the phase of the clock signal separately complicates the configuration and increases the cost. And the burden on the user side is increased.

  An object of the present invention is to provide a drive circuit or the like that can compensate for delay characteristic variation of a display device with a simple configuration and can maintain or improve image quality.

  The present invention is a drive circuit for driving an active matrix display device, which selectively outputs a clock signal having a different phase according to a switching signal, a power supply for outputting a voltage signal, and a power supply from the power supply. A flexible printed wiring board that supplies the voltage signal and the clock signal from the driving IC to the display device, the printed wiring board supplying the voltage signal to the driving IC as the switching signal. And

  The present invention also provides a flexible printed wiring board for supplying a drive signal for driving an active matrix display device, a high potential power supply voltage signal line for supplying a high potential power supply voltage signal to the display device, and a low potential power supply. A low potential power supply voltage signal line for supplying a voltage signal to the display device; a clock signal line for supplying a clock signal to the display device; and either the high potential power supply voltage signal line or the low potential power supply voltage signal line. The switching signal line is branched, and includes a switching signal line that supplies a switching signal to a driving IC that generates the clock signal to switch the phase of the clock signal.

  In addition, the present invention is an active matrix display device, which is a display panel having active matrix pixels, a driver IC that selectively outputs a clock signal having a different phase according to a switching signal, and the clock signal and voltage. A flexible printed wiring board that supplies a driving signal including a signal to the display panel and supplies a switching signal obtained by branching the voltage signal to the driving IC to switch a phase of the clock signal. To do.

  In the present invention, focusing on supplying a voltage signal to the display device via the flexible printed wiring board, the voltage signal is branched and supplied to the drive IC as a switching signal. The driving IC switches and outputs clock signals having different phases according to the switching signal and supplies the clock signals to the display device via the flexible printed wiring board. For example, the driving IC selectively outputs a clock signal having a relatively early phase (advanced) and a clock signal having a phase delayed. When the propagation delay characteristic of the display device is good, a clock signal whose phase is delayed according to the switching signal is supplied to the display device. When the propagation delay characteristic of the display device is poor (the delay time is large), Then, a clock signal having an early phase is supplied to the display device.

  According to the present invention, since the switching signal for switching the phase of the clock signal output from the driving IC is generated using the voltage signal of the flexible printed wiring board, the phase of the clock signal can be switched with a simple configuration. Accordingly, variation in delay characteristics among display devices can be eliminated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Overall configuration>
First, the overall configuration of the active matrix display device according to the present embodiment will be described. The display device shown in FIG. 1 is a liquid crystal display device mounted on, for example, a mobile phone, and includes a liquid crystal display panel (LCD panel) 16 configured by enclosing liquid crystal between a pair of substrates, and the LCD panel 16. A drive circuit 10 for driving is provided. The drive circuit 10 is supplied with a video signal (DATA in the figure), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a clock (MCLK), and based on these signals, analog video signals (R, G, B signals) ) And a flexible printed wiring board (FPC) 14 for supplying the LCD panel 16 with a driving IC 11 for generating and outputting a clock signal, a reference power supply 12, various driving signals from the driving IC 11 and a power supply voltage signal from the reference power supply 12. It is comprised.

  In the LCD panel 16, a thin film transistor (TFT) is provided as a switching element in each pixel, and on / off of the TFT is controlled by a gate line extending in the row direction, and each data line extending in the column direction via the TFT is controlled. This is an active matrix LCD panel that enables display for each pixel by supplying display data to the pixel. Around the display unit 26 of the panel, a horizontal driver for supplying display data to the data lines at a predetermined timing and a vertical driver for sequentially controlling the gate lines are formed. The horizontal driver sequentially shifts the horizontal start pulse (HST) in accordance with the clock signal (HCLK) supplied from the FPC 14 via the pad 15. The horizontal direction shift register (HSR) 20 and the start pulse from the HSR 20 are sequentially shifted. And a sampling circuit 24 for sampling the analog video signal. The clock signal (HCLK) is level-adjusted by the level shifter (L / S) 18 and supplied to the HSR 20, and the video signal sampled by the sampling circuit 24 is supplied to the data line. The vertical direction driver has a vertical direction register 28, which shifts the vertical start pulse (VST) sequentially using the vertical clock (VCLK) as a clock in accordance with the number of gate lines of the LCD panel 16 and performs a predetermined logical operation before gate. Output to line.

  The driving IC 11 generates a horizontal clock (HCLK), a horizontal start pulse (HST), a vertical clock (VCLK), a vertical start pulse (VST), etc. according to Hsync, Vsync, and dot clock (DOTCLK). (T / C). DOTCLK is supplied to the H counter via a frequency dividing circuit. The H counter counts DOTCLK every 1H period and outputs the count value to the decoder. The pulse signal decoded by the decoder is output as HCLK through the logic gate. Another decoder obtains a timing immediately before the start of the 1H period based on the count value and generates a pulse signal. This pulse signal from the decoder is similarly output as HST via the logic gate. VCLK and VST are also generated and output in the same manner, and these generation methods are disclosed in, for example, Japanese Patent Laid-Open No. 2001-356746.

  Further, the driving IC 11 has a phase switching circuit that switches the phase of the generated HCLK in two stages. The configuration of the phase switching circuit is arbitrary, and includes two delay circuits that respectively generate relatively early phase HCLK and late phase HCLK, and a selector switch that selectively switches and outputs these delay circuits. be able to. The driving IC 11 has a switching terminal for inputting a switching signal from the outside, and the switching signal is supplied to the switch via the switching terminal. The selector switch selectively switches one of the two delay circuits according to the switching signal and outputs one of the two phases early and late. The switching signal is supplied from the LCD panel 16 side that should output HCLK, more specifically from the FPC 14 side.

  The reference power supply 12 generates and outputs VDD (high potential power supply voltage) and VSS (low potential power supply voltage). Note that VSS may be GND. For example, VDD = 8V and VSS = 0V. HCLK, HST, VCLK, VST and video signals R, G, and B from the driving IC 11 and VDD and VSS from the reference power supply 12 are supplied to the LCD panel 16 via the signal lines of the FPC 14.

  In addition to these signals, the FPC 14 has a switching signal line for supplying a switching signal to the phase switching circuit of the driving IC 11. This switching signal line is obtained by branching either the VDD signal line or the VSS signal line in the FPC 14, and whether the VDD signal line or the VSS signal line is branched depends on the degree of delay characteristics of the LCD panel 16. Set depending on.

  Hereinafter, the phase switching circuit and the FPC 14 in the driving IC 11 will be described in more detail.

<Phase switching circuit>
FIG. 2 shows the configuration of the phase switching circuit 30 provided in the driving IC 11. The phase switching circuit 30 includes a delay circuit 34 having a delay time t1, a delay circuit 36 having a delay time t2 (t1 <t2), and an input side for alternatively operating the delay circuit 34 and the delay circuit 36. A switch 32 and an output side switch 38 are provided. In the figure, the delay circuit 34 has one delay element (inverter), and the delay circuit 36 has three delay elements (inverters), and t2 = t1 × 3 is set. Times t1 and t2 can be set arbitrarily.

  The input side switch 32 is composed of a CMOS TFT, the horizontal clock HCLK generated by the timing controller T / C of the driving IC 11 is supplied to the input terminal, the switching signal SW from the FPC 14 and the inversion inverted by the inverter are supplied to the gate terminal. A signal is supplied. A delay circuit 34 is connected to one of the two output terminals of the input side switch 32, and a delay circuit 36 is connected to the other. The same applies to the output side switch 38. The delay circuit 34 is connected to one of the two input terminals of the output side switch 38, the delay circuit 36 is connected to the other, and the inverted signal of the switching signal SW is supplied to the gate terminal. .

  If the switching signal SW is a binary signal (H and L), and the switching signal SW is H (Hi), the upper TFTs of the input side switch 32 and the output side switch 38 are both turned ON, and HCLK is a delay circuit 34. To the clock signal line of the FPC 14. The delay time of HCLK at this time is the delay time t1 in the delay circuit 34, which is a signal having a relatively early phase.

  On the other hand, when the switching signal SW is L (Low), both the lower TFTs of the input side switch 32 and the output side switch 38 are turned on, and HCLK is supplied to the clock signal line of the FPC 14 and further to the HSR 20 via the delay circuit 36. The The delay time of HCLK at this time is the delay time t2 in the delay circuit 36, which is a signal with a relatively delayed phase.

  As described above, it is possible to selectively supply two HCLKs having different phases to the HSR 20 of the LCD panel 16 by the switching signal SW from the FPC 14. Therefore, when the LCD panel 16 is given and its propagation delay characteristic is measured, if the delay characteristic is good (within the normal delay range), the signal level is L to select the delay circuit 36. When the switching signal SW is supplied to the LCD panel 16 and the delay characteristic of the LCD panel 16 is poor (the delay amount is large), the signal level is switched to H so that the delay circuit 34 is selected to compensate for the delay amount. By supplying the signal SW to the LCD panel 16, it is possible to cope with variations in individual propagation delay characteristics of the LCD panel 16.

<FPC>
FIG. 3 schematically shows the configuration of the FPC 14 in FIG. The FPC 14 has a plurality of signal lines for supplying each signal from the driving IC 11 and the reference power supply 12 to the LCD panel 16, but generates a switching signal line by branching either the VDD signal line or the VSS signal line in the middle. Then, a switching signal is supplied to the driving IC 11 using this switching signal line. FIG. 3A shows a case where the switching signal line is generated by branching the VDD signal line, and the level of the switching signal SW becomes the VDD level, that is, H. FIG. 3B shows a case in which the switching signal line is generated by branching the VSS signal line, and the level of the switching signal SW becomes the VSS level, that is, L. As described above, a plurality of (two in this embodiment) delay circuits in the phase switching circuit of the driving IC 11 can be selected by setting the level of the switching signal SW to either H or L. The FPC 14 has already formed a VDD signal line for supplying a high potential voltage signal from the reference power supply 12 to the LCD panel 16 and a VSS signal line for supplying a low potential voltage signal. In the present embodiment, paying attention to this, the existing circuit of the FPC 14 is not provided without separately providing a circuit for generating the switching signal SW in the LCD panel 16 or separately outside the LCD panel 16. By using this signal line, the delay circuit can be selected without increasing the number of parts. 3A and 3B is prepared in advance, and the delay characteristics of the LCD panel 16 are measured. As a result, if the delay characteristics are good, one end of the FPC 14 in FIG. If the delay characteristic is poor when connected to the pad 15, one end of the FPC 14 in FIG. 3A may be connected to the pad 15 of the LCD panel 16. The driving IC 11 is connected to the other terminal of the FPC 14, and the switching signal line of the FPC 14 is connected to the switching terminal of the driving IC 11. Therefore, the switching signal SW corresponding to the propagation delay characteristic of the LCD panel 16 is supplied to the switching terminal of the driving IC 11, and either one of the two phases of HCLK is output according to the switching signal SW. As a result, HCLK having a relatively delayed phase is output to the LCD panel 16 having good propagation delay characteristics, and HCLK having a relatively early phase is output to the LCD panel 16 having poor propagation delay characteristics. And supplied to the HSR 20 of the LCD panel 16.

  FIG. 4 shows a configuration in which the driving IC 11, the reference power supply (panel power supply) 12, and the LCD panel 16 are connected by the FPC 14. This is a case where the propagation delay characteristic of the LCD panel 16 is poor. The FPC 14 is the FPC 14 shown in FIG. 3A, that is, the FPC 14 that branches from the VDD signal line and generates a switching signal line. The switching signal line of the FPC 14 is connected to the switching terminal of the driving IC 11, and the switching signal from the FPC 14 is supplied to the phase switching circuit 30 of the driving IC 11 through this switching terminal. Since the level of the switching signal is VDD, that is, H, the delay circuit 34 in the phase switching circuit 30 is selected, and HCLK having a relatively early phase is generated and output. HCLK having an early phase is supplied to the HSR 20 of the LCD panel 16 via the clock signal line of the FPC 14. Although HCLK is delayed because the propagation delay characteristic in the LCD panel 16 is poor, the propagation delay in the LCD panel 16 is canceled because the HCLK having an early phase is originally supplied from the driving IC 11, and the video at the optimum sampling timing. The display data can be supplied to the data line by sampling the signal.

  5 and 6 show sampling timings in the HSR 20 and the sampling circuit 24 when the phase of the HCLK is adjusted by controlling the phase switching circuit 30 in the driving IC 11 as described above. Yes. FIG. 5 shows the configuration of the HSR 20 and the sampling circuit 24. HCLK, its inverted clock and horizontal start pulse HST are supplied from the FPC 14 to the shift register constituting the HSR 20 via the pad 15. HCLK and its inverted clock are supplied to the shift register. Each shift register sequentially shifts HST in accordance with HCLK and supplies it to the sampling circuit 24. The sampling circuit 24 has a switching TFT, and a video signal from the FPC 14 is supplied to an input terminal of the sampling circuit 24. An output of a shift register, that is, HST synchronized with HCLK is supplied as a sampling pulse to a gate terminal via an inverter. The The video signal is sampled at the timing when HCLK rises to H and supplied to the data line.

  FIG. 6 is a timing chart showing the sampling timing of the video signal by HCLK. FIGS. 6A and 6B are timing charts in the case of the LCD panel 16 having good propagation delay characteristics (fast delay time). As shown in FIG. Through H.36, HCLK delayed in phase is supplied. HCLK is delayed by a predetermined time T1 within the LCD panel 16 and, as a result, provides an optimum sampling timing when the video signal reaches a certain level as shown in FIG. 6B. On the other hand, FIGS. 6C and 6D are timing charts for the LD panel 16 having poor propagation delay characteristics (slow delay time), and as shown in FIG. HCLK having an early phase is supplied through the delay circuit 34 (rises at an earlier timing than HCLK in FIG. 6A). Although HCLK is delayed by a predetermined time T2 (T1 <T2) in the LCD panel 16, since the original HCLK phase is early, the delay of (T2-T1) is almost canceled, as shown in FIG. Even in this case, the optimum sampling timing almost the same as in FIG. 6B can be provided.

  Note that both T2 and T1 vary depending on the individual LCD panel 16, and the phase switching circuit 30 in the driving IC 11 is configured to selectively switch and output two HCLKs having a predetermined phase difference. It is difficult to completely cancel -T1). However, even in the case of the LCD panel 16 that has been treated as defective in the past because of poor propagation delay characteristics even in the same model, in this embodiment, the level of the video signal is constant by outputting HCLK having a fast phase. Thus, the LCD panel 16 is not wasted.

  As described above, in this embodiment, the phase switching circuit 30 is provided in the driving IC 11, and the phase switching circuit 30 is controlled to be switched according to the switching signal generated by the FPC 14. Accordingly, the video signal can be sampled at the optimum timing by adaptively adjusting the sampling timing. Further, since the switching signal for switching control of the phase switching circuit 30 is supplied by branching the VDD signal or the VSS signal in the FPC 14, the number of parts is not increased, and the LCD panel 16 has a simple configuration. It is possible to switch reliably.

  FIG. 7 shows a manufacturing flowchart of the LCD display device according to this embodiment. First, the propagation delay characteristic of the LCD panel 16 is measured (S101). Any method can be used to measure the propagation delay characteristics. For example, a TEG (Test Element Group) is created and the signal delay is actually measured. The drive frequency is changed to display a black and white burst signal on the LCD panel, and sampling is performed. For example, the amount of delay is measured by visually observing black and white blur due to timing delay.

  After measuring the propagation delay characteristics, it is determined whether the delay amount is within a predetermined range (S102). If it is within the predetermined range, the delay circuit 36 is selected to generate HCLK with a phase delay (S103). Then, the FPC 14 having the switching signal line branched from the VSS is selected as the FPC 14 and connected to the LCD panel 16 so that the delay circuit 36 is selected in the phase switching circuit 30 of the driving IC 11 (S104). On the other hand, if the delay amount exceeds the predetermined range, the delay circuit 34 is selected to generate HCLK having an early phase (S105). Then, the FPC 14 having a switching signal line branched from VDD is selected as the FPC 14 and connected to the LCD panel 16 so that the delay circuit 34 is selected in the phase switching circuit 30 of the driving IC 11 (S106). The series of steps shown in FIG. 7 can be automated. That is, a propagation delay characteristic evaluation unit and an FPC selection unit are provided, and the LCD panel 16 is supplied to the propagation delay characteristic evaluation unit to evaluate the delay amount. The obtained delay amount is compared with a predetermined range, and if it is within the predetermined range, the FPC 14 is taken out from the stocker of the FPC 14 having the VSS branch line and connected to the LCD panel 16, otherwise, the FPC 14 having the VDD branch line is connected. The FPC 14 is taken out from the stocker and connected to the LCD panel 16. The measurement of the delay amount, the comparison with the predetermined range, and the selection of the FPC 14 can be controlled by a computer.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this, A various deformation | transformation is possible.

  For example, the present embodiment can be applied to a high-resolution LCD display device having a high drive frequency, but may be applied to any active matrix display device regardless of the drive frequency.

  In this embodiment, the switching signal is generated by branching the voltage signal from the reference power supply 12, but the VDD of the reference power supply 12 is a relatively high voltage (for example, 8V), and the driving IC 11 has a high voltage. Can be supplied and only a low voltage signal can be supplied, a VDD (for example, 3V) signal supplied from the driving IC 11 to the FPC 14 is branched by the FPC 14 to generate a switching signal, which is supplied to the switching terminal of the driving IC 11. It is good also as a structure. FIG. 8 shows the configuration in this case. The VDD signal from the driving IC 11 is fed back from the FPC 14 to the switching terminal, and the phase switching circuit 30 is controlled to be switched by this VDD signal.

In this embodiment, VDD or VSS is branched in the FPC 14 to generate a switching signal. However, since VDD and VSS are supplied to the LCD panel 16, the VDD or VSS is not in the FPC 14 but in the LCD panel 16. The switching signal may be generated by branching VSS. The switching signal branched in the LCD panel 16 is supplied to the switching terminal of the driving IC 11 via the switching signal line in the FPC 14. In the LCD panel 16, the VDD signal line and the VSS signal line are insulated from each other by an interlayer insulating film such as SiO ₂ to form a multilayer structure. Therefore, for example, when a multilayer structure is formed in the LCD panel 16 such as VDD signal line / first interlayer insulating film / switching signal line / second interlayer insulating film / VSS signal line, and switching signals are generated by branching from VDD. When the first interlayer insulating film is destroyed by laser irradiation or the like, the VDD signal line and the switching signal line are short-circuited, and the switching signal is generated by branching from the VSS, the second interlayer insulating film is irradiated by laser irradiation or the like. The VSS signal line and the switching signal line may be short-circuited by destruction. Alternatively, the VSS signal line and the switching signal line are short-circuited in the default state, and in the case of the LCD panel 16 having good propagation delay characteristics, it is used in the default state and HCLK having a slow phase is supplied to the LCD panel 16 from the driving IC 11. In the case of the LCD panel 16 having poor propagation delay characteristics, the connection between the VSS signal line and the switching signal line is broken by laser irradiation and disconnected, and an insulating film between the switching signal line and the VDD signal line is provided. It may be broken by laser irradiation and short-circuited. FIG. 9 shows the configuration in this case. FIG. 9A shows the LCD panel 16 in a default state, in which the VSS signal line and the switching signal line are short-circuited in the LCD panel 16. The level of the switching signal is L, and HCLK delayed in phase is supplied from the driving IC 11. FIG. 9B shows the case of the LCD panel 16 having poor propagation delay characteristics. The VSS signal line and the switching signal line are disconnected by laser irradiation, and the insulating film between the VDD signal line and the switching signal line is broken. This is the case when it is short-circuited. The level of the switching signal is H, and HCLK having an early phase is supplied from the driving IC 11.

  Further, in this embodiment, the branch point when the switching signal is branched from either VDD or VSS may be an arbitrary position in the FPC 14 or the LCD panel 16, and in the case of branching in the FPC 14, it is shown in FIG. In addition to branching on the side closer to the driving IC 11, the VDD and VSS branch points are set at different positions so that the two types of FPCs 14 shown in FIGS. 3A and 3B can be easily identified. , Etc. are also possible. It may be preferable that the switching signal line branched from VDD or VSS is branched in a different direction from the other signal line in order to avoid a short circuit with the other signal line that is not branched. In FIG. 3A, the branch line from VDD is wired between VDD and VSS, but the branch line from VDD is wired on the side opposite to VSS. However, it is necessary to change the switching terminal array of the driving ICs accordingly.

  In the present embodiment, when the switching signal is branched from VDD and the level is set to H, HCLK having an early phase is output from the driving IC 11, and when the switching signal is branched from VSS and the level is set to L. However, when the switching signal is branched from VDD and its level is set to H, it may be configured to output HCLK having a slow phase. Considering disconnection of the switching signal line or the like, it may be preferable to configure so that HCLK having a slow phase is output from the driving IC 11 when the level of the switching signal is L.

1 is an overall configuration diagram of a display device according to an embodiment. FIG. 2 is a configuration diagram of a phase switching circuit of the driving IC in FIG. 1. It is a block diagram of FPC in FIG. It is explanatory drawing which shows the branch of the switching signal line from VDD signal line. It is a block diagram of the horizontal direction shift register and sampling circuit of FIG. It is a timing chart which shows the sampling timing of embodiment. It is a manufacturing method flowchart of an embodiment. It is another explanatory view showing the branch of the switching signal line from the VDD signal line. It is branch explanatory drawing in an LCD panel.

Explanation of symbols

  10 driving circuit, 11 driving IC, 12 reference power supply, 14 flexible printed wiring board (FPC), 16 LCD panel, 30 phase switching circuit.

Claims (3)

A drive circuit for driving an active matrix display device,
A driving IC that selectively outputs clock signals having different phases according to the switching signal;
A power supply that outputs a voltage signal;
A flexible printed wiring board that supplies the display device with the voltage signal from the power source and the clock signal from the driving IC, and the printed wiring board that supplies the voltage signal to the driving IC as the switching signal;
A drive circuit for a display device, comprising: A flexible printed wiring board for supplying a drive signal for driving an active matrix display device,
A high potential power supply voltage signal line for supplying a high potential power supply voltage signal to the display device;
A low potential power supply voltage signal line for supplying a low potential power supply voltage signal to the display device;
A clock signal line for supplying a clock signal to the display device;
A switching signal line formed by branching either the high-potential power supply voltage signal line or the low-potential power supply voltage signal line, and supplying a switching signal to a drive IC that generates the clock signal to A switching signal line for switching between
A flexible printed wiring board for driving a display device, comprising: An active matrix display device,
A display panel having active matrix pixels;
A driving IC that selectively outputs clock signals having different phases according to the switching signal;
A flexible printed wiring board that supplies a driving signal including the clock signal and a voltage signal to the display panel, and supplies a switching signal obtained by branching the voltage signal to the driving IC to switch the phase of the clock signal;
An active matrix display device comprising:

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