JP2006148105A5

JP2006148105A5 -

Info

Publication number: JP2006148105A5
Application number: JP2005330614A
Authority: JP
Filing date: 2005-11-15
Publication date: 2008-12-25

Claims

A first chip package;
A module board;
A first conductive member interposed between the first chip package and the module substrate;
A semiconductor module comprising: a protector that pressurizes the first conductive member, the module substrate, and the first chip package.

The semiconductor module according to claim 1, wherein the first conductive member includes one layer and a conductive pad.

The semiconductor module according to claim 1, wherein the first chip package includes a plurality of chips and a plurality of substrates.

The semiconductor module according to claim 1, wherein the protector serves as a heat sink for the first chip package.

The semiconductor module according to claim 4 , wherein the heat sink is connected to the module substrate and pressurizes the first conductive member.

The heat sink includes a first end adjacent to the first chip package and a second end adjacent to the module substrate. The first end and the second end are: The semiconductor module according to claim 4 , wherein the semiconductor modules are coupled to each other by a crimping clip.

A first end adjacent to the first chip package and a second end adjacent to the module substrate form a pocket for the first chip package and the first conductive member. The semiconductor module according to claim 6 .

A first chip package array including the first chip package;
A first conductive member array including the first conductive member interposed between a chip package of the first chip package array and the module substrate;
A second chip package array including a plurality of second chip packages;
And a second conductive member array interposed between the chip package of the second chip package array and the chip package of the first chip package array, wherein the protector includes the first conductive member. The conductive member of the member array, the chip package of the first chip package array, and the module substrate are pressurized, and the first conductive member array and the second conductive member array are pressurized. The semiconductor module according to claim 1 .

A first chip package array including the first chip package;
A first conductive member array including the first conductive member interposed between a chip package of the first chip package array and the module substrate;
A second chip package array including a plurality of second chip packages;
A second conductive member array including a second conductive member interposed between the chip package of the second chip package array and the substrate module;
The protector pressurizes the conductive member of the first conductive member array, the chip package of the first chip package array, and the module substrate, and the first conductive member array and the second conductive member are pressed. 2. The semiconductor module according to claim 1 , wherein the member array is pressurized.

The protector serves as a plurality of heat sinks for the first chip package array and the second chip package array, and includes the first conductive member array, the first chip package array, and the second chip package array. 9. The semiconductor module according to claim 8 , further comprising a plurality of U-shaped clips that pressurize the chip package array, the second conductive member array, the plurality of heat sinks, and the module substrate.

The protector serves as a plurality of heat sinks for the first chip package array and the first chip package array, and the protector includes the first conductive member array and the first chip package array. The semiconductor module according to claim 9 , further comprising: a plurality of U-shaped clips that pressurize the second chip package array, the second conductive member array, the plurality of heat sinks, and the module substrate. .

A third chip package array including a plurality of third chip packages;
A third conductive member array including a third conductive member interposed between the chip package of the first chip package array and the chip package of the third chip package array;
A fourth chip package array including a plurality of fourth chip packages;
A fourth conductive member array including a fourth conductive member interposed between the chip package of the second chip package array and the chip package of the fourth chip package array;
The protector pressurizes the first conductive member array, the second conductive member array, the third conductive member array, and the fourth conductive member array, and the first chip package array. A plurality of heat sinks for the second chip package array, the third chip package array, and the fourth chip package array, and the first conductive member array and the first chip package. Array, second chip package array, second conductive member array, third chip package array, third conductive member array, fourth chip package array, fourth conductive The apparatus further comprises a plurality of U-shaped clips that pressurize the member array, the plurality of heat sinks, and the module substrate. The semiconductor module according to 9.

Providing a module substrate having one or more active surfaces;
Positioning a conductive member on the one or more active surfaces;
Mounting a chip package on the conductive member;
Applying a pressure to the module substrate, the conductive member, and the chip package.