JP2006147628A - Treatment method of substrate, inspection method of substrate, control program and computer storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily distinguish a defect which exists in a substrate beforehand such as a ground defect, etc., and a defect generated in arbitrary treatment such as photolithography, etc. <P>SOLUTION: Inspection before treatment in a step S101 and inspection after development in a step S105 are performed in a defect inspection unit (INS). Information about a detected defect is saved in a computer. In a step S106, the defected detected by the inspection before the treatment is compared with the defect detected by the inspection after the development, and analysis treatment is performed. In this analysis treatment, the defect of the inspection before the treatment of the step S101 is deleted from the defect of the inspection after the development of the step S105 based on the defect information such as the position, the size, the shape, the number, etc. of the defect. Further, the defect generated in the photolithography is extracted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a substrate processing method, a substrate inspection method, a control program, and a computer storage medium. Specifically, for example, a substrate processing method, a substrate inspection method, a control program, and the like for performing processing such as photolithography on a substrate such as a semiconductor wafer It relates to computer storage media.

  In the manufacture of semiconductor devices, a photolithography technique for forming a desired resist pattern on a substrate by applying a resist solution to a substrate such as a semiconductor wafer, exposing the resist film using a photomask, and further developing the resist film. Is used. In general, a resist coating / development processing system is used to perform a series of photolithography processes. And this resist coating / development processing system has been proposed that includes an inspection / measurement unit for inspecting / measuring the state of a substrate (for example, Patent Document 1).

  Conventionally, inspection / measurement of defects and the like in the inspection / measurement unit is called ADI (post-development pattern inspection), and inspects a substrate after development processing using a macro inspection apparatus. Based on the number of defects and the defect distribution (position) output as the ADI inspection results, the shipping decision to the next process has been made.

However, since the photoresist transmits the inspection light, the inspection result includes the base defects of the substrate that occurred before the photolithography process. Therefore, if there are many base defects, only the defects generated in the photolithography process are included. The work to extract was necessary. In this work, it is necessary to grasp the process where the defect occurred and to judge the importance and influence of the defect. There was a problem that the contents were likely to vary.
JP 2003-209154 A (FIG. 1 and the like)

  The present invention has been made in view of the above circumstances, and it is easy to distinguish between defects existing in the substrate in advance such as base defects and defects generated in an arbitrary process such as photolithography. Objective.

In order to solve the above-described problem, according to the first aspect of the present invention, before processing a substrate, a pre-inspection step of inspecting the substrate to detect defects,
A post-inspection step of inspecting the substrate and detecting defects after processing the substrate;
A substrate processing method comprising:
A substrate processing method characterized in that only defects in the processing of the substrate are extracted by comparing the defects detected in the pre-inspection step with the defects detected in the post-inspection step. Is provided.

  In the substrate processing method according to the first aspect, it is preferable to compare and check the defect detected in the pre-inspection step and the defect detected in the post-inspection step by analyzing the imaging of the substrate. Further, the processing of the substrate is preferably photolithography, or resist coating processing, exposure processing, or development processing in photolithography.

Further, according to the second aspect of the present invention, a pre-inspection step of inspecting the substrate to detect a defect,
A resist coating step of forming a resist film by coating a resist solution on the substrate after the pre-inspection step;
An exposure step of transferring a mask pattern to the resist film by exposure using a photomask;
A development step of forming a resist pattern on the substrate based on the transferred mask pattern;
After the development step, a post-inspection step for detecting defects by inspecting the substrate;
Including
Provided is a substrate processing method characterized in that a dummy process different from a process for a normal substrate in which a serious defect is not detected is performed in a subsequent process on a substrate in which a serious defect is detected in the previous inspection process. Is done.

The substrate processing method according to the second aspect further includes a pre-exposure inspection step of detecting defects by inspecting the substrate after the resist coating step,
In a subsequent process, it is preferable to perform a dummy process different from a process for a normal substrate in which no serious defect is detected, on the substrate in which a serious defect is detected in the pre-exposure inspection process.

Further, it further includes a pre-development inspection step of detecting defects by inspecting the substrate after the exposure step,
It is preferable to perform a dummy process different from a process for a normal substrate in which a serious defect is not detected in a subsequent process on a substrate in which a serious defect is detected in the pre-development inspection process.

  Further, only the defect in the photolithography process may be extracted by comparing the defect detected in the pre-inspection process with the defect detected in the post-inspection process.

Further, as a dummy process corresponding to the resist coating process, it is preferable to perform a dummy coating process that does not apply a resist solution to the substrate, and as a dummy process corresponding to the exposure process, a dummy that does not irradiate the substrate with light. It is preferable to perform an exposure process, and as a dummy process corresponding to the development process, it is preferable to perform a dummy development process in which a developer is not supplied to the substrate.
Furthermore, it is preferable to include a heat treatment step of heating the substrate, and as the dummy treatment corresponding to the heat treatment step, a dummy heat treatment is performed in which the substrate is waited at a standby position and heating is not performed.

According to a third aspect of the present invention, a pre-inspection step of inspecting the substrate and detecting defects before processing the substrate;
A post-inspection step of inspecting the substrate and detecting defects after processing the substrate;
Including
A substrate inspection method, wherein only defects in the processing of the substrate are extracted by comparing the defects detected in the pre-inspection step with the defects detected in the post-inspection step. Is provided.

In the substrate inspection method according to the third aspect, it is preferable to compare and check the defect detected in the previous inspection step and the defect detected in the subsequent inspection step by analyzing the imaging of the substrate.
Moreover, it is preferable that the processing of the substrate is photolithography, or resist coating processing, exposure processing, or development processing in photolithography.

  According to a fourth aspect of the present invention, there is provided a control that operates on a computer and controls the substrate processing apparatus so that the substrate processing method according to the first or second aspect is performed at the time of execution. A program is provided.

According to a fifth aspect of the present invention, there is provided a computer storage medium storing a control program that operates on a computer,
A computer storage medium is provided, wherein the control program controls a substrate processing apparatus so that the substrate processing method according to the first or second aspect is performed at the time of execution.

  According to the present invention, substrate defects such as semiconductor wafers can be excluded, and only defects generated in the photolithography process can be automatically grasped. Therefore, even if the substrate has many substrate defects, shipping judgment can be made in the photolithography process. It can be done quickly and accurately. In addition, since anyone can make an accurate determination without depending on the experience of the operator, a highly reliable semiconductor product can be provided without any variation in inspection contents.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view of a resist coating / development processing system 1 capable of performing the substrate processing method of the present invention, FIG. 2 is a schematic front view thereof, and FIG. 3 is a schematic rear view thereof. 1 shows a configuration in which the resist coating / development processing system 1 and the exposure apparatus 15 are combined, and a control station 50 is shown.

  The resist coating / development processing system 1 includes a cassette station 11 as a transfer station, a processing station 13 having a plurality of processing units, and a semiconductor wafer (hereinafter simply referred to as “wafer”) between the cassette station 11 and the processing station 13. The wafer W is transferred between the inspection station 12 that performs the transfer of W and inspects the wafer W processed at the processing station 13 and the exposure apparatus 15 provided adjacent to the processing station 13. Interface station 14 and a control station 50 for controlling each of these components.

  In the cassette station 11, a wafer cassette (CR) containing a plurality of (for example, 25) wafers W is loaded and unloaded. On the cassette mounting table 21, a plurality (five in FIG. 1) of positioning protrusions 21a for mounting a wafer cassette (CR) are provided in one row along the X direction. The wafer cassette (CR) is placed with the wafer loading / unloading port facing the inspection station 12 side.

  The cassette station 11 includes a wafer transfer mechanism 22 having a wafer transfer pick 22a. This wafer transfer pick 22a can selectively access any one of the wafer cassettes (CR), and can also access a transition unit (TRS-I) provided in the inspection processing station 12 described later. ing.

  In the inspection station 12, an inspection module 31 for inspecting the processing state of the wafer W when the resist coating / development processing system 1 is used and a first main transfer unit A1 are arranged. The first main transfer unit A1 includes three arms that hold the wafer W. These arms rotate integrally around the Z axis, move up and down in the Z axis direction, and separately in the horizontal direction ( (In the XY plane) and can be expanded and contracted.

  The inspection module 31 uses a line width measuring unit (ODP; Optical Digital Profilometry) that measures the line width of the developing line and a macro inspection device (not shown) to scratch the wafer substrate and scratch the resist film surface (scratch detection). A defect inspection unit (INS) for inspecting foreign matters (comet detection), development unevenness, development defects after development processing, etc., a line width measuring unit (ODP), and a defect inspection unit (INS) A computer (PC) that controls and stores and analyzes information obtained in each of these inspection units is provided.

  The inspection / measurement in the defect inspection unit (INS) or the line width measurement unit (ODP) is performed, for example, by observing the surface of the wafer W with a CCD camera and analyzing the image with a computer (PC). As the structure of the defect inspection unit (INS) and the line width measurement unit (ODP), a stage for mounting the wafer W and a CCD camera are provided in the housing. (1) The stage is freely rotatable. One that is movable in the X / Y / Z direction; (2) the stage is fixed; the CCD camera is movable in the X / Y / Z direction and is rotatable in the XY plane; (3) The stage is movable in the X / Y / Z directions and is rotatable in the XY plane, and the CCD camera is fixed.

  The measurement by the line width measurement unit (ODP) can be performed on, for example, all the wafers W or measurement wafers W extracted every 2 to 14 sheets. Further, the inspection by the defect inspection unit (INS) can be performed at a ratio of, for example, all wafers W or one for every two wafers.

  The processing station 13 includes a third processing unit group G3, a fourth processing unit group G4, and a fifth processing unit group G5 in order from the inspection station 12 side on the back side of the system (upper side in FIG. 1). A second main transport unit A2 is provided between the third processing unit group G3 and the fourth processing unit group G4, and a third main transport unit is provided between the fourth processing unit group G4 and the fifth processing unit group G5. A3 is provided. Further, a first processing unit group G1 and a second processing unit group G2 are provided in order from the inspection station 12 side on the front side of the system (lower side in FIG. 1).

  In the third processing unit group G3, a high-temperature heat treatment unit (BAKE) that heats the wafer W, a high-precision temperature control unit (CPL-G3) that controls the temperature of the wafer W with high accuracy, and a temperature control unit (TCP) The transition units (TRS-G3) that serve as a transfer unit for the wafer W between the first main transfer unit A1 and the second main transfer unit A2 are stacked in, for example, 10 stages.

  In the fourth processing unit group G4, for example, a pre-bake unit (PAB) that heat-treats the wafer W after resist application, a post-bake unit (POST) that heat-treats the wafer W after development, and a high-precision temperature control unit (CPL-G4), transition units (TRS-G4) serving as a transfer part of the wafer W between the second main transfer part A2 and the third main transfer part A3 are stacked in, for example, 10 stages. In the fifth processing unit group G5, for example, a post-exposure bake unit (PEB) that heat-treats the wafer W after exposure and before development, a high-precision temperature control unit (CPL-G5), the third main transport unit A3, and the first Transition units (TRS-G5) serving as a transfer part of the wafer W with the wafer transfer body 19 are stacked, for example, in 10 stages.

  A sixth processing unit group G6 having an adhesion unit (AD) and a heating unit (HP) for heating the wafer W is provided on the back side of the second main transfer unit A2. Further, on the back surface side of the third main transfer portion A3, there are provided a peripheral exposure device (WEE) for selectively exposing the edge portion of the wafer W and a film thickness measuring device (FTI) for measuring the resist film thickness. Seven processing unit groups G7 are provided.

  In the first processing unit group G1, three resist coating units (COT) for forming a resist film and a bottom coating unit (BARC) for forming an antireflection film are stacked in a total of five stages. In FIG. 1, “CP” indicates a coater cup, and “SP” indicates a spin chuck. In the second processing unit group G2, the developing units (DEV) are stacked in five stages.

  A second main wafer transfer device 17 is provided in the second main transfer portion A2. The second main wafer transfer device 17 includes three arms that hold the wafer W. These arms rotate integrally around the Z axis, move up and down in the Z axis direction, and separately in the horizontal direction. It can be expanded and contracted (in the XY plane). Thus, the second main wafer transfer device 17 can selectively access each of the first processing unit group G1, the third processing unit group G3, the fourth processing unit group G4, and the sixth processing unit group G6. The third main wafer transfer unit A3 is provided with a third main wafer transfer device 18 having the same structure as that of the second main wafer transfer device 17, and the third main wafer transfer device 18 includes the second processing unit group G2. The fourth processing unit group G4, the fifth processing unit group G5, and the seventh processing unit group G7 can be selectively accessed.

  Liquid temperatures for supplying processing liquid to the first and second processing unit groups G1 and G2 between the first processing unit group G1 and the inspection station 12 and between the second processing unit group G2 and the interface station 14, respectively. Ducts 29 and 30 are provided for supplying clean air from the conditioning pumps 25 and 26 and the air conditioner outside the resist coating / development processing system 1 to the inside of each processing unit group G1 to G5.

  Chemical units (CHM) 27 and 28 for supplying chemicals to the first and second processing unit groups G1 and G2 are provided at the lowermost stages of the first and second processing unit groups G1 and G2, respectively.

  The panel on the back side of the processing station 13 and the first processing unit group G1 to the seventh processing unit group G7 can be removed for maintenance.

  The interface station 14 includes a first interface station 14a on the processing station 13 side and a second interface station 14b on the exposure apparatus 15 side. A first wafer transfer body 19 is disposed at the first interface station 14a so as to face the opening of the fifth processing unit group G5, and a second wafer transfer body 20 movable in the X direction is disposed at the second interface station 14b. Is arranged.

  On the back side of the first wafer transfer body 19, the peripheral exposure apparatus (WEE), the in-buffer cassette (INBR) for temporarily storing the wafer W transferred to the exposure apparatus 15, and the exposure apparatus 15 are unloaded in order from the top. An eighth processing unit group G8 is provided in which out buffer cassettes (OUTBR) for temporarily storing the wafers W are stacked. On the front side of the first wafer transfer body 19, there is a ninth processing unit group G9 in which a transition unit (TRS-G9) and two high-precision temperature control units (CPL-G9) are stacked in order from the top. Is provided.

  The first wafer transfer body 19 has a fork 19a for wafer transfer. The fork 19a accesses each unit of the fifth processing unit group G5, the eighth processing unit group G8, and the ninth processing unit group G9, and transfers the wafer W between the units. The second wafer transfer body 20 has a wafer transfer fork 20a. The fork 20a is accessible to each unit of the ninth processing unit group G9 and the in-stage 15a and out-stage 15b of the exposure apparatus 15, and transfers the wafer W between these units.

  Each component of the resist coating / development processing system 1 is controlled by the control station 50. The control station 50 includes a process controller 51 including a CPU, a user interface 52, and a storage unit 53. The process controller 51 includes a keyboard on which a process manager manages command input to manage the resist coating / development processing system 1, a display that visualizes and displays the operating status of the resist coating / development processing system 1, and the like. A user interface 52 is connected.

  Further, the process controller 51 has a recipe in which a control program (software) for realizing various processes executed by the resist coating / development processing system 1 under the control of the process controller 51 and processing condition data are recorded. A stored storage unit 53 is connected.

  If necessary, an arbitrary recipe is called from the storage unit 53 by an instruction from the user interface 52 and is executed by the process controller 51, so that the resist coating / development processing system 1 is controlled under the control of the process controller 51. The desired processing is performed. In addition, recipes such as the control program and processing condition data may be stored in a computer-readable storage medium such as a CD-ROM, a hard disk, a flexible disk, a non-volatile memory, or the like. For example, it is possible to transmit the data from time to time via a dedicated line and use it online.

In the resist coating / development processing system 1 configured as described above, a single wafer W taken out from the wafer cassette (CR) is transferred to, for example, the transition unit (TRS-I) of the inspection station 12 to detect defects. After the pre-processing inspection as the pre-inspection process is performed in the inspection unit (INS), the inspection unit (INS) is transported to the transition unit (TRS-G3) of the processing station 13, and the temperature control and adhesion unit in the temperature control unit (TCP) Adhesion treatment in (AD), formation of antireflection film in bottom coating unit (BARC), heat treatment in heating unit (HP), baking treatment in high temperature heat treatment unit (BAKE), high precision temperature control unit (CPL- Temperature control in G3), resist solution in resist coating unit (COT) Coating process, prebaking treatment at the pre-baking unit (PAB), through a peripheral exposure process in the peripheral exposure device (WEE), it is conveyed to the exposure apparatus 15. Then, the wafer W is exposed to light in the exposure apparatus 15, transferred to the transition unit (TRS-G9), post-exposure bake processing in the post-exposure bake unit (PEB), development processing in the development unit (DEV), post-processing. After a post-bake process in the bake unit (POST), it is carried into the inspection station 12 again, and after a post-processing inspection as a post-inspection process in the defect inspection unit (INS), it is returned to the wafer cassette (CR). .
Although only one defect inspection unit (INS) is shown in FIGS. 1 to 3 above, for example, when the wafer W is inspected for each process such as a resist coating process, an exposure process, and a development process. Can also be provided with a defect inspection unit (INS) in the vicinity of each processing unit.

<First Embodiment>
FIG. 4 is a flowchart showing a process example of the substrate processing method according to the first embodiment of the present invention. The substrate processing method according to the present embodiment performs a photolithography process on a wafer using the resist coating / development processing system 1, and FIG. 4 shows only main processes.
First, in step S101, a pre-processing inspection as a pre-inspection process is performed on the wafer W. The pre-processing inspection is performed in a defect inspection unit (INS) of the inspection station 12. Information on defects detected in the pre-processing inspection, for example, the position, size, shape, number, etc. of defects on the wafer W is stored in a computer (PC).

In step S102, a resist coating process is performed on the wafer W in the resist coating unit (COT). Subsequently, an exposure process in the exposure device 15 is performed in step S103, and a developing process in the developing unit (DEV) is performed in step S104.
After the development process, a post-development inspection as a post-inspection step is performed in step S105. The post-development inspection is performed in the defect inspection unit (INS) of the inspection station 12 in the same manner as the pre-processing inspection in step S101, and information on the detected defects is stored in a computer (PC).

  In subsequent step S106, the defect detected in the pre-processing inspection and the defect detected in the post-development inspection are collated by a computer (PC), and analysis processing is performed. In this analysis process, based on defect information such as the position, size, shape, and number of defects, the defects in the pre-processing inspection in step S101 are excluded from the defects in the post-development inspection in step S105.

FIG. 5 schematically shows the state of defects appearing on the wafer image W ′ taken in the defect inspection unit (INS). FIG. 5A shows the macro defect detected in the pre-processing inspection (step S101). On the other hand, FIG. 5B shows macro defects detected in the post-development inspection (step S105). The macro defects detected in the post-development inspection include the macro defects that originally existed on the base of the wafer W and the macro defects generated in the photolithography process.
Accordingly, the result of FIG. 5B is compared with the result of FIG. 5A, and the macro defect originally present on the wafer W is subtracted from the macro defect detected by the post-development inspection. As shown in FIG. 3C, only macro defects generated in the photolithography process can be extracted. Whether the result of FIG. 5B and the result of FIG. 5A are the same defect by image analysis based on, for example, the coordinates (position) and size (X direction, Y direction) of the defect. This can be done by identifying whether or not. The operation of extracting defects generated in the photolithography process can be automatically performed on, for example, a computer (PC).

  By performing the analysis process in this way, it is possible to extract defects generated in the photoresist process from steps S102 to S104. Therefore, since only the defects generated in the photolithography process can be automatically grasped except for the base defects of the wafer W, the shipping judgment in the photolithography process can be performed quickly and accurately even when the wafer W has many base defects. be able to. In addition, since anyone can make an accurate determination without depending on the experience of the operator, a highly reliable semiconductor product can be provided without any variation in inspection contents.

  In addition, in an apparatus in which a defect inspection unit (INS) is incorporated in-line, such as the resist coating / development processing system 1 shown in FIG. Can be greatly shortened, and improvement in productivity can be expected. Further, in the method of performing inspection by connecting a defect inspection apparatus to the outside, it is necessary to once carry out the wafer W from the resist coating / development processing system for inspection, but the defect inspection unit (INS) must be inlined. Therefore, there is no risk of new particle adhesion due to carrying out to the outside, and there is no need to wait for a space as in the case of using an external defect inspection apparatus, so that an improvement in productivity can be expected.

Second Embodiment
FIG. 6 is a flowchart showing an example of a processing routine in the substrate processing method according to the second embodiment of the present invention. In the present embodiment, a normal processing flow (step S201 to step S211) for performing a photolithography process on a single wafer W using the resist coating / development processing system 1 and a serious defect is detected. A dummy process flow (steps S221 to S226) for performing the dummy process is provided.

First, in step S201, a pre-processing inspection as a pre-inspection process is performed on the wafer W and analyzed. The pre-processing inspection is performed in a defect inspection unit (INS) of the inspection station 12.
In step S202, analysis is performed based on the information regarding the defects detected in the pre-processing inspection, and it is determined whether or not these defects are serious defects. In the present invention, a “serious defect” means a defect that cannot be normally commercialized as a semiconductor product even if processing thereafter is continued. Judgment of whether a defect is serious or not is based on information on the background defects of the wafer W, for example, a master that classifies from minor defects to serious defects by using the position, size, shape, number, etc. of defects on the wafer W as an index. This can be done by preparing a table in advance and collating the master table with the inspection result obtained in step S201 on a computer (PC).

If it is determined in step S202 that the defect is not a serious defect (No), the wafer W is unloaded from the defect inspection unit (INS). For example, the temperature adjustment in the temperature adjustment unit (TCP), the adhesion unit (AD) ), Heat treatment in the heating unit (HP), baking in the high temperature heat treatment unit (BAKE), high precision temperature control unit (CPL-G ₃₎ ) Is then transferred to the resist coating unit (COT), a resist coating process is performed in step S203, and a pre-baking process in the pre-baking unit (PAB) is further performed.

  Thereafter, the wafer W is transferred again to the defect inspection unit (INS), and a pre-exposure inspection is performed in step S204. A plurality of defect inspection units (INS) may be provided, and the pre-exposure inspection in step S204 may be performed using a defect inspection unit (INS) different from the defect inspection unit (INS) used in step S201.

  In step S205, an analysis is performed based on information on defects detected in the pre-exposure inspection, and it is determined whether or not these defects are serious defects. Note that whether or not the background defect is serious has already been determined in step S202, and therefore, it is possible to determine mainly the defect that has occurred in the resist coating process in step S203. Similar to the case of step S202, this determination can be performed using a master table that classifies, for example, from minor defects that can occur in resist coating processing to serious defects.

  If it is determined in step S205 that the defect is not a serious defect (No), the wafer W is unloaded from the defect inspection unit (INS) and subjected to, for example, a peripheral exposure process in the peripheral exposure apparatus (WEE), and then the exposure apparatus 15 And exposure processing is performed in step S206. Further, post-exposure bake processing in a post-exposure bake unit (PEB) is performed on the wafer W after the exposure processing.

  Next, the wafer W is transferred again to the defect inspection unit (INS), and a pre-development inspection is performed in step S207. Note that the pre-development inspection in step S207 may be performed using a defect inspection unit (INS) different from the defect inspection unit (INS) used in step S201 or step S204.

  Based on the information about defects detected in the pre-development inspection (step S207), analysis is performed in step S208 to determine whether or not these defects are serious defects. Here, it is possible to make a judgment mainly on the defects generated in the exposure processing in step S206. This determination can be performed using, for example, a master table in which defects generated in the exposure process or obvious defects are classified from minor to serious.

  If it is determined in step S208 that the defect is not a serious defect (No), the wafer W is unloaded from the defect inspection unit (INS), transferred to the developing unit (DEV), and developed in step S209. The wafer W after the development processing is further subjected to a post baking process in a post baking unit (POST).

Next, the wafer W is again transferred to the defect inspection unit (INS), where post-development inspection is performed in step S210, and then returned to the wafer cassette (CR).
In step S211, the defect detected in the pre-application inspection (step S201) is compared with the defect detected in the post-development inspection (step S210), and analysis processing is performed. In this analysis processing, based on defect information such as the position, size, shape, and number of defects, the defects in the pre-application inspection in step S201 are deleted from the defects in the post-development inspection in step S210. Thereby, the defect which arose in the photolithography process can be grasped | ascertained (refer FIG. 5 regarding 1st Embodiment). Note that it is also possible to extract only serious defects that have occurred in the development processing in step S209.

The wafer W that is determined to have a serious defect (Yes) in step S202 of FIG. 6 with respect to the normal wafer W processing flow described above is based on a dummy coating process (based on a dummy processing flow different from the normal processing flow). Step S221), dummy exposure processing (step S223), and dummy development processing (step S225) are performed.
Further, dummy exposure processing (step S223) and dummy development processing (step S225) are performed on the wafer W that is determined to have a serious defect (Yes) for the first time in step S205.
Further, dummy development processing (step S225) is performed on the wafer W that is determined to have a serious defect (Yes) for the first time in step S208.

The dummy processing flow includes a dummy inspection process in which no image is taken by the defect inspection unit (INS) (steps S222, S224, and S226). Although it is not necessary to perform the inspection again on the wafer W in which a serious defect has already been found, the dummy inspection is performed from the viewpoint of maintaining the wafer processing sequence in relation to the normal wafer W. The dummy inspection can be performed, for example, by causing a wafer W having a serious defect to wait in the transition unit (TRS-I).
Details of each dummy process in the dummy process flow are as follows.

  If it is determined in step S202 that the defect is serious (Yes), the wafer W is subjected to a dummy coating process in step S221 based on the dummy process flow. In this case, the wafer W having a serious defect is transferred to the resist coating unit (COT) in the same manner as the normal wafer W, but no resist solution is applied here. For this reason, wasted wasteful resist solution is prevented.

  If a serious defect is found in step S202, the wafer W is caused to wait, for example, in a transition unit (TRS-G3), so that the heating process in the heating unit (HP) and the baking process in the high temperature heat treatment unit (BAKE) are performed. May not be performed. In this way, waste of energy and time required for heating can be avoided.

Furthermore, the pre-baking process in the pre-baking unit (PAB) can be avoided by causing the wafer W that has been subjected to the dummy coating process in step S221 to wait, for example, in the transition unit (TRS-G4). The waste of energy and time required can be prevented.
Note that after the dummy coating process in step S221, a dummy inspection is performed in step S222.

  If it is determined in step S205 that there is a serious defect, the wafer W is subjected to dummy exposure processing in step S223 based on the dummy processing flow. The dummy exposure process is performed by the exposure apparatus 15, but light irradiation by excimer laser light or the like is not performed. As for the exposure process, light irradiation may be performed on a wafer W having a serious defect in the same manner as a normal wafer W. In addition, when the wafer W having a serious defect is caused to wait on the transition unit (TRS-G9), the loading / unloading of the exposure apparatus 15 itself can be omitted.

In addition, the wafer W after the dummy exposure process may be prevented from performing the post-exposure bake process in the post-exposure bake unit (PEB), for example, by making the transition unit (TRS-G5) wait. In this way, waste of energy and time required for heating can be avoided.
Note that after the dummy exposure process in step S223, a dummy inspection is performed in step S224.

  If it is determined in step S208 that the defect is serious (Yes), dummy development processing is performed in step S225 based on the dummy processing flow. In this case, the wafer W having a serious defect is transported to the development unit (DEV) in the same manner as the normal wafer W, but the developer is not supplied in the dummy development process. For this reason, wasted waste developer is prevented.

Further, the post-baking process in the post-bake unit (POST) may be not performed by waiting the wafer W after the dummy development process in, for example, the transition unit (TRS-G4). In this way, waste of energy and time required for heating can be avoided.
After the dummy development process in step S225, a dummy inspection is performed in step S226, and the wafer is returned to the wafer cassette (CR). The wafer W having a serious defect is discarded or reclaimed.

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to the said embodiment. In the above-described embodiment, the case where the inspection station 12 is provided between the cassette station 11 and the processing station 13 has been described. However, the inspection station 12 may be provided at another position, and the inspection station 12 may be provided. It can also be provided at a plurality of locations.

  Further, the inspection / measurement of the wafer W in the inspection station 12 is not limited to the inspection / measurement by the defect inspection unit (INS) and the line width measurement unit (ODP). Defect inspection equipment that inspects the positional deviation of the pattern caused by exposure, FTI, particle inspection equipment that detects the number of particles attached to the wafer, and the solvent of the resist solution that has jumped out of the wafer surface adheres to the wafer again. A splash back inspection apparatus for inspecting whether or not a wafer is present, a common defect detection apparatus for detecting a common defect appearing in the same shape at the same location on the wafer surface, a scum detection apparatus for detecting a residual resist remaining on the wafer after development processing, Other clamp ring inspection equipment, NO RESIST inspection equipment, NO DEVLOP inspection It is also possible to incorporate an inspection device or the like.

  In the above embodiment, a semiconductor wafer is taken up as a substrate to be processed. However, the substrate may be a glass substrate used for a liquid crystal display (LCD) or a reticle substrate used for a photomask. Further, although resist coating / development processing has been taken up regarding substrate processing, the present invention can also be applied to a substrate processing apparatus that performs each processing such as cleaning processing, interlayer insulating film coating processing, and etching processing. In this case, the inspection station is provided with an inspection / measurement apparatus corresponding to the processing of the substrate.

1 is a schematic plan view of a resist coating / development processing system used in the practice of the present invention. FIG. 2 is a schematic front view of the resist coating / development processing system shown in FIG. 1. FIG. 2 is a schematic rear view of the resist coating / development processing system shown in FIG. 1. The flowchart which shows the process example of the substrate processing method of 1st Embodiment of this invention. The drawing which shows typically the defect of the board | substrate before and behind a photolithography process. The flowchart which shows the process example of the substrate processing method of 2nd Embodiment of this invention.

Explanation of symbols

1; resist coating / development processing system 11; cassette station 12; inspection station 13; processing station 14; interface station 15; exposure device 16; first main wafer transfer device 17; Wafer transport mechanism 31; inspection module INS; defect inspection unit ODP; line width measurement units G1 to G9; first processing unit group to ninth processing unit group W ... semiconductor wafer

Claims (18)

A pre-inspection step for inspecting the substrate and detecting defects before processing the substrate;
A post-inspection step of inspecting the substrate and detecting defects after processing the substrate;
A substrate processing method comprising:
A substrate processing method characterized in that only defects in the processing of the substrate are extracted by comparing the defects detected in the pre-inspection step with the defects detected in the post-inspection step. .   The substrate processing method according to claim 1, wherein the defect detected in the pre-inspection step and the defect detected in the post-inspection step are compared and collated by analyzing imaging of the substrate.   The substrate processing method according to claim 1, wherein the processing of the substrate is photolithography.   The substrate processing method according to claim 1, wherein the substrate processing is resist coating processing, exposure processing, or development processing in photolithography. A pre-inspection process for detecting defects by inspecting the substrate;
A resist coating step of forming a resist film by coating a resist solution on the substrate after the pre-inspection step;
An exposure step of transferring a mask pattern to the resist film by exposure using a photomask;
A development step of forming a resist pattern on the substrate based on the transferred mask pattern;
After the development step, a post-inspection step for detecting defects by inspecting the substrate;
Including
A substrate processing method, wherein a dummy process different from a process for a normal substrate in which no serious defect is detected is performed in a subsequent process on a substrate in which a serious defect is detected in the previous inspection process. Further including a pre-exposure inspection step of detecting defects by inspecting the substrate after the resist coating step;
6. The substrate in which a serious defect is detected in the pre-exposure inspection step is subjected to a dummy process different from a process for a normal substrate in which a serious defect is not detected in the subsequent steps. The substrate processing method as described. Further comprising a pre-development inspection step of detecting defects by inspecting the substrate after the exposure step;
6. The substrate in which a serious defect is detected in the pre-development inspection step is subjected to a dummy process different from a process for a normal substrate in which a serious defect is not detected in a subsequent process. The substrate processing method according to claim 6.   The defect detected in the pre-inspection process and the defect detected in the post-inspection process are compared to extract only the defect in the photolithography process. The substrate processing method according to claim 7.   9. The substrate processing method according to claim 5, wherein a dummy coating process that does not apply a resist solution to a substrate is performed as a dummy process corresponding to the resist coating process. 10.   9. The substrate processing method according to claim 5, wherein a dummy exposure process that does not irradiate the substrate with light is performed as the dummy process corresponding to the exposure step.   9. The substrate processing method according to claim 5, wherein a dummy developing process in which a developing solution is not supplied to the substrate is performed as a dummy process corresponding to the developing step. 10.   12. The method according to claim 5, further comprising a heat treatment step for heating the substrate, wherein the dummy treatment corresponding to the heat treatment step is performed by performing a dummy heat treatment in which the substrate is waited at a standby position and heating is not performed. The substrate processing method according to any one of the above. A pre-inspection step for inspecting the substrate and detecting defects before processing the substrate;
A post-inspection step of inspecting the substrate and detecting defects after processing the substrate;
Including
A substrate inspection method, wherein only defects in the processing of the substrate are extracted by comparing the defects detected in the pre-inspection step with the defects detected in the post-inspection step. .   The substrate inspection method according to claim 13, wherein the defect detected in the pre-inspection step and the defect detected in the post-inspection step are compared and collated by analyzing imaging of the substrate.   The substrate inspection method according to claim 13, wherein the processing of the substrate is photolithography.   15. The substrate inspection method according to claim 13, wherein the processing of the substrate is resist coating processing, exposure processing, or development processing in photolithography.   A control program that operates on a computer and controls the substrate processing apparatus so that the substrate processing method according to any one of claims 1 to 12 is performed at the time of execution. A computer storage medium storing a control program that runs on a computer,
A computer storage, wherein the control program controls a substrate processing apparatus so that the substrate processing method according to any one of claims 1 to 12 is performed at the time of execution. Medium.

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