JP2006142447A - Functional element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce cost by miniaturizing a chip size and improving defect rate with simple process. <P>SOLUTION: Many pieces of chip elements 3 and wiring patterns 7 are formed on a wafer 30, and the wafer is diced after a cap substrate 4 is mounted opposed to each chip element through a junction seal layer 5 having a predetermined thickness. A chip element storage space part 6 sealing the chip element 3 is constituted between a main surface 2a of the chip substrate 2 and a first main surface 4a of the cap substrate 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a functional element body having a movable part, such as a micro electro mechanical system (MEMS), a piezoelectric thin film resonance element (FBAR) or a surface acoustic wave filter element (SAW). Device), a functional element body such as a bulk acoustic wave device (BAW), and a manufacturing method thereof.

  In recent years, various mobile electronic devices such as personal computers, mobile phones, video devices, audio devices, and the like have been reduced in size and weight, increased in functionality, increased in functionality, and increased in speed. In mobile electronic devices and the like, a mounting substrate having a wiring layer having a fine wiring pattern formed in multiple layers for high density wiring is used for this purpose, and the mounting substrate is small and multifunctional. A circuit module body in which the integrated circuit component, the electronic component, or various semiconductor device components are mounted by a surface mounting method such as a flip chip mounting method is provided.

  As a circuit module body, for example, a semiconductor device can be chip-sized by directly mounting a so-called bare chip in a non-package state on a mounting substrate from a mounting method through a terminal piece protruding from a resin mold or a ceramic package. The planned mounting method is also adopted. In the circuit module body, connectors such as solder bumps are provided in advance on a large number of element mounting electrodes formed on the mounting board, and the bare chip that is positioned and combined with the mounting board is soldered by reflow soldering or the like. To be implemented.

  The circuit module body enables high-density mounting of electronic components and semiconductor devices by reducing the mounting area and increasing the number of pins by making the mounting area of the mounting substrate approximately the same as the chip size. . In addition, the circuit module body realizes high-speed signal transmission and high frequency by shortening the wiring length with less loss. In a circuit module body, a bare chip mounted on a mounting substrate is sealed with an insulating resin so that insulation and mechanical protection from other mounting components can be achieved.

  By the way, in a function blocking device such as MEMS, FBAR, or SAW having a functional surface provided with a mover or a vibrator, a functional element is surface-mounted on a mounting substrate like the semiconductor device described above, and an insulating resin is used. If the structure sealed with is used, there is a problem that the mover and the vibrator are fixed and cannot operate and cannot function. In a functional element device, if a minute movable part of the functional element body is exposed, the characteristics change due to the temperature change or etching solution applied during the packaging process or the circuit module manufacturing process. May occur.

  Therefore, the functional element device is generally configured by hermetically packaging a chip element formed on a device substrate with a resin cap body, and is mounted on a mounting substrate or the like. In the functional element device, since the outer shape of the packaging is larger than the size of the chip element, it has been difficult to realize a circuit module body with high density mounting or downsizing.

  In circuit module bodies, various mounting methods for forming a hollow portion for mounting a functional element with an appropriate configuration on the inner layer of a package substrate or a mounting substrate have been studied. For example, in Patent Document 1, an insulating resin frame and a connection bump that surround an active surface of a chip element and constitute an adhesive layer are provided, and the chip element is mounted face-down on a mounting substrate with the active surface as an opposing surface. A micro-package structure for (surface mounting) is disclosed. In such a micro package structure, a hollow portion surrounded by an insulating resin frame is formed between the active surface of the chip element and the main surface of the mounting substrate. According to such a micro package structure, a chip element having an active surface with respect to a mounting substrate can be face-down mounted in the same manner as other electronic components and bare chips. Therefore, according to such a micro package structure, the circuit module body is made thinner and the efficiency of the mounting process is improved.

  On the other hand, in a functional element device, a fine movable part provided in a MEMS element or the like is easily affected by the external environment, and electrical characteristics and functional characteristics greatly change due to oxidation or electrostatic charging. Therefore, in the functional element device, a package process and a modularization process in a series of device manufacturing processes are generally performed by a low temperature process. Further, in such a functional element device, the functional element body is held in an airtight state (hermetic sealing state) in a vacuum or reducing atmosphere that suppresses the influence from the various external factors described above, so that a stable operation is performed. Need to be configured.

  Patent Document 2 discloses a circuit board in which a functional element mounted in a hollow portion (cavity) and an external output terminal formed on a surface layer of a mounting board are connected by vias, but the airtightness of the cavity is maintained. . In the circuit board, circuit patterns are formed in multiple layers on an insulating layer containing a glass-ceramic component, and an intermediate layer made of a metal component is provided so as not to be dissolved by the plating solution. In the circuit board, even if the insulating layer is made porous by the plating process for forming the surface wiring layer, the airtight state of the cavity is maintained by the intermediate layer.

  In Patent Document 3, for a device wafer on which a predetermined wiring pattern having a large number of chip elements and input / output electrodes is formed, a large number of joints and vias are formed on the cap wafer and cut one by one. A functional element device is disclosed in which a functional element body is sealed in a hollow portion by performing a process of cutting an element wafer after sealing and electrical connection by mounting the cap body corresponding to each chip element. .

Japanese Patent No. 3514349 JP 2003-282863 A Japanese Patent Laid-Open No. 2002-246489

  By the way, in the micro package disclosed in Patent Document 1 described above, although it is effective in reducing the thickness, the chip is provided with a region for forming connection bumps and a region for forming a frame-shaped insulating resin layer on the chip element. The element itself becomes larger. In a micro package, it is possible to mount a chip element in an area that is almost the same as the outer dimensions of the mounting substrate. However, the increase in size of this chip element greatly contributed to the miniaturization of the entire module. There was a problem of not getting. Also, in the micro package, there is a problem that reliability is lowered due to the influence of moisture and oxidation because the chip element is mounted in an open state.

  On the other hand, in the circuit board disclosed in Patent Document 2, the reliability is improved by mounting the functional element in an airtight state in the cavity of the mounting board. However, since such a circuit board uses a substrate containing a glass-ceramic component, the chip element is damaged during ceramic firing. Further, in the circuit board, there is a problem that the board is expensive and the cost is high because noble metals such as Au, Ag, Pt, and Rh are used in order to maintain the airtightness of the via hole. Furthermore, since the circuit board is provided with a lid for closing the cavity, there is a problem in that the thickness of the circuit board increases as a whole and the size cannot be reduced.

  Since the functional element device disclosed in Patent Document 3 performs packaging of chip elements in the wafer process, handling is improved, damage to minute movable parts and the like is prevented, and yield is greatly improved. . Functional device devices are formed with high precision as a single unit by using a wafer formed of a silicon substrate or glass substrate, but the wafer has low machinability to form via holes, etc., and the multilayered structure integrates matching circuits etc. There is a problem that it is difficult to realize and cost is high. In addition, although it is possible to reduce the size of the functional element device alone, there is a problem that the mounting structure on the mounting board becomes complicated and the circuit module body cannot be thinned and the efficiency of the mounting process cannot be realized. .

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a functional element body capable of reducing the so-called chip size, improving the yield by a simple process, achieving high accuracy and reducing the cost, and a manufacturing method thereof. .

  The functional element body according to the present invention that achieves the above-described object includes a chip substrate, a cap substrate, and a bonding seal layer. In the functional element body, a chip substrate is formed by cutting a wafer, and a chip element and a wiring pattern having predetermined input / output electrodes connected to the chip element are formed on a main surface. In the functional element body, the cap substrate is formed with a first wiring pattern having connection electrodes that are relatively connected to the input / output electrodes on the chip substrate side on the first main surface, and first via the vias on the second main surface. A second wiring pattern having an external connection electrode and interlayer connection with the wiring pattern is formed. In the functional element body, the bonding seal layer is formed on the first main surface of the cap substrate with a predetermined thickness in a frame-like region surrounding the connection electrode.

  In the functional element body, after a large number of chip elements and wiring patterns are formed on the main surface in the wafer state, the cap substrate faces the chip elements on the main surface of the wafer and the first main surface is the mounting surface. It is mounted via a bonding seal layer. In the functional element body, a chip element housing space for sealing the chip elements is formed between the main surface of the wafer and the first main surface of the cap substrate by the bonding seal layer having a predetermined thickness. In the functional element body, cutting is performed one by one by cutting the wafer between the cap substrates to form a chip substrate. In the functional element body, a circuit module body is configured by being mounted on a mounting substrate via an external connection electrode with the chip substrate as a ceiling portion and the second main surface of the cap substrate as a mounting surface.

  Moreover, the manufacturing method of the functional element body concerning this invention which achieves the objective mentioned above has a wafer process, a cap board | substrate manufacturing process, a joining sealing layer formation process, a cap board | substrate mounting process, and a wafer cutting process. In the method of manufacturing a functional element body, a wafer process includes a step of forming a large number of chip elements on a main surface of a chip substrate made of a wafer, and a large number of wirings having predetermined input / output electrodes for each chip element. Forming a pattern and forming a connection bump on each of the input / output electrodes. In the method of manufacturing a functional element body, the cap substrate manufacturing step includes forming a first wiring pattern having connection electrodes that are connected to each input / output electrode on at least a first main surface using an organic insulating substrate as a base material. And a step of forming a second wiring pattern having an external connection electrode on the second main surface, and a step of forming a via penetrating the organic insulating substrate to connect the first wiring pattern and the second wiring pattern to each other. . In the method of manufacturing the functional element body, the bonding seal layer forming step includes a frame layer having a predetermined thickness in a frame region surrounding the connection electrode on the first main surface of the cap substrate. A bonding seal layer to be bonded is formed. In the method of manufacturing the functional element body, the cap substrate mounting step combines the cap substrate with respect to the chip substrate by positioning the first main surface as a mounting surface and positioning the connection electrodes relative to the input / output electrodes on the main surface. The cap substrate is configured between the main surface of the cap substrate and the first main surface of the cap substrate by subjecting the cap substrate to a predetermined curing process on the chip substrate to cure and integrate the bonding seal layer. Sealing each chip element in each chip element storage space. In the method of manufacturing the functional element body, the wafer cutting step cuts the wafer between the cap substrates and divides the wafer into chip substrates to manufacture the functional element body.

  In the method for manufacturing a functional element body, a functional element body in which a chip element is sealed in a chip element storage space formed between the main surface of the chip substrate and the first main surface of the cap substrate is manufactured by a bonding seal layer. . In the method for manufacturing a functional element body, a functional element body mounted on a mounting substrate via an external connection electrode is manufactured with the chip substrate as a ceiling portion and the second main surface of the cap substrate as a mounting surface.

  According to the present invention, a cap substrate is bonded to a chip substrate provided with a high-precision chip element or wiring pattern formed in a wafer state via a bonding seal layer having a predetermined thickness at the outer peripheral portion of the chip element. Thus, a highly airtight chip element storage space is formed and the chip elements are sealed. According to the present invention, downsizing is achieved, so that the mounting density of circuit modules and the like is improved, so that downsizing and high functionality are achieved. According to the present invention, the handling property is improved during the manufacturing process to prevent the chip element from being damaged, and the chip element is sealed in a highly airtight state in the chip element storage space to perform a stable operation. Thus, the yield and reliability can be improved. According to the present invention, the mounting structure for the module substrate or the like is simplified through the cap substrate, and the productivity of the circuit module is improved.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a functional element body 1 and a manufacturing method thereof shown as embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the functional element body 1 includes a chip substrate 2 obtained by cutting a silicon substrate (wafer) 10 used in a semiconductor process, a chip element 3 provided on the main surface 2a of the chip substrate 2, The cap substrate 4 and the bonding seal layer 5 are included. As will be described in detail later, the functional element body 1 includes a chip element storage space 6 between the chip substrate 2 and the cap substrate 4, and the chip element 3 is sealed in the chip element storage space 6. The functional element body 1 is mounted on the module substrate 21 via the cap substrate 4 and constitutes the high-frequency circuit module body 20 mounted on the mobile phone, personal computer, or the like shown in FIG.

  The functional element body 1 forms a so-called bare chip by providing the chip element 3 on the chip substrate 2 and forming the wiring pattern 7 and a large number of input / output electrodes 8. The chip substrate 2 is located at a substantially central portion of the main surface 2a and will not be described in detail. Is configured. A plurality of input / output electrodes 8 are formed on the chip substrate 2 so that the wiring pattern 7 is drawn from the chip mounting electrodes to the outer peripheral side to surround the chip element mounting region.

  On the chip substrate 2, mounting bumps 9 are formed on the input / output electrodes 8 to mount the cap substrate 4 electrically and mechanically, as will be described later. The mounting bumps 9 are formed in a stud shape by, for example, an additive method such as a ball bump forming method using a gold wire, a plating method, or a printing method. Each mounting bump 9 is formed to have a height that is slightly larger than the thickness of the bonding seal layer 5 described later.

  The functional element body 1 is mounted on the chip element mounting area of the chip substrate 2 with the chip element 3 provided with a fine movable portion 3b on the functional surface 3a, although details are omitted. The chip element 3 is composed of a functional chip element such as a SAW element (surface acoustic wave element), a BAW element (bulk elastic wave element), a MEMS (microelectromechanical component), or an FBAR element (piezoelectric thin film resonant element). The chip element 3 is mounted on the chip element mounting region by, for example, a flip chip mounting method, with electrodes whose details are omitted being aligned with opposing input / output electrodes, with the functional surface 3a facing upward.

  In addition, the functional element body 1 may form the chip element 3 directly on the main surface 2a of the chip substrate 2 by thin film technology or the like, and in this case, it is formed together with the wiring pattern 7. The functional element body 1 may be a composite functional chip element in which a plurality of identical or different chip elements 3 are mounted on a chip substrate 2. When the functional element body 1 is mounted on the chip substrate 2 by, for example, a flip chip mounting method, an underfill agent is applied so that the mechanical bonding strength is maintained.

  The cap substrate 4 is an organic insulating substrate 10 excellent in heat resistance, chemical resistance, or processability, such as liquid crystal polymer, glass epoxy, polyimide, polyphenylene ether, bismaletotriazine, polytetrafluoroethylene, or butadiene resin for high frequency. The organic insulating substrate is used as a base material. The cap substrate 4 is substantially the same as the outer dimensions of the chip substrate 3 described above, and the copper foil layers attached to both surfaces of the organic insulating substrate 10 are subjected to predetermined patterning by a photolithographic method or the like to obtain the first A first wiring pattern 11 and a second wiring pattern 12 are formed on the main surface 4a and the second main surface 4b, respectively. In the cap substrate 4, the organic insulating substrate 10 described above is less expensive than a ceramic substrate or a glass substrate and is excellent in workability of the via 13.

  The cap substrate 4 is formed with a plurality of vias 13 in which conduction processing is performed on via holes penetrating the organic insulating substrate 10, and the first wiring pattern 11 and the second wiring pattern 12 are connected to each other through the vias 13. Is done. As will be described later, the cap substrate 4 is mounted on the main surface 2a of the chip substrate 2 with the first main surface 4a as a mounting surface. On the cap substrate 4, a large number of connection electrodes 14 are formed on the first wiring pattern 11 on the first main surface 4 a side to be connected to the opposing input / output electrodes 8 of the chip substrate 2.

  The cap substrate 4 is formed with the above-described vias 13 corresponding to the connection electrodes 14, and the connection electrodes 14 are connected to the second wiring patterns 12 on the second main surface 4 b side through the vias 13. is doing. The cap substrate 4 is configured such that the first wiring pattern 11 is formed as a shield pattern 15 by forming a portion facing the chip element mounting region of the chip substrate 2 in a solid state, thereby mounting the chip mounted in the chip storage space portion 6. The element 3 is electrically shielded so that stable operation can be performed.

  A large number of external connection electrodes 16 connected to the connection electrodes 14 on the first wiring pattern 11 side via the vias 13 are formed on the second wiring pattern 12 on the second main surface 4 b side on the cap substrate 4. Has been. The cap substrate 4 is mounted on the module substrate 21 by the flip chip mounting method with the second main surface 4b as a mounting surface, as will be described in detail later. The external connection electrode 16 is connected to the electrode.

  In addition, although the cap board | substrate 4 showed the double-sided board | substrate which formed the 1st wiring pattern 11 and the 2nd wiring pattern 12 in the 1st main surface 4a and the 2nd main surface 4b of the organic insulating substrate 10, It may be a multilayer wiring board in which the wiring layer is formed in multiple layers. The cap substrate 4 constitutes a mounting body on the module substrate 21, but may be constituted by a large-sized substrate that also serves as the module substrate 21. However, the cap substrate 4 becomes unsuitable when a plurality of chip elements 2 and wiring patterns 7 formed on the chip substrate 2 are formed on the wafer 30 as will be described later.

  In the cap substrate 4, a bonding seal layer 5 is formed on the first main surface 4 a for bonding to the chip substrate 2. The bonding seal layer 5 is made of, for example, an ultraviolet curable benzocyclobutene resin-based sealing adhesive, and has a frame shape over the entire circumference along the outer peripheral edge where the connection electrodes 14 of the cap substrate 4 are formed. Formed. The bonding seal layer 5 is coated with a sealing adhesive with a predetermined thickness on the entire surface of the first main surface 4a, masked with the corresponding portion of each connection electrode 14 as an opening, irradiated with ultraviolet rays, and developed. By performing the processing, each connection electrode 14 is formed in a frame shape facing outward.

  When the cap substrate 4 is aligned with the input / output electrodes 8 facing each connection electrode 14 with the first main surface 4a as a mounting surface with respect to the chip substrate 2, the bonding seal layer 5 is combined with each connection electrode 14. Around the outer periphery of the mounting bump 9 to be crimped. The bonding seal layer 5 is cured by being irradiated with ultraviolet rays in a predetermined pressure state, and bonds the first main surface 4a of the cap substrate 4 and the main surface 2a of the chip substrate 2 in a sealed state. As shown in FIG. 1, the bonding seal layer 5 holds the operation amount of the movable portion 3 b between the first main surface 4 a and the main surface 2 a with respect to the cap substrate 4 with respect to the chip substrate 2. It is formed with a height that is set to an opposing interval that is sufficient for. The bonding seal layer 5 forms a chip element storage space portion 6 including a sealed space portion by bonding the first main surface 4a of the cap substrate 4 and the main surface 2a of the chip substrate 2 in a sealed state. .

  The bonding seal layer 5 has a composition in which the sealing adhesive is composed of 38% to 55% by weight of benzocyclobutene resin and 25% to 60% by weight of mesitylene, and is irradiated with ultraviolet rays for a predetermined time. After that, it is formed by developing with glycol ether. Further, the bonding seal layer 5 may be applied with an adhesive using a mask having an opening in the region facing each connection electrode 14. The bonding seal layer 5 may be formed using not only benzocyclobutene resin but also, for example, epoxy resin, acrylic resin, or silicon resin adhesive resin. The bonding seal layer 5 is made of a resin film material that maintains its adhesiveness in an uncured state, such as an anisotropic conductive film (ACF) used in, for example, semiconductor chip manufacturing processes. You may make it join to the 1st main surface 4a.

  The functional element body 1 covers each chip element 3 and the wiring pattern 7 in the wafer state, and the cap substrate 4 is bonded via the bonding seal layer 5, and the wafer 30 is individually cut between the cap substrates 4. It is cut into pieces and completed. In the functional element body 1, the bonding process of each cap substrate 4 to the wafer 30 is performed in a vacuum chamber or an inert gas atmosphere, so that the chip element storage space 6 is configured in a vacuum atmosphere or an inert gas atmosphere. Since the chip element storage space 6 is held in a highly airtight state, the functional element body 1 operates in a stable state without being affected by environmental conditions, and the movable part 3b. Oxidation such as the above is also suppressed and the life is extended.

  In the functional element body 1, the chip substrate 2 and the cap substrate 4 are integrated at the outer peripheral portion of the chip element 3 via the bonding seal layer 5, and the chip storage space portion 6 in which airtightness is maintained is configured. In the functional element body 1, since the chip element 3 and the wiring pattern 7 are formed with high precision and the handling property is improved, the chip element is prevented from being damaged and the yield is improved and the equipment is improved. Cost reduction by simplifying the process and improving productivity. Since the functional element body 1 is so-called chip size reduced, the mounting density of the circuit module body 20 is improved so as to reduce the size and increase the functionality, and the module via the cap substrate 4 is also provided. The mounting process on the substrate 21 is also easily performed.

  In the functional element body 1, bumps 17 are formed on each external connection electrode 16 of the second wiring pattern 12 formed on the second main surface 4 b of the cap substrate 4, and the main surface of the module substrate 21 is interposed via these bumps 17. The circuit module body 20 is configured by flip-chip mounting on 21a. Although the module substrate 21 is not particularly limited, it is preferable to use an insulating substrate of the same material described above having the same linear expansion coefficient in order to mount the cap substrate 4 in a stable state, and is formed by a conventionally known multilayer wiring board technique. .

  That is, a so-called double-sided substrate in which copper foil layers are formed on both sides of an insulating substrate is used as the module substrate 21, and a wiring pattern is formed on each copper foil layer to form a core substrate. Constitute. The module substrate 21 joins a prepreg with copper foil to both sides of the core substrate, forms a wiring pattern by patterning the copper foil layers of these prepregs, and further connects the wiring patterns of each layer as appropriate. Via formation is performed to complete the multilayer wiring board. Of course, the module substrate 21 is not limited to such a wiring substrate process, and may be formed by various wiring substrate techniques that have been conventionally implemented.

  Although not described in detail, the module substrate 21 has a large number of mounting electrodes 23 relative to each external connection electrode 16 formed on the cap substrate 4 of the functional element body 1 described above on the wiring pattern 22 formed on the main surface 21a. Is provided. The functional element body 1 is combined with the module substrate 21 by aligning the external connection electrodes 16 facing the mounting electrodes 22 with the second main surface 4b as a mounting surface. The module substrate 21 is heated and pressed by a heating and pressing device from the chip substrate 2 side, so that the bumps 17 formed on the external connection electrodes 16 are joined to the mounting electrodes 22 to function the functional element body 1. Is flip-chip mounted. The module substrate 21 is filled with the underfill 18 at the joint portion between each mounting electrode 22 and each external connection electrode 16 so that the functional element body 1 is firmly mounted. Although not shown, other chip components, electronic components, and the like are mounted on the main surface 21 a on the module substrate 21 to constitute the circuit module body 20.

  The manufacturing process of the functional element body 1 described above will be described with reference to FIGS. The manufacturing process of the functional element body 1 includes a wafer process in which a large number of chip elements 3 are provided on the main surface 30 a of the wafer 30 and a wiring pattern 7 is formed corresponding to each chip element 3. The manufacturing process of the functional element body 1 includes a cap substrate manufacturing process in which the cap substrate 4 is manufactured by the multilayer wiring board technology. The manufacturing process of the functional element body 1 includes a bonding seal layer forming process for forming the bonding seal layer 5 on each cap substrate 4. The manufacturing process of the functional element body 1 includes a cap substrate mounting process in which the cap substrate 4 is mounted on each chip element forming region 31 of the wafer 30 via the bonding seal layer 5. The manufacturing process of the functional element body 1 includes a wafer cutting process in which the wafer 30 is cut and the functional element bodies 1 are cut one by one.

  In the wafer process, chip element formation regions 31 are formed at a predetermined interval with respect to the supplied wafer 30, and input / output electrodes 8 and chips are formed on the respective chip element formation regions 31 as shown in FIG. A wiring pattern 7 having mounting electrodes is formed. In the wafer process, the chip elements 3 are mounted by connecting connection electrodes to the respective chip mounting electrodes of the respective wiring patterns 7. In the wafer process, as shown in FIG. 4, mounting bumps 9 having a predetermined height are formed on the input / output electrodes 8 of each wiring pattern 7.

  In the cap substrate manufacturing process, as described above, a predetermined patterning process on the double-sided substrate having the organic insulating substrate 10 as a base material, a step of laminating a prepreg with a copper foil on the double-sided substrate, or a predetermined pattern on the copper foil layer of the prepreg A patterning step is performed. In the cap substrate manufacturing process, the first wiring pattern 11 having the connection electrodes 14 that are relatively connected to the input / output electrodes 8 on the wafer 30 side is formed on the first main surface 4a through these processes, and the second main pattern 4a is formed. The second wiring pattern 12 having the external connection electrode 16 is formed on the surface 4b. In the cap substrate manufacturing process, the cap substrate 4 is completed by forming a plurality of vias 13 that pass through the organic insulating substrate 10 and the prepreg to connect predetermined portions of the first wiring pattern 11 and the second wiring pattern 12 to each other. .

  In the bonding seal layer forming step, a bonding seal having a predetermined thickness in a frame-like region along the outer peripheral edge surrounding the connection electrode 14 on the first main surface 4a of the cap substrate 4 manufactured by the cap substrate manufacturing step described above. Layer 5 is formed. In the bonding seal layer forming step, as described above, an ultraviolet curable sealing adhesive is used, and a patterning process is performed on the sealing adhesive layer formed by coating the entire surface of the first main surface 4a with a predetermined thickness. Then, a frame-shaped bonding seal layer 5 is formed with each connection electrode 14 facing outward.

  The cap substrate mounting step includes a cap substrate combining step of mounting the cap substrate 4 on each chip element formation region 31 of the wafer 30 in a vacuum or an inert gas atmosphere, and each chip element 3 via the bonding seal layer 5. A chip element sealing step of sealing in the chip element storage space 6. In the cap substrate combining step, as shown in FIG. 4, each of the chip elements 3 and each wiring pattern 7 of the wafer 30 is formed on the chip element formation region 31 with the first main surface 4a as a mounting surface. 4 are combined. In the cap substrate combining step, the mounting bumps 9 formed on the input / output electrodes 8 are fitted into the openings of the bonding seal layer 5 formed on the cap substrate 4, respectively, and these mounting bumps 9 pass through the openings. Then, it hits the connection electrode 14 facing outward.

  In the chip element sealing step, each cap substrate 4 is heated and pressed against the wafer 30 by a heating and pressing device. In the chip element sealing step, the mounting bumps 9 formed on the input / output electrodes 8 are joined to the connection electrodes 14 and the cap substrate 4 is flip-chip mounted on the wafer 30. In the chip element sealing step, the bonding seal layer 5 is cured by performing a heating / pressing operation, and the cap substrates 4 are integrated on the wafer 30.

  In the chip element sealing step, as shown in FIG. 5, the first main surface 4a of each cap substrate 4 and the main surface 30a of the wafer 30 are held at a predetermined facing distance by the bonding seal layer 5, and this bonding seal The layer 5 closes the outer peripheral portion and seals each chip element 3 </ b> A and each wiring pattern 7 in the chip element storage space 6.

  In the wafer cutting step, the wafer 30 is cut between the cap substrates 4 using a slitter or the like as shown in FIG. In the wafer cutting step, each of the cut wafers 30 constitutes the chip substrate 2 to complete the functional element body 1.

  In the method of manufacturing the functional element body 1, each chip element 3 having the fine movable portion 3 b and the fine pitch wiring pattern 7 can be formed on the main surface 30 a of the wafer 30 with high accuracy. In the method of manufacturing the functional element body 1, handling performance is greatly improved by dividing the wafer 30 in a state where each chip element 3 and the wiring pattern 7 are covered with the cap substrate 4 via the bonding seal layer 5. Further, the occurrence of damage or the like of the chip element 3 is prevented and the yield is improved, and the cost is reduced by simplifying the facility and improving the productivity. In the method of manufacturing the functional element body 1, the chip element 3 is housed in the chip element housing space 6 in a highly airtight state, so that a stable operation is performed and oxidation of the movable part 3b and the like is suppressed, and a long lifetime is achieved. Therefore, an inexpensive functional element body 1 with a reduced chip size is manufactured.

It is sectional drawing of the functional element body shown as embodiment. It is sectional drawing of the circuit module body which mounted the functional element body. It is sectional drawing of the wafer in which the chip element and the wiring pattern were formed. It is sectional drawing which shows the mounting process of a cap board | substrate. It is sectional drawing which shows the cutting process of a wafer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Functional element body, 2 chip board | substrate, 3 chip element, 4 cap board | substrate, 5 joining sealing layer, 6 chip element storage space part, 7 wiring pattern, 8 input / output electrode, 9 mounting bump, 10 organic insulation board | substrate, 11th 1 wiring pattern, 12 second wiring pattern, 13 via, 14 connection electrode, 15 shield pattern, 16 external connection electrode, 17 bump, 18 underfill, 20 circuit module body, 21 module substrate, 22 wiring pattern, 23 mounting electrode , 30 Wafer, 31 Chip element formation area

Claims (3)

A chip substrate formed by cutting a wafer on which a chip element and a wiring pattern having predetermined input / output electrodes connected to the chip element are formed on the main surface;
A first wiring pattern having a connection electrode relatively connected to the input / output electrode is formed on the first main surface, and an interlayer connection and an external connection electrode are connected to the first wiring pattern through a via on the second main surface. A second wiring pattern having a cap substrate mounted on the main surface of the chip substrate with the first main surface as a mounting surface;
A frame-shaped region surrounding the connection electrode is formed on the first main surface of the cap substrate to have a predetermined thickness, and includes a bonding seal layer that bonds the cap substrate to the chip substrate.
A chip element storage space for sealing the chip element is formed between the main surface of the chip substrate bonded by the bonding seal layer and the first main surface of the cap substrate, and the chip substrate is used as a ceiling portion. A functional element body mounted on a mounting substrate via the external connection electrode with the second main surface of the cap substrate as a mounting surface.   The cap substrate is formed of an organic insulating substrate, and the first wiring pattern has a shield metal layer that covers a constituent portion of the chip element storage space with a metal layer over the entire area. 2. The functional element body according to 1. Forming a plurality of chip elements on a main surface of a chip substrate made of a wafer; forming a plurality of wiring patterns having predetermined input / output electrodes for each of the chip elements; A wafer process having a process of forming a connection bump on each electrode;
A step of forming a first wiring pattern having a connection electrode that is connected to each of the input / output electrodes on at least a first main surface using an organic insulating substrate as a base material; and a second step having an external connection electrode on a second main surface A cap substrate manufacturing step comprising: forming a wiring pattern; and forming a via penetrating the organic insulating substrate to connect the first wiring pattern and the second wiring pattern.
Bonding seal for forming a bonding seal layer on the first main surface of the cap substrate, which is formed of a frame-shaped layer having a predetermined thickness in a frame-shaped region surrounding the connection electrode, and bonds the cap substrate to the chip substrates. A layer forming step;
Positioning the cap substrate with respect to the chip substrate with the first main surface as a mounting surface and positioning the connection electrodes on the main surface relative to the input / output electrodes; and combining the cap substrate with the chip The bonding seal layer is cured and integrated with respect to the substrate to integrate the chip elements into the chip element storage spaces formed between the main surface of the cap substrate and the first main surface of the cap substrate. Cap substrate mounting process for sealing the chip element;
A wafer cutting step in which the wafer is cut and separated into one chip substrate between the cap substrates.
A method for manufacturing a functional element body, wherein the functional element body is mounted on the mounting substrate via the external connection electrode with the chip substrate as a ceiling and the second main surface of the cap substrate as a mounting surface. .

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