JP2006135526A - Output buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a response time from input to output and a transition time of the output shorter than before when an input signal is fast and when an output load is small as compared with the driving capacity of an output-stage transistor. <P>SOLUTION: The present invention includes an output-stage buffer 1, pre-buffers 2 and 3 which drive the output-stage buffer 1, and control circuits 4 and 5 which control input signals to the pre-buffers 2 and 3 based upon signals that the pre-buffers 2 and 3 output to the output-stage buffer 1. The pre-buffers 2 and 3 vary in driving capacity in steps based upon the signals output to the output buffer 1. The control circuits 4 and 5 control the input signals to the pre-buffers 2 and 3 so that the signals that the pre-buffers 2 and 3 output to the output-stage buffer 1 gently vary at the start of the variation of the input signals and also speedily vary a specified time after the start of variation of the input signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an output buffer circuit used in a semiconductor integrated device or the like, and in particular, can reduce a response time from an input to an output and an output transition time while reducing a through current and unnecessary radiation.

In recent years, semiconductor products are often used together with receiving devices in the same system for reasons such as integration of receiving devices. In addition, due to higher performance of receiving devices, unnecessary radiation emitted from semiconductor products often causes malfunctions. One means for reducing unwanted radiation is to increase the signal transition time.
Incidentally, an output buffer circuit is known as an electronic circuit used in a semiconductor integrated device or the like. In such an output buffer circuit, the response time from the input to the output and the transition time of the output are extremely large even when the output load is increased while reducing the through current and unnecessary radiation, which are usual problems. What does not become large is known (for example, refer to Patent Document 1).

  As shown in FIG. 7, this conventional output buffer circuit includes output stage MOS transistors P1, N1 for driving an output load, MOS transistors P2, N2 operating in the same manner as the MOS transistors P1, N1, and an input stage. MOS transistors P3 and N3, and MOS transistors P4 and N4 constituting a control circuit. In FIG. 7, the output load driven by the MOS transistors P1 and N1 in the output stage is not shown.

Next, the operation of the conventional output buffer circuit having such a configuration will be described with reference to FIG. In the following description, for the sake of convenience, the potential of the high power supply voltage VDD is assumed to be “H” level, and the potential of the low power supply voltage VSS is assumed to be “L” level.
As shown in FIG. 8A, when the potential of the input signal In transitions from the “L” level to the “H” level at time t1, the P-type MOS transistor P3 is turned off and the N-type MOS transistor N3 is turned on. . When the N-type MOS transistor N3 is turned on, the potential of the node A2 quickly becomes “L” level (see FIG. 8C), and the N-type MOS transistors N1 and N2 are turned off.

  At time t1, as shown in FIG. 8D, the potential of the node A3 is at the “L” level, the N-type MOS transistor N4 is off, and the P-type MOS transistor P4 is on. At this time, as shown in FIG. 8B, the potential of the node A1 is at the “H” level, but since the N-type MOS transistor N3 and the P-type MOS transistor P4 are on, the “A” level thereafter. The voltage decreases until the threshold voltage (absolute value) of the P-type MOS transistor P4 is reached.

Thereafter, at time t2, the P-type MOS transistors P1 and P2 are gradually turned on as the potential of the node A1 decreases, and the potential of the output signal Out and the potential of the node A3 start to increase gradually ( (See FIGS. 8D and 8E).
Then, from time t2 to time t3, the potential of the node A3 increases from the “L” level toward the “H” level (see FIG. 8D). Furthermore, since the potential of the node A3 rises from time t3 to time t4, the N-type MOS transistor N4 is gradually turned on.

Thereafter, at time t4, as the N-type MOS transistor N4 is turned on, the potential of the node A1 quickly transitions to the “L” level (see FIG. 8B), and the P-type MOS transistors P1 and P2 are completely turned on. The output signal Out and the potential of the node A3 quickly transition to the “H” level (see FIGS. 8D and 8E).
Here, FIG. 8F shows the current Ivdd flowing from the P-type MOS transistor P1 to the output load, and FIG. 8G shows the current Ivss flowing from the output load to the N-type MOS transistor N1. .

As shown in FIG. 8 (f), the current Ivdd becomes a constant value from the time t2 when the P-type MOS transistor P1 is turned on, and the potential of the node A1 decreases from the time t3. And gradually decreases from time t4 when the P-type MOS transistor P1 is completely turned on.
When the potential of the input signal In transitions from the “H” level to the “L” level, the operation of each paired MOS transistor such as the MOS transistors P1 and N1 is reversed, and the polarity of the potential is inverted. The circuit operation is the same as in the above case.

The feature of the conventional output buffer circuit shown in FIG. 7 is that the MOS transistors connected in series between the power supplies do not turn on simultaneously. For this reason, the through current between the power supplies is small, and the output stage MOS transistor P1 or N1 has a small inrush current generated between the output stage transistor and the output load at the start of output transition.
In addition, since the predetermined time that the MOS transistor in the output stage is completely turned on is not related to the output load, the response time from the input to the output and the transition time of the output even when the output load increases. It also has the feature of not becoming extremely large.
JP-A-10-290154

  However, in the conventional output buffer circuit, when the input signal is high-speed and when the output load is small with respect to the driving capability of the MOS transistor of the output stage, during the period when the MOS transistor of the output stage is in the half-on state, Since the transition of the output is completed, there is a problem that the response time from the input to the output and the transition time of the output are significantly increased as compared with a general output buffer circuit.

  Therefore, an object of the present invention is to realize a response time and an output from an input to an output even when an output load is increased when realizing reduction of a through current and unnecessary radiation, which is a constant problem of an output buffer circuit. Taking advantage of the conventional technology that the transition time does not increase excessively, when the input signal is high-speed and when the output load is small with respect to the driving capability of the MOS transistor in the output stage, the response time from the input to the output and the output An object of the present invention is to provide an output buffer circuit capable of making the transition time faster than the conventional one.

In order to solve the above-described problems and achieve the object of the present invention, the inventions according to claims 1 to 6 have the following configurations.
That is, the invention according to claim 1 is directed to an output stage buffer that outputs an output signal, a prebuffer that inputs an input signal and drives the output stage buffer, and a signal that the prebuffer outputs to the output stage buffer. And a control circuit for controlling an input signal to the pre-buffer.
According to a second aspect of the present invention, in the output buffer circuit according to the first aspect, the driving capability of the pre-buffer varies stepwise based on a signal output to the output stage buffer.

According to a third aspect of the present invention, in the output buffer circuit according to the first or second aspect, at the start of the transition of the input signal, the control circuit moderates a signal output from the pre-buffer to the output stage buffer. The input signal to the pre-buffer is controlled so that the signal output from the pre-buffer to the output stage buffer is quickly changed after a predetermined time has elapsed from the start of the input signal transition. It has become.
According to a fourth aspect of the present invention, there is provided the output buffer circuit according to the third aspect, wherein the output buffer circuit is provided between an output side of the prebuffer and a control terminal of the control circuit, and from the input of the input signal to the output of the output signal. And a circuit for setting the response time and the output transition time to desired values.

  The invention according to claim 5 is connected in series with the output stage buffer having the first MOS transistor, the second MOS transistor, and the second MOS transistor, and has a polarity different from that of the second MOS transistor. A pre-buffer having a third transistor, a fourth MOS transistor, and a fifth MOS transistor connected in parallel with the fourth MOS transistor and having a polarity different from that of the fourth MOS transistor constitute a switch. And a control circuit for controlling the input voltage of the pre-buffer, and an input terminal is connected to the gate of the second MOS transistor and to the gate of the third MOS transistor through the switch. The connection point of the second and third MOS transistors is the first MOS transistor. Is connected to the gate of the data, are connected to the gates of said fourth and fifth MOS transistors, and the drain of said first MOS transistor is connected to the output terminal.

  The invention according to claim 6 is connected in series with the output stage buffer having the first MOS transistor, the second MOS transistor, and the second MOS transistor, and has a polarity different from that of the second MOS transistor. A pre-buffer having a third transistor, a fourth MOS transistor, and a fifth MOS transistor connected in parallel with the fourth MOS transistor and having a polarity different from that of the fourth MOS transistor constitute a switch. And a control circuit for controlling the input voltage of the pre-buffer, and an input terminal is connected to the gate of the second MOS transistor and to the gate of the third MOS transistor through the switch. The connection point of the second and third MOS transistors is the first MOS transistor. The gate of the fourth MOS transistor, the gate of the fifth MOS transistor is connected to a power supply terminal, and the drain of the first MOS transistor is connected to the output terminal. It is connected.

According to the present invention, an inrush current generated between the output stage transistor and the output load at the start of output transition can be suppressed, and noise and unnecessary radiation can be reduced.
Further, in the present invention, by controlling so that the transition of the gate voltage of the output stage transistor does not stagnate, even when the input signal is high speed and the output load is small relative to the driving capability of the output stage MOS transistor, The response time from output to output and the output transition time can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of an output buffer circuit of the present invention.
In the first embodiment, as shown in FIG. 1, an output stage buffer 1, prebuffers 2 and 3 for driving the output stage buffer 1, and signals output from the prebuffers 2 and 3 to the output stage buffer 1 are used. Control circuits 4 and 5 that control input signals to the pre-buffers 2 and 3 based on the input circuit 6, an input terminal 6 to which the input signal In is input, and an output terminal 7 for taking out the output signal Out are provided.

The output stage buffer 1 drives an output load (not shown). For this reason, as shown in FIG. 1, the output stage buffer 1 is composed of a P-type MOS transistor P1 and an N-type MOS transistor N1, which are connected in series and the common connection portion is connected to the output terminal 7. Yes.
That is, in the MOS transistor P1, a high power supply voltage VDD is supplied to the source, the drain is connected to the drain of the MOS transistor N1, and the common connection portion is connected to the output terminal 7. The MOS transistor N1 is supplied with a low power supply voltage VSS at its source. Further, the output signals of the pre-buffers 2 and 3 are supplied to the gates of the MOS transistors P1 and N1, respectively.

The pre-buffers 2 and 3 operate according to the input signal In and a signal that is controlled by the control circuits 4 and 5, respectively, and drives the output stage buffer 1 by the output signal.
Therefore, as shown in FIG. 1, the pre-buffer 2 is composed of a P-type MOS transistor P2 and an N-type MOS transistor N3 having a polarity different from that of the P-type MOS transistor P2. The transistor P1 is connected to the gate.

  That is, in the MOS transistor P2, a high power supply voltage VDD is supplied to the source, the drain is connected to the drain of the MOS transistor N3, and the common connection portion is connected to the gate of the MOS transistor P1. The MOS transistor N3 is supplied with a low power supply voltage VSS at its source. Further, an input signal In is supplied to the gate of the MOS transistor P2, and a signal obtained by controlling the input signal In by the control circuit 4 is supplied to the gate of the MOS transistor N3.

As shown in FIG. 1, the pre-buffer 3 is composed of a P-type MOS transistor P3 and an N-type MOS transistor N2 having a different polarity from the P-type MOS transistor P3, which are connected in series, and the common connection portion is a MOS transistor. It is connected to the gate of N1.
That is, in the MOS transistor P3, the high power supply voltage VDD is supplied to the source, the drain is connected to the drain of the MOS transistor N2, and the common connection portion is connected to the gate of the MOS transistor N1. The MOS transistor N2 is supplied with a low power supply voltage VSS at its source. Further, a signal obtained by controlling the input signal In by the control circuit 5 is supplied to the gate of the MOS transistor P3, and the input signal In is supplied to the gate of the MOS transistor N2.

The control circuits 4 and 5 gently transition the signals output from the pre-buffers 2 and 3 to the output stage buffer 1 at the start of the transition of the input signal In, and after a predetermined time has elapsed from the start of the transition of the input signal In, The input signals to the pre-buffers 2 and 3 are controlled so that the signals output from the pre-buffers 2 and 3 to the output stage buffer 1 are quickly changed.
Therefore, as shown in FIG. 1, the control circuit 4 includes a P-type MOS transistor P4 and an N-type MOS transistor N5 having a different polarity from the P-type MOS transistor P4, and includes an electronic switch in which these are connected in parallel. The input signal In is supplied to one end side of the parallel circuit, and the output signal output from the other end side is supplied to the gate of the MOS transistor N3. Further, the output signal of the pre-buffer 2 is supplied to the gates of the MOS transistors P4 and N5, and the conduction control of the MOS transistors P4 and N5 is performed.

  That is, the drain of the MOS transistor P4 and the source of the MOS transistor N5 are connected, and this common connection is connected to the input terminal 6. The source of the MOS transistor P4 and the drain of the MOS transistor N5 are connected, and this common connection is connected to the gate of the MOS transistor N3. Further, the gates of the MOS transistors P4 and N5 are connected in common, and this common connection is connected to the common connection of the MOS transistors P2 and N3 and the gate of the MOS transistor P1, respectively.

  Further, as shown in FIG. 1, the control circuit 5 includes a P-type MOS transistor P5 and an N-type MOS transistor N4 having a different polarity from the P-type MOS transistor P5, and includes an electronic switch in which these are connected in parallel. The input signal In is supplied to one end side of the parallel circuit, and the output signal output from the other end side is supplied to the gate of the MOS transistor P3. Further, the output signal of the pre-buffer 3 is supplied to the gates of the MOS transistors P5 and N4, and the conduction control of the MOS transistors P5 and N4 is performed.

  That is, the drain of the MOS transistor P5 and the source of the MOS transistor N4 are connected, and this common connection is connected to the input terminal 6. The source of the MOS transistor P5 and the drain of the MOS transistor N4 are connected, and this common connection is connected to the gate of the MOS transistor P3. Further, the gates of the MOS transistors P5 and N4 are connected in common, and this common connection is connected to the common connection of the MOS transistors P3 and N2 and the gate of the MOS transistor N1.

Next, an operation example of the first embodiment having such a configuration will be described with reference to FIG. 1 and FIG.
As shown in FIG. 2A, when the potential of the input signal In transitions from the “L” level to the “H” level at time t1, the P-type MOS transistor P2 is turned off and the N-type MOS transistor N2 is turned on. . When the N-type MOS transistor N2 is turned on, the potential of the node AN1 quickly becomes “L” level (see FIG. 2C), the N-type MOS transistors N1 and N4 are turned off, and the P-type MOS transistor P5 is turned on.

  Accordingly, since the “H” level that is the potential of the input signal In propagates to the node AN2 without being lowered, the potential of the node AN2 becomes the “H” level (see FIG. 2E), and the P-type MOS transistor P3. Turn off. At this time, as shown in FIG. 2B, the potential of the node AP1 is at “H” level, the P-type MOS transistor P4 is turned off, and the N-type MOS transistor N5 is turned on. Therefore, as shown in FIG. 2 (d), the potential that is lowered by the threshold voltage of the N-type MOS transistor N5 is propagated to the node AP2 from the "H" level that is the potential of the input signal In. N3 is in a semi-on state.

Thereafter, at time t2, as shown in FIG. 2B, the potential of the node AP1 starts to gradually decrease. Along with the decrease, the P-type MOS transistor P1 is in a half-on state, and the potential of the output signal Out gradually rises from the “L” level (see FIG. 2F).
At time t3, since the potential of the node AP1 exceeds the threshold voltage (absolute value) of the P-type MOS transistor P4, the P-type MOS transistor P4 is turned on. When the P-type MOS transistor P4 is turned on, the “H” level, which is the potential of the input signal In, propagates without decreasing. Therefore, as shown in FIG. 2D, the potential of the node AP2 is quickly set to the “H” level. To rise.

Therefore, at time t4, the N-type MOS transistor N3 transitions from the half-on state to the complete on-state, and the potential of the node AP1 quickly decreases to the “L” level (see FIG. 2B). Along with this, the P-type MOS transistor P1 also completely transitions to the on state, so that the potential of the output signal Out quickly transitions to the “H” level (see FIG. 2 (f)).
Here, FIG. 2G shows the current Ivdd flowing from the P-type MOS transistor P1 to the output load, and FIG. 2H shows the current Ivss flowing from the output load to the N-type MOS transistor N1. .

As shown in FIG. 2G, the current Ivdd turns the P-type MOS transistor P1 into a half-on state, gradually increases from time t2, and turns on the P-type MOS transistor P1 completely. It gradually decreases from time t3.
In the above description, the case where the potential of the input signal In transitions from the “L” level to the “H” level has been described. On the other hand, when the potential of the input signal In transitions from the “H” level to the “L” level, the operation of each paired MOS transistor such as the MOS transistors P1 and N1 is reversed, and the polarity of the potential is changed. Each circuit is simply inverted, and the circuit operation is the same as in the above case.

  As described above, in the first embodiment, the gate voltage of the MOS transistors of the pre-buffers 2 and 3 is controlled stepwise based on the gate voltage of the MOS transistors of the output stage buffer 1, so that the output signal Out At the start of the transition, the gate voltage of the MOS transistor of the output stage buffer 1 is gradually changed, and after a predetermined time has elapsed, the gate voltage of the MOS transistor of the output stage buffer 1 is quickly changed.

That is, in the first embodiment, unlike the conventional circuit, control is performed so that the transition of the gate voltage of the MOS transistor of the output stage buffer 1 does not stagnate during the period from the start to the completion of the transition of the output signal Out.
Therefore, according to the first embodiment, the response time from the input to the output and the transition time of the output when the input signal is high-speed and when the output load is small with respect to the driving capability of the MOS transistor in the output stage. Increase can be suppressed.
In addition, according to the first embodiment, the features that the response time and the transition time do not increase excessively when the output load is increased and the reduction of the through current and unnecessary radiation, which are the features of the conventional circuit, are lost. Not.

(Second Embodiment)
FIG. 3 is a circuit diagram showing the configuration of the second embodiment of the output buffer circuit of the present invention.
This second embodiment is basically the same as the configuration of the first embodiment shown in FIG. 1, and is obtained by replacing the control circuits 4 and 5 shown in FIG. 1 with control circuits 4A and 5A shown in FIG. is there.
That is, as shown in FIG. 3, the control circuit 4A supplies a high power supply voltage VDD to the gate of the MOS transistor N5 constituting it, and the control circuit 5A is low to the gate of the MOS transistor P5 constituting it. The power supply voltage VSS is supplied. That is, the gates of the MOS transistors N5 and P5 are connected to the power supply terminal. These points are different in configuration from the control circuits 4 and 5 of the first embodiment.

Therefore, in the second embodiment, as shown in FIG. 3, the configuration of the other parts except the configuration of the control circuits 4A and 5A is the same as the configuration of the first embodiment shown in FIG. The same reference numerals are given to the constituent elements of FIG.
Since the operation of the second embodiment is the same as that of the first embodiment, the description of the operation is omitted. Further, according to the second embodiment, the same effect as the first embodiment can be realized.

(Third embodiment)
FIG. 4 is a circuit diagram showing the configuration of the third embodiment of the output buffer circuit of the present invention.
In the third embodiment, as shown in FIG. 4, the output stage buffer 1, pre-buffers 2 and 3 for driving the output stage buffer 1, and signals output from the pre-buffers 2 and 3 to the output stage buffer 1 are used. Based on the control circuits 4 and 5 for controlling the input signals to the pre-buffers 2 and 3, and delay circuits 8 provided between the output sides of the pre-buffers 2 and 3 and the control terminals of the control circuits 4 and 5, 9, an input terminal 6 to which the input signal In is input, and an output terminal 7 for taking out the output signal Out.

That is, the third embodiment is based on the first embodiment shown in FIG. 1 and further adds delay circuits 8 and 9 shown in FIG. Accordingly, in the third embodiment, the configuration of the other parts is the same as the configuration of the first embodiment shown in FIG. 1 except for the configuration in which the delay circuits 8 and 9 are added. The same reference numerals are given and description of the configuration is omitted.
The delay circuit 8 is a circuit that delays the time required to turn the N-type MOS transistor N3 of the pre-buffer 2 from the half-on state to the complete-on state by a predetermined time.

Therefore, the delay circuit 8 is provided between the node AP1 and the gates of the P-type MOS transistor P4 and the N-type MOS transistor N5, and the gates of the MOS transistors P4 and N5 are the node AP3.
The delay circuit 9 is a circuit that delays the time required to turn the P-type MOS transistor P3 of the pre-buffer 3 from the half-on state to the complete-on state by a predetermined time.
Therefore, the delay circuit 9 is provided between the node AN2 and the gates of the P-type MOS transistor P5 and the N-type MOS transistor N4, and the gates of the MOS transistors P5 and N4 are the node AN3.

Next, a specific configuration example of the delay circuits 8 and 9 will be described with reference to FIGS.
As shown in FIG. 5, the delay circuit 8 includes a P-type MOS transistor P6 and a delay element 81 in which a plurality of diode-connected P-type MOS transistors P7 are connected in series.
The P-type MOS transistor P6 has a gate connected to the input terminal 6, a high power supply voltage VDD supplied to the source, and a drain connected to the node AP3 (the gates of the MOS transistors P4 and N5). The delay element 81 has one end side (input side) connected to the node AP1 (the gate of the MOS transistor P1) and the other end side (output side) connected to the node AP3.
As shown in FIG. 6, the delay circuit 9 includes an N-type MOS transistor N6 and a delay element 91 in which a plurality of diode-connected N-type MOS transistors N7 are connected in series.

The N-type MOS transistor N6 has a gate connected to the input terminal 6, a low power supply voltage VSS supplied to the source, and a drain connected to the node AN3 (the gates of the MOS transistors P5 and N4). The delay element 91 has one end side (input side) connected to the node AN1 (the gate of the MOS transistor N1) and the other end side (output side) connected to the node AN3.
Here, the delay circuits 8 and 9 are configured by a combination of MOS transistors as shown in FIG. 5 and FIG. 6, but may be configured by a resistance element or a resistance element and a capacitance element instead. .

Next, the operation of the delay circuit 8 shown in FIG. 5 will be described with reference to the drawings.
In FIG. 5, when the potential of the input signal In supplied to the gate of the MOS transistor P6 transitions from the “H” level to the “L” level, the P-type MOS transistor P6 is turned on and the potential of the node AP3 is set to the “H” level. Transition to. On the other hand, when the potential of the input signal In transitions from the “L” level to the “H” level, the P-type MOS transistor P6 is turned off, and the potential of the node AP3 maintains the “H” level. At this time, although the potential of the node AP1 is at the “H” level, the N-type MOS transistor N3 in FIG. 4 is in a half-on state, and thus gradually decreases from the “H” level.

  Therefore, the delay element 81 composed of a plurality of P-type MOS transistors P7 is sequentially turned on from the side of the P-type MOS transistor 7 connected to the node AP1, and the potential of the node AP3 is set to each threshold value of the plurality of P-type MOS transistors P7. The voltage drops to the sum of the voltage (absolute value). Therefore, by setting the number of the plurality of P-type MOS transistors P7, the response time from the input to the output and the output transition time can be changed to desired values.

Next, the operation of the delay circuit 9 shown in FIG. 6 will be described with reference to the drawings.
In FIG. 6, when the potential of the input signal In supplied to the gate of the MOS transistor N6 transitions from the “L” level to the “H” level, the N-type MOS transistor N6 is turned on and the potential of the node AN3 is set to the “L” level. Transition to. On the other hand, when the potential of the input signal In transitions from the “H” level to the “L” level, the N-type MOS transistor N6 is turned off, and the potential of the node AN3 is maintained at the “L” level. At this time, the potential of the node AN1 is at the “L” level, but the P-type MOS transistor P3 in FIG. 4 is in a half-on state, and thus gradually increases from the “L” level.

Therefore, the delay element 91 composed of a plurality of N-type MOS transistors N7 is sequentially turned on from the side of the N-type MOS transistor N7 connected to the node AN1, and the potential of the node AN3 is set to each threshold value of the plurality of N-type MOS transistors N7. It rises to the potential of the sum of the voltage (absolute value). Therefore, if the number of the plurality of N-type MOS transistors N7 is set, the response time from the input to the output and the output transition time can be changed to desired values.
As described above, in the third embodiment, the delay circuits 8 and 9 are further added to the configuration of the first embodiment shown in FIG. It becomes possible to set the response time until the output and the transition time of the output to desired values.

The present invention is an output buffer circuit and is applied to a semiconductor integrated device or the like.

It is a circuit diagram of a 1st embodiment of the present invention. It is a wave form diagram which shows the example of a waveform of each part of FIG. It is a circuit diagram of a 2nd embodiment of the present invention. It is a circuit diagram of a 3rd embodiment of the present invention. It is a circuit diagram which shows the specific example of a delay circuit. It is a circuit diagram which shows the other specific example of a delay circuit. It is a circuit diagram of a conventional circuit. It is a wave form diagram which shows the example of a waveform of each part of FIG.

Explanation of symbols

P1-P7 P-type MOS transistor N1-N7 N-type MOS transistor 1 Output stage buffer 2, 3 Pre-buffer 4, 5 Control circuit 6 Input terminal 7 Output terminal 8, 9 Delay circuit

Claims (6)

An output stage buffer for outputting an output signal;
A pre-buffer that inputs an input signal and drives the output stage buffer;
A control circuit for controlling an input signal to the pre-buffer based on a signal output from the pre-buffer to the output stage buffer;
An output buffer circuit comprising:   2. The output buffer circuit according to claim 1, wherein the pre-buffer has a driving capability that changes stepwise based on a signal output to the output stage buffer. 3.   The control circuit gently transitions the signal output from the pre-buffer to the output stage buffer at the start of the transition of the input signal, and after a predetermined time has elapsed from the start of the transition of the input signal, the pre-buffer 3. The output buffer circuit according to claim 1, wherein an input signal to the pre-buffer is controlled so that a signal output to the output stage buffer is quickly changed.   A circuit that is provided between the output side of the pre-buffer and the control terminal of the control circuit, and sets a response time and an output transition time from the input of the input signal to the output of the output signal to desired values; The output buffer circuit according to claim 3, further comprising: An output stage buffer having a first MOS transistor;
A pre-buffer having a second MOS transistor and a third transistor connected in series with the second MOS transistor and having a polarity different from that of the second MOS transistor;
A fourth MOS transistor and a fifth MOS transistor connected in parallel with the fourth MOS transistor and having a polarity different from that of the fourth MOS transistor constitute a switch, and control the input voltage of the prebuffer. A control circuit,
An input terminal is connected to the gate of the second MOS transistor and is connected to the gate of the third MOS transistor via the switch.
The connection point of the second and third MOS transistors is connected to the gate of the first MOS transistor and to the gates of the fourth and fifth MOS transistors,
An output buffer circuit, wherein a drain of the first MOS transistor is connected to an output terminal. An output stage buffer having a first MOS transistor;
A pre-buffer having a second MOS transistor and a third transistor connected in series with the second MOS transistor and having a polarity different from that of the second MOS transistor;
A fourth MOS transistor and a fifth MOS transistor connected in parallel with the fourth MOS transistor and having a polarity different from that of the fourth MOS transistor constitute a switch, and control the input voltage of the prebuffer. A control circuit,
An input terminal is connected to the gate of the second MOS transistor and is connected to the gate of the third MOS transistor via the switch.
The connection point of the second and third MOS transistors is connected to the gate of the first MOS transistor and to the gate of the fourth MOS transistor,
A gate of the fifth MOS transistor is connected to a power supply terminal;
An output buffer circuit, wherein a drain of the first MOS transistor is connected to an output terminal.

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