JP2006135153A - Buildup printed-circuit board and bond structure of electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of solder junctions on a buildup printed wiring board taking a stack via structure. <P>SOLUTION: In the junction structure of a buildup printed wiring board with electronic components, stack vias on the outermost layer are formed with conductive paste. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a configuration in which a build-up printed wiring board and an electronic component having a stacked via structure are mounted on the build-up printed wiring board, in particular, a stack via structure of the build-up printed wiring board and a copper on which the electronic component is mounted. The present invention relates to a method for arranging foil lands.

  In recent years, portable devices typified by mobile phones and digital cameras have become more sophisticated and smaller in size, and various semiconductor devices used for these devices are required to be thin and small. As a package structure of various semiconductor devices for multi-pins that meet this requirement, a ball grid array (BGA) in which a plurality of solder balls are arranged on the surface as connection terminals in a grid pattern and protruded, and a semiconductor Si chip is sealed with resin And an area array type semiconductor device called a chip size package (CSP).

  As a printed wiring board on which these BGA and CSP are mounted, a build-up wiring board has been proposed that is compatible with the narrow pitch and multi-pin configuration of an area array type semiconductor device.

  Stack via build-up printed wiring with a via structure in which the interlayer signal connection of the build-up printed wiring board is formed in a stack to further increase the density of the build-up printed wiring board that supports narrow pitch and high pin count. Substrates have also been proposed.

  By using the build-up printed wiring board having the stacked via structure, the wiring density of the printed wiring board can be improved and the degree of design freedom can be improved, thereby realizing high density.

As a technique for improving the stack via interlayer connection reliability in a build-up printed wiring board having a stacked via structure, as shown in Japanese Patent Application Laid-Open Nos. 2003-23251 and 2003-304061, a stack via formation of a build-up printed wiring board is performed. A method using a material with a low coefficient of linear expansion as the resin material used as the interlayer insulating layer is proposed, reducing the stress generated in the interlayer connection resin layer near the via hole and reducing the cracks generated in the interlayer connection resin layer. It was suppressed.
JP2003-23251 JP 2003-304061 A

  However, in the build-up printed wiring board having the stacked via structure disclosed in Japanese Patent Application Laid-Open Nos. 2003-23251 and 2003-304061 in the above-described conventional example, the case where a crack occurs in the interlayer connection resin layer in the vicinity of the via hole Although effective, in many cases the copper foil land on the stack via is also used as an electrode for joining electronic parts, the solder represented by the heat cycle test is used for the solder that joins the copper foil land and the electronic part electrode. When the stress test was given, there was a problem that cracks occurred in the solder joints in a very short test cycle.

  The above-mentioned conventional example does not mention cracks in the solder joints, but as a structural problem peculiar to build-up printed wiring boards having a stacked via structure, cracks occur in the interlayer connection resin layer near the via hole. The authors have inferred that solder cracks have occurred in the solder joints with a mechanism similar to the mechanism used.

  The object of the first invention according to the present application based on the above inference is to solve the above-mentioned problems. The copper foil land and the electronic component electrode of the build-up printed wiring board having the stacked via structure are provided. An object of the present invention is to provide a solder joint structure between an electronic component and a build-up printed wiring board having high reliability by extending the rupture life of a solder joint without causing cracks in the solder to be joined.

  In order to achieve the above object, a first invention according to the present application is formed in at least an outermost layer of the buildup printed wiring board in a structure for joining a buildup printed wiring board having a stacked via structure and an electronic component. The stacked via is formed of a conductive paste.

  In the above configuration, the means for forming the stack via formed at least on the outermost layer of the stack via with a conductive paste made of metal and resin allows the linear expansion coefficients of the interlayer insulating resin and the conductive paste of the outermost layer to be approximately equal. As a result, the stress acting between the interlayer insulating resin and the conductive paste is further reduced compared to the case where the conventional interlayer insulating resin has a smaller linear expansion coefficient and a copper stacked via is formed, and a stacked via structure is adopted. Stress relaxation to the solder joining the copper foil land of the build-up printed wiring board and the electronic component electrode is possible.

  In order to achieve the above object, a second invention according to the present application is a structure in which a build-up printed wiring board having a stacked via structure and an electronic component are joined, and a pattern is drawn out from a surface copper foil land of the stacked via. It is connected to a copper land for joining parts.

  In the above-mentioned configuration, the stack that does not serve as both the copper via land of the stacked via and the copper foil land of the electronic component by means of connecting the copper land for bonding the electronic component by drawing the pattern from the surface copper foil land of the stacked via. A build-up printed wiring board structure having a via structure is possible, and a stack via is not formed immediately below the copper foil land for joining electronic components, so that stress relaxation to the solder joint can be achieved.

  As described above, according to the first invention of the present application, in the structure for joining the build-up printed wiring board having the stacked via structure and the electronic component, the stacked via formed in at least the outermost layer of the stacked via. Since the linear expansion coefficient of the outermost interlayer insulating resin and the conductive paste is substantially equal, the stress acting between the interlayer insulating resin and the conductive paste is the same as that of the conventional interlayer insulating resin line. The expansion coefficient can be reduced, and it can be further reduced as compared with the case where the stack via is formed by copper plating. Therefore, it is possible to relieve stress on the solder that joins the copper foil land of the build-up printed wiring board and the electronic component electrode, thereby improving the reliability of the solder joint.

  Further, in the structure for joining the build-up printed wiring board having the stack via structure of the present invention and the electronic component, by drawing the pattern from the surface copper foil land of the stack via and connecting it to the copper foil land for joining the electronic component, The build-up printed wiring board structure that takes the stack via structure that does not use the copper foil land of the stack via and the copper foil land of the electronic component is possible, and the stack via is not formed immediately below the copper foil land for joining the electronic component. Stress relaxation to the solder joint is possible. Therefore, it is possible to relieve stress on the solder that joins the copper foil land of the build-up printed wiring board and the electronic component electrode, and the reliability of the solder joint can be improved.

  First, the best mode for carrying out the present invention will be described. The build-up printed wiring board of the present embodiment is produced by manufacturing a printed wiring board of a core layer by a general multilayer board manufacturing process, and sequentially forming three build-up layers on both sides with the core layer as a core. Different via holes are formed in a stacked via structure.

  The first and second stacked vias close to the core layer are made by laminating interlayer insulation resin and then drilled at the desired position with a laser, and the inside of the via hole is filled with copper by copper plating, and the entire via hole is filled with copper. Finally, a desired wiring pattern is formed by etching.

  For the third build-up layer formed on the second stack via, the third-layer interlayer insulation resin is pre-drilled to a desired position with a laser, and the conductive paste is printed in the hole by printing or dispensing. After the formation, the outermost layer copper foil affixed to the carrier tape is pressure-bonded by hot pressing to perform interlayer connection, and finally the surface layer pattern is formed by etching.

  Examples of the conductive paste used in this embodiment include silver paste and copper paste, and the linear expansion coefficient of the paste can be adjusted by the characteristics of the resin material constituting the paste.

  In addition, as the interlayer insulating resin used in the present embodiment, it is desirable to select a material whose linear expansion coefficient matches that of the conductive paste as much as possible.

(First embodiment)
Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram that best represents the features of the present invention, and is a cross-sectional view in which a CSP is mounted on a build-up printed wiring board on which stacked vias are formed.

  The build-up printed wiring board in which the stacked via of the present invention is formed is obtained by laminating an interlayer insulating resin having a copper foil bonded on one side on a patterned copper foil land 12 on the surface of the core layer, and then laminating the copper foil land 12 with a laser. A hole is made in the interlayer insulating resin layer from a position directly above. A first-stage stack via 11 is formed by copper plating in the holed portion of the insulating resin layer, and the hole is filled with copper, and a necessary pattern is formed by etching.

  Further, in the same manner, an interlayer insulating resin having a copper foil bonded on one side is laminated on the patterned copper foil land 10, and then a hole is drilled in the interlayer insulating resin layer from a position directly above the copper foil land 10 with a laser. To do. A second-stage stack via 9 is formed by copper plating at the holed portion of the insulating resin layer, and the hole is filled with copper, and a necessary pattern is formed by etching.

  On the other hand, the interlayer insulating resin sheet forming the outermost layer of the third layer of the stack via is drilled at a desired position with a laser before laminating the interlayer insulating resin sheet. After the paste is filled by the printing method, it is laminated. Furthermore, a copper foil sheet having a copper tape attached in advance on the entire surface of the carrier tape is patterned, and the patterned copper foil sheet with a carrier is laminated on the interlayer insulating resin sheet forming the third outermost layer, and then collectively. A build-up printed wiring board with a three-stage stacked via structure is completed by forming a necessary pattern by etching by heat pressing and etching.

  Here, the interlayer insulating resin sheet 4 is a prepreg material in which an epoxy resin is impregnated with glass fibers or aramid fibers, and the linear expansion coefficient in the z direction is generally 40 to 80 ppm. On the other hand, the coefficient of linear expansion of copper is 16.5 ppm, but the conductive paste used for the third level stack via in the present invention is 40 ppm, and the coefficient of linear expansion of the interlayer insulating resin sheet and the outermost layer stack via 7 is 40 ppm. Are almost equal.

  By adopting such a configuration, as a result of an accelerated test (thermal shock test) that gives a thermal stress of −25 ° C. to + 125 ° C., a solder joint that has been broken in 400 cycles in the past is broken in 1000 cycles. As a result, the bonding reliability of the solder joint was improved.

(Second embodiment)
2 and 4 are views showing a second embodiment of the present invention. FIG. 2 is a cross-sectional view in which a CSP is mounted on a build-up printed wiring board on which stacked vias are formed. FIG. 4 is a view in which the CSP is mounted. FIG.

  This embodiment is a case where the position of the stack via is further moved from directly below the component land of the CSP with respect to the first embodiment, and the linear expansion coefficient between the insulating layer 4 and the conductive paste of the stack via. Even if there is a slight difference, the stress concentration does not occur in the solder at the joint, and the rest is the same as in the first embodiment.

  Even in such a configuration, as in the first embodiment, as a result of an accelerated test (thermal shock test) applying a thermal stress of −25 ° C. to + 125 ° C., the solder joint portion has been broken in 400 cycles in the past. However, it did not break even after 1000 cycles, and the joining reliability of the solder joint was improved.

(Third embodiment)
3 and 4 are views showing a third embodiment of the present invention. FIG. 3 is a cross-sectional view in which a CSP is mounted on a build-up printed wiring board on which stacked vias are formed. FIG. 4 is a view in which the CSP is mounted. FIG.

This embodiment is a case where a third level stacked via is formed by the same copper plating as the first level and the second level with respect to the second embodiment. Even if there is a slight difference in the linear expansion coefficient, the stress concentration does not occur in the solder at the joint, and the rest is the same as in the first embodiment.
Even in such a configuration, as in the first embodiment, as a result of an accelerated test (thermal shock test) applying a thermal stress of −25 ° C. to + 125 ° C., the solder joint portion has been broken in 400 cycles in the past. However, it did not break even after 1000 cycles, and the joining reliability of the solder joint was improved.

  Although three embodiments have been described above, the present invention is not limited to this, and the number of stacked vias may be large or small. Also, the method of forming the conductive paste in the stack vias may be a method in which the vias of the build-up printed wiring board are formed by the paste.

Sectional drawing which shows the 1st Example of this invention. Sectional drawing which shows the 2nd Example of this invention. Sectional drawing which shows the 3rd Example of this invention. The top view which shows the 2nd, 3rd Example of this invention.

Explanation of symbols

1 CSP Package 2 CSP Si Chip 3 Solder Ball 4 Interlayer Insulating Resin (Glass Epoxy Material)
5 Solder resist 6 Copper foil land 7 3rd layer stacked via formed with conductive paste 8 3rd layer stacked via connection pad of 1st inner layer 9 2nd layer stacked via filled with copper plating 10 2 layers of inner layer Third stage stacked via connection pad 11 First stage stacked via filled with copper plating 12 Inner layer third layer stacked via connection pad 13 Inner layer signal line 14 CSP junction surface layer copper foil land 15 CSP junction Pattern to connect surface layer copper foil land and stack via 16 Stack via surface layer copper foil land 17 3rd layer stack via filled with copper plating

Claims (4)

  A build-up printed wiring board having a stack via structure, wherein the stack via formed in at least the outermost layer of the stack via is formed of a conductive paste. And junction structure with electronic components.   A buildup printed wiring board having a stacked via structure and a printed wiring board for connecting an electronic component, wherein the pattern is drawn from at least the outermost layer copper foil land of the stacked via and connected to the connecting land of the electronic component Bonding structure with up-printed wiring boards and electronic components.   When the surface layer copper land of the stack via according to claim 1 is also used as a connection land of an electronic component, at least the outermost layer stack via is formed of a conductive paste, and the buildup printed wiring board and the electronic component Bonding structure.   3. A structure for joining a build-up printed wiring board and an electronic component, wherein at least the outermost layer stack via of the stack via according to claim 2 is formed of a conductive paste.

Images