JP2006134915A - Semiconductor substrate, solid state imaging device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a desired potential distribution with good precision even if there is unevenness in an active layer in a substrate surface. <P>SOLUTION: The semiconductor substrate 1 includes a first semiconductor layer 121 made of a first conductivity type formed by an epitaxial growth through an SOI-Box layer 11 on an SOI support substrate 10, a second semiconductor layer 122 made of a plurality of layers in which an impurity concentration changes gradually with second conductivity type formed of epitaxial growth on the first semiconductor layer 121, and a third semiconductor layer 123 made of a first conductivity type formed of the epitaxial growth on the second semiconductor layer 122. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor substrate having a semiconductor layer formed by epitaxial growth via an insulating layer on a support substrate, a solid-state imaging device using the semiconductor substrate, and a method for manufacturing the solid-state imaging device.

  A so-called back-illuminated solid-state imaging device that provides a signal circuit on one side of a semiconductor substrate and receives light from the other side has no signal wiring such as aluminum and a wiring interlayer film on the light receiving side, so that attenuation, kicking, etc. There is a merit that the amount of received light can be increased without being affected, and a merit that a part of kicked light can enter a neighboring pixel can be prevented (for example, see Patent Document 1).

  Here, in the back-illuminated solid-state imaging device, light is incident from one surface and a signal circuit is formed on the other surface. Therefore, ion implantation is performed from the surface on which the signal circuit is formed to form a photodiode.

JP 2003-273343 A

  In such a back-illuminated solid-state imaging device, a film thickness of about 5 μm is sufficient to photoelectrically convert all light having a wavelength in the visible light region, but it is 5 μm from one surface. In order to perform ion implantation to the depth, energy in the order of MeV is required, so it takes several hours to build a photodiode on one silicon substrate, especially when a high impurity concentration is required. The problem is that time is enormous.

  Another problem is that an SOI (Silicon On Insulator) substrate is used as a silicon substrate for making a back-illuminated solid-state imaging device, but the manufacturing variation in the in-plane film thickness of the SOI substrate active layer is 10%. Degree. For this reason, ion implantation near the light incident surface also varies within the silicon substrate surface, making it impossible to create a desired potential distribution, and a decrease in blue sensitivity where photoelectric conversion occurs near the light incident surface. The dark current generated near the substrate surface cannot be prevented. This is the same problem in solid-state imaging devices other than the back-illuminated type, and it is very difficult to form a desired potential distribution in the substrate with high accuracy.

  The present invention has been made to solve such problems. That is, the present invention provides a first semiconductor layer of the first conductivity type formed by epitaxial growth through an insulating layer on a support substrate, and a second semiconductor layer formed by epitaxial growth on the first semiconductor layer. A second semiconductor layer of a plurality of layers of a conductivity type, the impurity concentration of which gradually changes, and a third semiconductor layer of a first conductivity type formed by epitaxial growth on the second semiconductor layer. It is a semiconductor substrate provided.

  In such a semiconductor substrate, since the second semiconductor layer composed of a plurality of layers whose impurity concentration gradually changes by epitaxial growth is provided, a desired potential distribution can be accurately formed by epitaxial growth.

  The present invention also provides a first semiconductor layer of the first conductivity type formed by epitaxial growth through an insulating layer on a support substrate, and a second semiconductor layer formed by epitaxial growth on the first semiconductor layer. A second semiconductor layer of a plurality of layers of a conductivity type, the impurity concentration of which gradually changes, and a third semiconductor layer of a first conductivity type formed by epitaxial growth on the second semiconductor layer. A solid-state imaging device including: a semiconductor substrate provided; a pixel portion formed on the semiconductor substrate; and a signal circuit that processes an electrical signal obtained by the pixel portion.

  In the present invention, a solid-state imaging device is formed by forming a pixel portion and a signal circuit using a semiconductor substrate including a second semiconductor layer composed of a plurality of layers whose impurity concentration gradually changes by epitaxial growth. Thus, it becomes possible to efficiently send the electrons photoelectrically converted in the pixel portion to the signal circuit with an accurate potential gradient.

  The present invention also provides a first semiconductor layer of the first conductivity type formed by epitaxial growth through an insulating layer on a support substrate, and a second semiconductor layer formed by epitaxial growth on the first semiconductor layer. A second semiconductor layer of a plurality of layers of a conductivity type, the impurity concentration of which gradually changes, and a third semiconductor layer of a first conductivity type formed by epitaxial growth on the second semiconductor layer. A method for manufacturing a solid-state imaging device, comprising: a step of forming a pixel portion in which element separation is performed using a semiconductor substrate provided; and a step of forming a signal circuit for processing an electrical signal obtained in the pixel portion.

  In the present invention, a solid-state imaging device is formed by forming a pixel portion and a signal circuit using a semiconductor substrate including a second semiconductor layer composed of a plurality of layers whose impurity concentration gradually changes by epitaxial growth. Thus, a pixel portion having an accurate potential gradient can be formed, and a solid-state imaging device capable of efficiently sending photoelectrically converted electrons to a signal circuit can be provided.

  Therefore, according to the present invention, in manufacturing a solid-state imaging device using an SOI substrate, an accurate change in impurity concentration is set by epitaxial growth. Therefore, even if there is a variation in the in-plane film thickness of the SOI substrate, a desired change is possible. It becomes possible to construct a potential distribution. As a result, it is possible to prevent a decrease in blue sensitivity where photoelectric change occurs near the light incident surface and a dark current generated near the substrate surface, and to provide a solid-state imaging device with a high yield. Become.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor substrate according to this embodiment. That is, the semiconductor substrate 1 is composed of an SOI (Silicon On Insulator) substrate, and has a first conductivity type (in FIG. 1) via an SOI / Box layer (insulating layer) 11 formed on the SOI support substrate 10. a first semiconductor layer 121 made of p-type), a second semiconductor layer 122 made of a second conductivity type (n-type in FIG. 1) formed on the first semiconductor layer 121, and a second The third semiconductor layer 123 is formed on the semiconductor layer 122 and has a first conductivity type (p-type in FIG. 1).

  The first semiconductor layer 121, the second semiconductor layer 122, and the third semiconductor layer 123 are all formed on the SOI / Box layer 11 by epitaxial growth. The second semiconductor layer 122 is composed of a plurality of layers whose impurity concentration gradually changes. In the example shown in FIG. 1, the impurity concentration is set to gradually increase from the first semiconductor layer 121 side to the third semiconductor layer 123. Thereby, it is possible to accurately control the impurity concentration of each layer and set the film thickness, and to obtain a desired potential gradient.

In the example shown in FIG. 1, as the first semiconductor layer 121 on the SOI / Box layer 11, p-type impurities are formed within a thickness of 1.0 × 10 ¹⁸ cm ⁻³ and 200 nm, and the second semiconductor layer 122 is formed. N-type impurities are 1.0 × 10 ¹⁶ cm ⁻³ , 5.0 × 10 ¹⁶ cm ⁻³ , 1.0 × 10 ¹⁷ cm ⁻³ , 2.0 × 10 ¹⁷ cm ⁻³ , 2.5 × 10 Five layers of ¹⁷ cm ⁻³ are formed with a thickness of 1 μm, and a p-type impurity is formed as a third semiconductor layer 123 with a thickness of 1.0 × 10 ¹⁸ cm ⁻³ and a thickness of several μm. The SOI active layer 12 is configured by the first semiconductor layer 121, the second semiconductor layer 122, and the third semiconductor layer 123 formed on the SOI • Box layer 11.

  When a photodiode is formed using such a semiconductor substrate 1, surface dark current is prevented from being generated in the first semiconductor layer 121 and the third semiconductor layer 123, and photoelectric conversion is performed by changing the impurity concentration in the second semiconductor layer 122. Electrons obtained by the conversion can be efficiently sent to the signal circuit.

  In the semiconductor substrate 1 of this embodiment, since the first semiconductor layer 121, the second semiconductor layer 122, and the third semiconductor layer 123 are formed by epitaxial growth, the surface of the SOI / Box layer 11 serving as a base for epitaxial growth is used. It is necessary to eliminate as many lattice defects as possible. Therefore, in order to form the SOI • Box layer 11, a technology (for example, smart cut technology) that uses an oxide substrate to be bonded and manufactured by exfoliation by heat treatment of a portion previously implanted with a high concentration of hydrogen ions is used. It is desirable to form a base for epitaxial growth of the first semiconductor layer 121 on the Box layer 11.

  The solid-state imaging device of this embodiment forms a pixel portion and a signal circuit using such a semiconductor substrate. In particular, in the back-illuminated solid-state imaging device, a signal circuit is formed on one side of the semiconductor substrate shown in FIG. Make light incident. At this time, it is necessary to apply the potential gradient as described above from the light incident surface to the signal circuit surface in order to photoelectrically convert the incident light and to collect electrons generated by the photoelectric conversion on the surface of the semiconductor substrate on the signal circuit side. is there. Further, in order to reduce the influence of dark current generated on the surface of the semiconductor substrate, it is necessary to dope a high concentration p-type impurity in the vicinity of the surface of the semiconductor substrate.

  In a conventional back-illuminated solid-state imaging device, an SOI substrate is used as the semiconductor substrate, and the signal circuit is formed on a silicon active layer of the SOI substrate. At this time, the potential gradient and the high concentration p-type impurity on the surface of the semiconductor substrate are formed in the silicon active layer by ion implantation. At this time, the silicon active layer has an in-plane manufacturing variation, and its size is about 10% of the silicon active layer. Therefore, it is impossible to uniformly implant high-concentration impurity ions on the surface of the semiconductor substrate on the light incident surface side within the surface of the semiconductor substrate, resulting from light in the blue wavelength region that is photoelectrically converted near the light incident surface. The signal from the electrons is reduced and the dark current is generated.

  In addition, since the imaging wavelength region is the visible light region among the back-illuminated solid-state imaging devices, a film thickness of about 5 μm is sufficient as the silicon active layer thickness of the semiconductor substrate in order to photoelectrically convert light from blue to red. However, in order to perform ion implantation to a depth of 5 μm, energy on the order of MeV is required, and enormous time is required. Moreover, there is a problem that more time is required in the case of ion implantation of high concentration impurities.

  Therefore, in the present embodiment, the semiconductor substrate (SOI substrate) 1 shown in FIG. 1 is used in manufacturing the backside illumination type solid-state imaging device. That is, the SOI active layer (first semiconductor layer 121 to third semiconductor layer 123) 12 is formed by epitaxial growth, and the first semiconductor layer 121 having a p-type high concentration impurity concentration on the outermost surface side of the light incident surface. And a third semiconductor layer 123 having a p-type high-concentration impurity concentration on the signal circuit formation surface side. Deploy. Thereby, the SOI active layer 12 is grown to a total of about 5 μm. By forming the SOI active layer 12 by epitaxial growth, the impurity concentration distribution can be accurately changed, and the film thickness can also be set accurately.

  In the SOI active layer 12 having a thickness of about 5 μm, a photodiode is formed on the SOI active layer 12 formed by epitaxial growth in a back-illuminated solid-state imaging device that images light having a wavelength in the visible light region. Even if this is the case, an accurate potential gradient can be realized, and it is possible to overcome the limitations of manufacturing variations in the SOI active layer 12 of the SOI substrate and the limitations of high concentration ion implantation at high energy of the ion implantation apparatus.

  Next, a method for manufacturing the solid-state imaging device according to this embodiment will be described. In the manufacturing method of the solid-state imaging device according to the present embodiment, the solid-state imaging device is manufactured using the semiconductor substrate provided with the potential gradient by the epitaxial growth described above. In the following example, the method of manufacturing the back-illuminated solid-state imaging device Will be explained.

  2 to 11 are schematic cross-sectional views for sequentially explaining the method for manufacturing the solid-state imaging device according to the present embodiment. First, as shown in FIG. 2, an SOI substrate is prepared in which an SOI support substrate 10 and an SOI active layer 12 are bonded together via an SOI / Box layer 11 made of a thermal oxide film having a thickness of about 1 μm. A photodiode 20 is formed by providing an element isolation region.

  The SOI active layer 12 corresponds to the first semiconductor layer 121 to the third semiconductor layer 123 shown in FIG. 1, and is provided with an accurate potential gradient by epitaxial growth. Therefore, the photodiode 20 formed here can sufficiently suppress the signal drop from the electrons generated from the light in the blue wavelength region photoelectrically converted in the vicinity of the light incident surface and the generation of dark current.

  A transistor 21 is formed above the photodiode 20 via an interlayer film 30 and a signal circuit 22 composed of a plurality of layers is formed. After the signal circuit 22 and the transistor 21 are formed, a passivation film 31 is formed and protected.

  Next, as shown in FIG. 3, an adhesive layer 50 is formed on the passivation film 31 of the SOI substrate on which the photodiode 20 and the signal circuit 22 are formed, and a support substrate 40 made of silicon or the like is bonded thereto. When pasted together, a state as shown in FIG. 4 is obtained.

  Next, the bonded substrates are reversed, and the SOI support substrate 10 and the SOI / Box layer 11 are removed by etching using the support substrate 40 as a base. When removed, the photodiode 20 formed in the SOI active layer 12 is exposed to the surface as shown in FIG.

  Next, as shown in FIG. 6, an antireflection film 60 is formed on the SOI active layer 12 where the photodiode 20 is exposed. The antireflection film 60 has a thickness of several nm, and a plurality of layers are formed as necessary. Thereafter, an opening 23 for extracting an electrode is formed by etching in the peripheral SOI active layer 12 and the interlayer film 30 where the photodiode 20 is formed. The opening 23 has a size of several tens of μm □ and is formed to reach the signal circuit 22 of the interlayer film 30. Usually, the depth of the opening 23 is about 5 μm.

  Next, as shown in FIG. 7, a first resist R <b> 1 is applied so as to fill the formed opening 23. This application is performed in a plurality of times as necessary. That is, since the depth of the opening 23 is about 5 μm, there is a possibility that it is not completely filled by one application. Therefore, the first resist R <b> 1 can be embedded in the opening 23 by performing the cure for each time in a plurality of times. Further, the resist applied to portions other than the opening 23 is removed by exposure and development.

  Next, an on-chip color filter CF is formed on each photodiode 20 as shown in FIG. Here, an on-chip color filter CF corresponding to R (red), G (green), and B (blue) is formed in accordance with the position of the photodiode 20. The on-chip color filter CF is formed by applying a resist in the order of each color, exposing and developing, and when applying the resist, the first resist R1 is embedded in the opening 23 in the previous step. Since the surface is flattened, it is possible to uniformly apply a resist for forming the on-chip color filter CF. The on-chip color filter CF formed by exposing and developing the resist. Can be manufactured with high accuracy.

  Next, as shown in FIG. 9, the second resist R2 is applied to the entire surface including on the on-chip color filter CF, and the upper portion of the first resist R1 is exposed and developed to be removed. This second resist R2 becomes an on-chip microlens in a later step. When the second resist R2 is applied, the opening 23 is filled with the first resist R1 and the surface is flattened in the same manner as described above, so that an on-chip microlens is formed. The resist can be applied uniformly. Therefore, an on-chip microlens using this resist can be manufactured with high accuracy. Note that when opening the second resist R2 above the first resist R1, the opening is not the same size as the first resist R1, but a slightly smaller opening.

  After the application of the second resist R2, as shown in FIG. 10, the third resist R3 is applied on the second resist R2 at a position corresponding to the on-chip color filter CF. The shape of the on-chip microlens is formed by exposing, developing and curing R3. Thereafter, the entire surface of the substrate is exposed.

  FIG. 11 shows a state after etching the entire surface of the substrate. When the entire surface is etched with the third resist R3 configured in the shape of an on-chip microlens, the shape of the on-chip microlens formed with the third resist R3 is transferred to the second resist R2, The on-chip microlens ML is formed by the two resists R2.

  Further, this etching removes the first resist R 1 through the opening provided in the second resist R 2, and the signal wiring 22 is exposed through the opening 23. That is, since the upper portion of the second resist R2 is opened above the first resist R1 at the stage shown in FIG. 9, the opening 23 is embedded together with the formation of the on-chip microlens ML by the above-described entire etching. The first resist R1 can be removed at the same time. Since the first resist R1 is removed in accordance with the size of the opening of the second resist R2, the first resist R1 remains slightly on the inner wall of the opening 23.

  The opening 23 from which the first resist R1 has been removed becomes an electrode lead-out port, and for example, electrical continuity with the signal wiring 22 can be obtained by a bonding wire. In the bonding wire connection through the opening 23, since the inner wall of the opening 23 is protected by the first resist R1, direct contact between the bonding wire and the SOI active layer can be prevented.

  In the solid-state imaging device completed by such a manufacturing method, the influence of resist application due to the large opening 23 is suppressed while being a back-illuminated type, and a highly accurate on-chip color filter CF and on-chip microlens ML are formed. It becomes possible to do.

  In addition, since the opening 23 is provided at the stage shown in FIG. 6 to expose the signal circuit 22, and the first resist R1 is buried in the opening 23, the signal circuit 22 comes into contact with a chemical solution or the like in the subsequent configuration. This can be prevented, and problems such as corrosion of the signal circuit 22 can be avoided.

It is a schematic cross section explaining the semiconductor substrate which concerns on this embodiment. It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 1). It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 2). It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 3). It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 4). FIG. 10 is a schematic cross-sectional view (No. 5) for sequentially explaining the method for manufacturing the solid-state imaging device according to the embodiment. It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 6). FIG. 10 is a schematic cross-sectional view (No. 7) for sequentially describing the method for manufacturing the solid-state imaging device according to the embodiment. FIG. 10 is a schematic cross-sectional view (No. 8) for sequentially explaining the method for manufacturing the solid-state imaging device according to the embodiment. It is a schematic cross section (the 9) explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order. It is a schematic cross section explaining the manufacturing method of the solid-state imaging device concerning this embodiment in order (the 10).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 10 ... SOI support substrate, 11 ... SOI * Box layer, 12 ... SOI active layer, 20 ... Photodiode, 21 ... Transistor, 22 ... Signal circuit, 30 ... Interlayer film, 31 ... Passivation film, 121 ... 1st semiconductor layer, 122 ... 2nd semiconductor layer, 123 ... 3rd semiconductor layer, CF ... On-chip color filter, ML ... On-chip microlens, R1 ... 1st resist, R2 ... 2nd Resist, R3 ... Third resist

Claims (6)

A first semiconductor layer of a first conductivity type formed by epitaxial growth via an insulating layer on a support substrate;
A second semiconductor layer composed of a plurality of layers of a second conductivity type formed by epitaxial growth on the first semiconductor layer, the impurity concentration of which gradually changes;
And a third semiconductor layer of the first conductivity type formed by epitaxial growth on the second semiconductor layer. 2. The semiconductor substrate according to claim 1, wherein the impurity concentration of the plurality of layers constituting the second semiconductor layer increases from the first semiconductor layer side to the third semiconductor layer side. Gradually, a first semiconductor layer having a first conductivity type formed by epitaxial growth through an insulating layer on a supporting substrate and a second conductivity type formed by epitaxial growth on the first semiconductor layer. A semiconductor substrate comprising: a second semiconductor layer composed of a plurality of layers having different impurity concentrations; and a third semiconductor layer composed of a first conductivity type formed on the second semiconductor layer by epitaxial growth; ,
A pixel portion formed on the semiconductor substrate;
A solid-state imaging device comprising: a signal circuit that processes an electrical signal obtained by the pixel portion. 4. The solid-state imaging device according to claim 3, wherein the impurity concentration of the plurality of layers constituting the second semiconductor layer increases from the first semiconductor layer side to the third semiconductor layer side. . Gradually, a first semiconductor layer having a first conductivity type formed by epitaxial growth through an insulating layer on a supporting substrate and a second conductivity type formed by epitaxial growth on the first semiconductor layer. A semiconductor substrate comprising: a second semiconductor layer comprising a plurality of layers having different impurity concentrations; and a third semiconductor layer comprising a first conductivity type formed by epitaxial growth on the second semiconductor layer. And a step of forming a pixel portion subjected to element isolation,
Forming a signal circuit for processing an electrical signal obtained by the pixel portion. A method for manufacturing a solid-state imaging device. 6. The solid-state imaging device according to claim 5, wherein the impurity concentration of the plurality of layers constituting the second semiconductor layer increases from the first semiconductor layer side to the third semiconductor layer side. Manufacturing method.

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