JP2006120727A - Method of manufacturing semiconductor device and semiconductor device obtained by it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which a prescribed cap layer can be formed uniformly in the surface of a wafer by the electroless plating method, and to provide a semiconductor device obtained by the method. <P>SOLUTION: In the semiconductor device, a thin conductive film 9 is formed on the whole surface of an interlayer insulating film 5 including the inside of a recess 5b and an electroless-plated layer 10 of a CoWP film is formed on the thin conductive film 9 by the electroless plating method. Then the portions of the electroless-plated layer 10 and thin conductive film 9 positioned on the top surface of the interlayer insulating film 5 are removed by leaving the portions of the layer 10 and film 9 positioned in the recess 5b by performing CMP treatment. Thereafter, copper wiring containing a plated copper layer, electroless-plated layer, etc., is formed. In addition, the electroless-plated layer 10 and thin conductive film 9 in the recess 5b are used as a cap layer covering the plated copper layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device obtained thereby, and more particularly to a method of manufacturing a semiconductor device in which wiring is formed by a damascene method and a semiconductor device manufactured by the manufacturing method.

  As the size of the semiconductor device is reduced as the semiconductor device is highly integrated, copper (Cu) having excellent electromigration resistance has been used as a material for the metal wiring instead of the conventional aluminum. .

  Since copper wiring cannot be patterned by etching as in the case of aluminum wiring, the copper wiring is formed by a so-called damascene method. That is, first, by performing predetermined dry etching on the interlayer insulating film formed on the semiconductor substrate, a trench portion corresponding to the wiring pattern is formed. After a barrier metal layer and a copper seed layer are formed on the surface of the interlayer insulating film including the inside of the trench portion, a copper film is formed so as to fill the trench portion by plating.

  By subjecting the copper film or the like to chemical mechanical polishing, the copper film, copper seed layer and barrier metal layer located on the upper surface of the interlayer insulating film are removed leaving the copper film in the trench portion. In this way, copper wiring is formed in the trench portion. After the copper wiring is formed, a silicon nitride film, a silicon carbide film, and the like for preventing copper diffusion are formed on the interlayer insulating film so as to cover the copper wiring.

  However, the semiconductor device thus formed has a problem that the electromigration resistance deteriorates at the interface between the copper wiring and the silicon nitride film, that is, the upper surface portion of the copper wiring. Further, there is a problem that the RC delay that delays signal transmission is increased due to the wiring resistance R of the copper wiring and the capacitance C between wirings based on the dielectric constant of the silicon nitride film or the like.

  In order to solve such problems, application of an electroless plating method has been proposed. When a plating film is selectively deposited by electroless plating on the copper wiring exposed on the surface of the flattened interlayer insulating film after chemical mechanical polishing treatment, it protrudes from the surface of the flat interlayer insulating film. A plating film is formed. If an interlayer insulating film is further formed in this state, irregularities are formed on the surface of the interlayer insulating film, which causes a displacement of the resist pattern in the subsequent photolithography process. In addition, since the electroless plating method is greatly affected by the concentration of the chemical solution and the oxidation-reduction atmosphere, the deposition state of the plating film varies depending on the density of the wiring, the area of the wiring, or the shape of the wiring.

In order to solve such a problem, Patent Document 1 proposes a method of forming a recess in the copper wiring in the groove and forming a barrier layer by electroless plating in the recess. Patent Document 2 proposes a method of forming a barrier layer having a uniform film thickness on a copper wiring by an electroless plating method.
JP 2004-15028 A Japanese Patent Application Laid-Open No. 2004-152956

  However, the conventional semiconductor device has the following problems. In a semiconductor device, the potential of a wiring varies depending on the circuit configuration where the wiring is located. Therefore, when an attempt is made to deposit the plating film on the surface of the copper wiring by the electroless plating method, a difference may occur in the deposition rate of the plating film within the wafer surface. Also, there may be a difference in the adhesion between the plating film and the copper wiring.

  The present invention has been made to solve the above-described problems, and one object thereof is to provide a method of manufacturing a semiconductor device for uniformly forming a predetermined cap layer by electroless plating in a wafer surface. Another object is to provide a semiconductor device obtained by such a manufacturing method.

  A manufacturing method of a semiconductor device according to the present invention includes the following steps. An insulating film is formed on the main surface of the semiconductor substrate. A groove having a predetermined depth is formed in the insulating film. A first conductive film containing copper is formed in the groove portion with the upper surface at a position lower than the upper surface of the insulating film. A second conductive film is formed on the entire surface of the semiconductor substrate so as to cover the surface of the insulating film and the surface of the first conductive film located in the groove. A third conductive film is formed on the surface of the second conductive film by electroless plating. Insulating the upper surface of the third conductive film by removing the third conductive film and the second conductive film located on the upper surface of the insulating film, leaving the portions of the second conductive film and the third conductive film located in the groove. A cap layer is formed at substantially the same position as the upper surface of the film.

  According to this manufacturing method, before forming the third conductive film by electroless plating, the second conductive film is formed in advance on the entire surface of the semiconductor substrate including the surface of the first conductive film. Are at the same potential. As a result, when the third conductive film is formed on the surface of the second conductive film, the third conductive film is uniform over the entire surface of the semiconductor substrate without being affected by the underlying circuit configuration and has excellent adhesion. Can be formed. As a result, such a third conductive film can form a cap layer that is uniform and excellent in adhesion within the surface of the semiconductor substrate.

  In the semiconductor device manufactured as described above, the second conductive film is left in the groove and is interposed between the first conductive film and the cap layer. Therefore, the semiconductor device according to the present invention includes the insulating film, the groove, the first conductive film, and the cap layer in addition to the second conductive film. The insulating film is formed on the main surface of the semiconductor substrate. The groove is formed in the insulating film at a predetermined depth. The first conductive film is formed in the groove, has an upper surface at a position lower than the upper surface of the insulating film, and contains copper. The second conductive film is located in the groove and is formed so as to cover the side surface in the groove and the surface of the first conductive film. The cap layer is formed on the surface of the second conductive film in the groove and has an upper surface at the same position as the upper surface of the insulating film.

Embodiment 1
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. First, as shown in FIG. 1, an insulating film 2 such as a silicon oxide film is formed on a semiconductor substrate 1. A lower wiring 3 is formed on the insulating film 2. A liner layer 4 such as a silicon carbide film (SiC) or a silicon nitride film (SiN) is formed on the insulating film 2 so as to cover the lower wiring 3 by, for example, a plasma CVD (Chemical Vapor Deposition) method. An interlayer insulating film 5 such as a silicon oxide film is formed on the liner layer 4 by, eg, CVD.

  The interlayer insulating film 5 is subjected to predetermined photolithography and etching to form a groove 5a that exposes the surface of the lower wiring 3. A barrier metal layer 6 is formed by, for example, a CVD method or a PVD (Physical Vapor Deposition) method so as to cover the surface of the interlayer insulating film 5 exposed in the trench 5a, the surface of the lower wiring 3, and the upper surface of the interlayer insulating film 5. The As the barrier metal, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), or the like is applied.

  A copper film 7 as a copper seed film is formed by CVD or PVD, for example, so as to cover the barrier metal layer 6. Next, as shown in FIG. 2, a copper plating film 8 is formed on the semiconductor substrate 1 by electrolytic plating so as to fill the groove 5a. At this time, a plating solution mainly composed of a copper sulfate solution is used as the plating solution. Next, as shown in FIG. 3, by performing chemical mechanical polishing (CMP), the copper plating film 8, the copper film 7 and the barrier metal layer 6 (copper copper) located in the groove 5a are formed. The portions of the copper plating film 8, the copper film 7 and the barrier metal layer 6 located on the upper surface of the interlayer insulating film 5 are removed while leaving the plating film 8a, the copper film 7a and the barrier metal layer 6a).

  Further, by performing the CMP process, as shown in FIG. 4, a recess 5 b is formed by making the upper surface of the copper plating film 8 a lower than the position of the upper surface of the interlayer insulating film 5. The depth of the recess 5b is about 10 nm to 100 nm, more preferably about 10 nm to 30 nm. At this time, only a portion such as the copper plating film 8 can be selectively polished without substantially polishing the interlayer insulating film 5 by using a slurry having selectivity.

  Next, as shown in FIG. 5, a conductive thin film 9 is formed on the entire surface of the interlayer insulating film 5 including the inside of the recess 5b by a CVD method or a PVD method. The conductive thin film 9 may be a material having both functions of conductivity and barrier properties. For example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or tungsten ( W) etc. can be applied. Moreover, the film thickness of the conductive thin film 9 is about 5 nm to 30 nm, and more preferably about 5 nm to 15 nm.

  Next, as shown in FIG. 6, an electroless plating layer 10 is formed on the conductive thin film 9 by an electroless plating method. That is, first, tin (Sn) is adsorbed on the surface of the conductive thin film 9, and then the tin is replaced with palladium (Pd). At this time, chloride is used as tin and palladium. Alternatively, the complexed palladium is adsorbed on the conductive thin film 9 and reduced to leave only palladium. Next, the semiconductor substrate is rotated in a predetermined processing apparatus (not shown), and for example, a plating solution mainly composed of cobalt sulfate, tungstic acid, and hypophosphorous acid is applied to the rotating semiconductor substrate (wafer). By dripping, the electroless plating layer 10 of the CoWP film is formed. The thickness of the electroless plating layer 10 may be a thickness corresponding to the depth of the recess 5b or more.

  Next, as shown in FIG. 7, the CMP process is performed to leave the portions of the electroless plating layer 10 and the conductive thin film 9 (electroless plating layer 10a, conductive thin film 9a) located in the recess 5b. Then, the electroless plating layer 10 and the conductive thin film 9 located on the upper surface of the interlayer insulating film 5 are removed. In this manner, the copper wiring 11 including the copper plating layer 8a and the electroless plating layer 10a is formed in the semiconductor device. The electroless plating layer 10a and the conductive thin film 9a serve as a cap layer 14 that covers the copper plating film 8a.

  In the semiconductor device manufacturing method described above, the following effects can be obtained as compared with the conventional manufacturing method. First, in the conventional method for manufacturing a semiconductor device, after the recess 105b is formed, the electroless plating layer 110 is formed on the surface of the copper plating film 108a exposed in the groove 105a by an electroless plating method. For this reason, the copper plating film 108a is affected by the circuit configuration, and the deposition rate of the electroless plating layer may be different in the semiconductor substrate surface. As a result, in the portion where the deposition rate is relatively low, as shown in FIG. 8, the electroless plating layer does not protrude above the upper surface of the interlayer insulating film 105, but the portion where the deposition rate is relatively high. Then, as shown in FIG. 9, the electroless plating layer may protrude from the upper surface of the interlayer insulating film 105, which may affect the subsequent photolithography process. Further, the adhesion between the electroless plating layer 110 and the copper plating film 108a may not be good.

  On the other hand, according to the manufacturing method of the semiconductor device described above, the conductive thin film 9 is formed in advance on the entire surface of the semiconductor substrate 1 including the inside of the recess 5b before the electroless plating layer 8 is formed. The entire surface of the semiconductor substrate 1 is at the same potential. As a result, when the electroless plating layer (CoWP) 10 is formed on the surface of the conductive thin film 9, it is uniform over the entire surface of the semiconductor substrate 1 (the entire surface of the conductive thin film 9) without being affected by the underlying circuit configuration. And the electroless plating layer 10 excellent in adhesive force can be formed.

  Further, when the electroless plating layer 8 is formed, the entire surface of the semiconductor substrate 1 is covered with the conductive thin film 9, so that it is affected by the degree of density of the underlying wiring, the area of the wiring, the wiring shape, and the like. The electroless plating layer 10 can be formed without this. Then, by subjecting such an electroless plating layer 10 to a polishing process, the cap layer 14 having an upper surface at the same position as the upper surface of the interlayer insulating film 5 and having excellent adhesion can be formed. In the semiconductor device manufactured in this way, the conductive thin film 9a is left in the copper wiring 11 in the groove 5a and is interposed between the copper plating layer 8a and the electroless plating layer 10a. It will have structural features.

Embodiment 2
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, similarly to the process shown in FIG. 1, as shown in FIG. 10, the surface of the interlayer insulating film 5 exposed in the trench 5a, the surface of the lower wiring 3, and the upper surface of the interlayer insulating film 5 are covered, for example. A laminated film of a tantalum nitride (TaN) layer 12 and a tantalum (Ta) layer 13 is formed as the barrier metal layer 6 by CVD or PVD (Physical Vapor Deposition). Next, a copper film 7 as a copper seed film is formed so as to cover the barrier metal layer 6 by, for example, a CVD method or a PVD method.

  Next, by performing electrolytic plating as in the step shown in FIG. 2, a copper plating film 8 is formed on the semiconductor substrate 1 so as to fill the groove 5a, as shown in FIG. Next, by performing a CMP process in the same manner as in the step shown in FIG. 3, as shown in FIG. 12, portions of the copper plating film 8, the copper film 7 and the barrier metal layer 6 located in the groove 5a (copper plating film 8a, the copper film 7a, and the barrier metal layer 6a) are removed, and the copper plating film 8, the copper film 7, and the barrier metal layer 6 located on the upper surface of the interlayer insulating film 5 are removed.

  Next, by performing etching with a predetermined chemical solution, as shown in FIG. 13, the upper surface of the copper plating film 8a is made lower than the position of the upper surface of the interlayer insulating film 5, thereby forming a recess 5b. At this time, the barrier metal layer 6 is etched together with the copper plating film 8a. However, as the chemical solution, a chemical solution in which the etching of the barrier metal layer 6 does not proceed more than the etching of the copper plating film 8a is desirable.

  When the tantalum nitride (TaN) layer 12 and the tantalum (Ta) layer 13 are applied as the barrier metal layer 6, sulfuric acid, nitric acid, or the like can be used as the chemical solution. As shown in FIG. 13, the recess 5b is etched more in the portion located on the copper plating film 8a side than the portion located on the side wall side of the groove 5a regardless of whether the barrier metal layer 6 is a single layer stack. It is desirable to form in this way.

  Next, as in the step shown in FIG. 5, a conductive thin film 9 is formed on the entire surface of the interlayer insulating film 5 including the inside of the recess 5b by CVD or PVD, as shown in FIG. Next, an electroless plating layer 10 is formed on the conductive thin film 9 by performing electroless plating as in the step shown in FIG. Next, by performing a CMP process in the same manner as in the step shown in FIG. 7, as shown in FIG. 15, portions of the electroless plating layer 10 and the conductive thin film 9 located in the recess 5b (electroless plating layer 10a, A portion of the electroless plating layer 10 and the conductive thin film 9 located on the upper surface of the interlayer insulating film 5 is removed, leaving the conductive thin film 9a), and the copper including the copper plating layer 8a, the electroless plating layer 10a, etc. A wiring 11 is formed. The electroless plating layer 10a and the conductive thin film 9a serve as a cap layer 14 that covers the copper plating film 8a.

  Even in the semiconductor device manufacturing method described above, the conductive thin film 9 is previously formed on the entire surface of the semiconductor substrate 1 including the inside of the recess 5b before the electroless plating layer 10 is formed. When the electroless plating layer 10 is formed on the surface of the conductive thin film 9 at a potential, it is uniform over the entire surface of the semiconductor substrate 1 without being affected by the underlying circuit configuration and has excellent adhesion. The electrolytic plating layer 10 can be formed. Further, the electroless plating layer 10 can be formed without being affected by the degree of density of the underlying wiring, the area of the wiring, the wiring shape, and the like. Also in the semiconductor device manufactured in this way, the conductive thin film 9 is left in the copper wiring 11 in the groove 5a and is interposed between the copper plating layer 8a and the electroless plating layer 10a.

  In the above-described manufacturing method of each semiconductor device, CoWP has been described as an example of the electroless plating layer 10 formed by the electroless plating method, but cobalt (Co), tungsten (W), and molybdenum (Mo). As long as it is an alloy made of phosphorus (P), boron (B), etc. mixed from a metal such as nickel (Ni) or chromium (Cr) and a reducing agent for electroless plating, for example, CoWB, CoMoP, CoMoB, etc. .

  The embodiments disclosed herein are illustrative in all respects and are not limited thereto. The present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG. 1 in the same embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a first cross-sectional view showing one process according to a comparative example in the embodiment. FIG. 10 is a second cross-sectional view showing one process according to a comparative example in the embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment.

Explanation of symbols

  1 semiconductor substrate, 2 insulating film, 3 lower wiring, 4 liner layer, 5 interlayer insulating film, 5a groove, 5b recess, 6 barrier metal layer, 7 copper film, 8, 8a copper plating layer, 9, 9a conductive thin film, 10, 10a Electroless plating layer, 11 Copper wiring, 12 Tantalum nitride layer, 13 Tantalum layer, 14 Cap layer.

Claims (7)

Forming an insulating film on the main surface of the semiconductor substrate;
Forming a groove having a predetermined depth in the insulating film;
Forming a first conductive film containing copper having an upper surface at a position lower than the upper surface of the insulating film in the groove,
Forming a second conductive film on the entire surface of the semiconductor substrate so as to cover the surface of the insulating film and the surface of the first conductive film located in the groove;
Forming a third conductive film on the surface of the second conductive film by electroless plating;
Removing the third conductive film and the second conductive film located on the upper surface of the insulating film, leaving the second conductive film and the third conductive film located in the groove; And a step of forming a cap layer with the upper surface of the three conductive films positioned substantially at the same position as the upper surface of the insulating film. The step of forming the first conductive film includes:
Forming a film to be the first conductive film on the insulating film so as to fill the groove,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of polishing the film to be the first conductive film. The step of forming the first conductive film includes:
Forming a film to be the first conductive film on the insulating film so as to fill the groove,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing wet etching on a film to be the first conductive film. A step of forming a fourth conductive film on the exposed surface of the groove between the step of forming the groove and the step of forming the first conductive film;
In the step of forming the first conductive film, the first conductive film is formed such that the position of the upper surface of the first conductive film is lower than the upper end of the fourth conductive film located on the opening end side of the groove. The manufacturing method of the semiconductor device in any one of Claims 1-3 including the process to form. An insulating film formed on the main surface of the semiconductor substrate;
A groove portion having a predetermined depth formed in the insulating film;
A first conductive film including copper formed in the groove and having an upper surface at a position lower than the upper surface of the insulating film;
A second conductive film formed to cover the side surface in the groove and the surface of the first conductive film;
A semiconductor device comprising: a cap layer formed on a surface of the second conductive film in the groove and having an upper surface at the same position as the upper surface of the insulating film. A third conductive film formed between a surface of the groove and the first conductive film;
The semiconductor device according to claim 5, wherein a position of an upper surface of the first conductive film is set lower than an upper end portion of the third conductive film located on an opening end side of the groove portion.   The semiconductor device according to claim 5, wherein the cap layer is a plating layer.

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