JP2006119998A - Bus information collection device, data processing apparatus and bus information collection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable an accurate observation of bus information about every bus master with respect to every slave device. <P>SOLUTION: Transactions issued to a bus are input about every bus master, bus information is measured about every bus master according to the input transactions, and the measured bus information about every bus master is stored with respect to every slave device, so that the bus information by bus master can be read for each slave device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for collecting bus information of transactions issued from a bus master.

In recent years, the circuit scale of semiconductor integrated circuits has increased with the progress of semiconductor processes, and the functions mounted on one chip have become increasingly diversified and complicated. Along with this, the control software has also been increased in scale and functionality, and it is required to efficiently develop software that can fully exhibit the performance of the hardware (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 06-131215

  While semiconductor integrated circuits can reduce costs by mounting various functions on a single chip, it is difficult to grasp the internal operating state with software development on actual machines, so debugging work and performance improvement are difficult. There is a problem that optimization work cannot be performed efficiently.

  For example, it is possible to grasp the internal state to some extent by providing a semiconductor integrated circuit with a function of outputting bus trace information and the like to the outside, but an apparatus for analyzing output data is required. Further, providing an external terminal for output and a large-capacity memory for storing output data increases the cost. Furthermore, sufficient information cannot be output when the operating frequency increases.

  Also, when multiple bus masters and multiple slave devices are connected to a single bus, it is not possible to fully grasp the status of individual bus masters and slave devices by simply measuring the bus usage rate. There's a problem.

  The present invention has been made to solve the above-described problems, and an object thereof is to accurately grasp bus information for each bus master for each slave device.

  The present invention provides an input means for inputting a transaction issued to a bus for each bus master, a measuring means for measuring bus information for each bus master based on a transaction input by the input means, and a measurement by the measuring means. Storage means for storing the bus information for each bus master for each slave device, and the bus information for each bus master can be read for each slave device.

  Further, the present invention provides an input step for inputting a transaction issued to a bus for each bus master, a measurement step for measuring bus information for each bus master based on the transaction input in the input step, and the measurement step Storing the bus information for each bus master measured in step S1 for each slave device, so that the bus information for each bus master can be read for each slave device.

  According to the present invention, since bus information for each bus master can be accurately grasped for each slave device, debugging work, performance analysis work, optimization work, etc. in software development can be performed efficiently.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a bus information collection circuit according to the first embodiment. As shown in FIG. 1, the bus information collecting circuit 1 includes a register interface (I / F) 2, a register access control unit 3, a bus information measuring unit 4 of the bus master A, and a bus information measuring unit 5 of the bus master B. Has been.

  FIG. 1 shows an example in which there are two bus masters, bus master A and bus master B, but the number of bus masters is not limited to this, and there are three bus masters. Also good. In that case, the bus information measuring unit may be configured to correspond to the three bus masters.

  The register interface 2 is an input / output unit that reads / writes the registers of the bus information measuring unit 4 and the bus information measuring unit 5 so that a CPU (not shown) controls the operation of the bus information collecting circuit 1 and reads the measured information. It is.

  The register access control unit 3 decodes an address value in CPU access, and controls reading / writing of the registers of the bus information measurement unit 4 and the bus information measurement unit 5 mapped to a predetermined address.

  The bus information measuring unit 4 is a block for measuring bus information of the bus master A, and is a slave device that is subject to transfer direction and transfer target information on the number of transactions issued by the bus master A on the bus and delay time (latency). Measure separately.

  Further, the bus information measurement unit 4 includes a bus operation information input unit 10, a register 12, an operation control unit 13, a transaction frequency measurement unit 14, a latency measurement unit 15, a maximum latency detection unit 16, and a minimum latency detection unit 17. Yes.

  The bus operation information input unit 10 receives information necessary for grasping the contents of a transaction issued on the bus, a transfer request signal from the measurement target bus master, a transfer direction signal indicating read / write, and a bus A transfer permission signal from the arbiter that performs arbitration, a slave device identification signal from the decoder that identifies the slave device, a transfer completion signal from the slave device, and the like are input.

  The register 12 includes a group of registers, and is used as an interface for controlling the bus information measuring unit 4 and reading the measured information. Here, the inside of the register 12 will be described in detail.

  FIG. 2 is a block diagram illustrating a detailed configuration of the register 12 according to the first embodiment. As shown in FIG. 2, the register 12 includes a control register 20 that sets the operation mode and operation start / stop of the bus information measuring unit 4, a bus information register 21 that holds information of a read transaction for the slave device A, and a slave device A. The bus information register 22 holds information on the write transaction for the slave device B, the bus information register 23 holds information on the read transaction for the slave device B, and the bus information register 24 holds the information on the write transaction for the slave device B.

  Note that FIG. 2 shows an example in which there are two slave devices, slave device A and slave device B, but the number of slave devices is not limited to this, and the read transaction depends on the number of slave devices. It is only necessary to configure a bus information register for use and write transactions.

  Each of the bus information registers 21 to 24 of the register 12 further includes a transaction number register 30 that holds the number of transactions, a latency accumulation register 31 that holds a cumulative value of latency (unit is clock cycle), and a maximum value of latency (unit is clock cycle). ) And a latency minimum value register 33 for holding a latency minimum value (unit: clock cycle).

  Here, referring back to FIG. 1, the operation control unit 13 of the bus information measuring unit 4 performs control such as initialization of each block and start / stop of operation in the bus information measuring unit 4 in accordance with the value set in the control register 20. .

  The transaction count measurement unit 14 measures the number of transactions for each transfer direction and for each target slave device in accordance with the input from the bus operation information input unit 10, and stores the measured value in the transaction count register 30 of the register 12.

  The latency measuring unit 15 measures transaction latency accumulation for each transfer direction and target slave device according to the input from the bus operation information input unit 10, and stores the measured value in the latency accumulation register 31 of the register 12. Further, the latency in each transaction is notified to the maximum latency detecting unit 16 and the minimum latency detecting unit 17.

  The maximum latency detection unit 16 detects the maximum latency of a transaction for each transfer direction and each target slave device according to the input from the bus operation information input unit 10. When the latency measurement value is notified from the latency measurement unit 15, it is compared with the value of the latency maximum value register 32 of the register 12, and when the latency measurement value notified from the latency measurement unit 15 is large, the latency maximum is obtained. The value register 32 is updated.

  The minimum latency detection unit 17 detects the minimum latency of a transaction for each transfer direction and for each target slave device according to the input from the bus operation information input unit 10. When the latency measurement value is notified from the latency measurement unit 15, it is compared with the value of the latency minimum value register 33 of the register 12, and when the latency measurement value notified from the latency measurement unit 15 is small, the latency minimum The value register 33 is updated.

  The bus information measuring unit 5 is a block that measures the bus information of the bus master B, and the configuration thereof is the same as the configuration of the bus information measuring unit 4. In the following description, the bus information measuring unit 5 is the same as the bus information measuring unit 4 except that the target bus master is different from the description of the bus information measuring unit 4, and the description thereof is omitted.

  Next, the operation of the bus information collection circuit 1 according to the first embodiment will be described with reference to FIG. FIG. 3 is a timing chart for explaining the operation of the bus information collecting circuit 1. Here, the operation of a transaction issued to the bus by the bus master A is shown, “clk” is a clock cycle, “request” is a transfer request signal, “grant” is a transfer permission signal, “address” is an address of a transfer target area, “ “rw” is the transfer direction (read low, write high), “done” is the transfer completion signal, “rdata” is the read data from the transfer target area, “wdata” is the write data to the transfer target area, “slave” Indicates the identification value of the slave device to be transferred.

  First, when a CPU (not shown) sets operation start to the control register 20, the bus information measurement unit 4 initializes the register 12, and starts operations of the transaction count measurement unit 14 and the latency measurement unit 15. To do. As initialization of the register 12, the transaction count register 30, the latency accumulation register 31, and the latency maximum value register 32 of each of the bus information registers 21 to 24 are set to “0”, and the latency minimum value register 32 is a settable maximum value. For example, the value is set to 65535 in the case of a 16-bit configuration.

  FIG. 3 shows a transaction in which the bus master A writes data (wdata0) to the address A0 area of the slave device A during 3 to 9 clock cycles. Specifically, in the third clock cycle, when the bus master A asserts the request signal and the transaction is started, the latency measuring unit 15 starts measuring the latency in the transaction. When the grant signal is asserted from the arbiter in the fifth clock cycle, the bus master A changes the address signal to A0, the rw signal to High, and the wdata signal to wdata0 from the next six clock cycles.

  In the sixth clock cycle, when the bus master A changes the address signal, the decoder decodes the address A0 and changes the slave signal to an identification value indicating the slave device A. Thereafter, when the done signal is asserted in the ninth clock cycle, the transfer is completed, and the latency measuring unit 15 finishes the latency measurement (latency is 7 clock cycles).

  Since this transaction is writing to the slave device A, the value of the bus information register 22 of the register 12 is updated. First, the transaction count measurement unit 14 adds “1” to the value of the transaction count register 30. The latency measuring unit 15 adds the measured latency (7 clock cycles) to the latency accumulation register 31. Further, the maximum latency detecting unit 16 compares the latency value (7 clock cycles) measured by the latency measuring unit 15 with the value of the latency maximum value register 32 (0 clock cycle), and the measured value of the latency measuring unit 15 is large. Therefore, the value of the latency maximum value register 32 is updated to 7 clock cycles. The minimum latency detecting unit 17 compares the latency value (7 clock cycles) measured by the latency measuring unit 15 with the value of the latency minimum value register 33 (maximum clock cycle that can be set), and the latency measuring unit 15 measures the latency. Since the value is small, the value of the latency minimum value register 33 is updated to 7 clock cycles.

  During the 14 to 23 clock cycles shown in FIG. 3, the bus master A shows a transaction for reading the data of rdata1 from the address A1 area of the slave device B. Specifically, in the 14th clock cycle, when the bus master A asserts the request signal and the transaction is started, the latency measuring unit 15 starts measuring the latency in the transaction. When the grant signal is asserted from the arbiter in the 15th clock cycle, the bus master A changes the address signal to A1 and the rw signal to Low (read) from the next 16th clock cycle.

  In the 16th clock cycle, when the bus master A changes the address signal, the decoder decodes the address A1 and changes the slave signal to an identification value indicating the slave device B. Thereafter, when the done signal is asserted together with the change of the rdata signal in the 23rd clock cycle, the transfer is completed, and the latency measuring unit 15 finishes the latency measurement (the latency is 10 clock cycles).

  Since this transaction is a read to the slave device B, the value of the bus information register 23 of the register 12 is updated. First, the transaction count measurement unit 14 adds “1” to the value of the transaction count register 30. The latency measuring unit 15 adds the measured latency (10 clock cycles) to the latency accumulation register 31. Further, the maximum latency detecting unit 16 compares the latency value (10 clock cycles) measured by the latency measuring unit 15 with the value of the latency maximum value register 32 (0 clock cycle), and the measured value of the latency measuring unit 15 is large. Therefore, the value of the latency maximum value register 32 is updated to 10 clock cycles. The minimum latency detection unit 17 compares the latency value (10 clock cycles) measured by the latency measurement unit 15 with the value of the latency minimum value register 33 (maximum clock cycle that can be set), and the latency measurement unit 15 measures the latency. Since the value is small, the value of the latency minimum value register 33 is updated to 10 clock cycles.

  As described above, every time the bus master A issues a transaction, the bus information measuring unit 4 operates, and the transaction count register 30 and the latency accumulation register 31 provided for each transfer direction (read / write) and slave device. Then, the values of the latency maximum value register 32 and the latency minimum value register 33 are updated.

  The information held in the register 12 of the bus information measuring unit 4 and the bus information measuring unit 5 can be read out by the CPU at any time, and processing such as outputting to the outside using a communication device can be performed.

  Next, a case where a transaction issued by a predetermined bus master is a burst transfer in which a plurality of data transfers are performed in one transaction will be described with reference to FIG.

  FIG. 4 is a timing chart for explaining the operation in burst transfer. In FIG. 4, the burst signal indicates the number of times of data transfer, the stb signal indicates the strobe signal of the transfer data, and the rest is the same as FIG.

  During the 3 to 9 clock cycles shown in FIG. 4, data write (wd0, wd1) is performed twice (burst signal is 2) to the area from address A0. During 14 to 23 clock cycles, data reading (rd0, rd1, rd2, rd3) is performed four times (burst signal is 4) for the area from address A1. Also in these burst transfers, the number of transactions, the accumulated latency, the maximum value, and the minimum value are measured in the same manner as described with reference to FIG.

  Needless to say, when the burst signal is “1”, it is exactly the same as the single transfer.

  In addition, when the transaction is only single transfer, the transfer data amount can be obtained by converting the number of transactions into data, but when burst transfer is mixed, the transfer data amount cannot be obtained only by the transaction number. Therefore, by providing a unit for measuring the number of data transfers from the burst signal in the bus information measuring unit 4 and a register for newly storing the number of data transfers in the register 12, a transfer data amount can be obtained even when burst transfers are mixed. Can do.

  In the above description, the latency measuring unit 15 measures the latency from when the bus master A issues a transfer request to when the transfer is completed, but obtains transfer permission from the arbiter after the bus master A issues the transfer request. It may be configured to measure the latency up to. Also in this case, the number of transactions, the accumulated latency, the maximum value, and the minimum value are measured in the same manner as described above. By doing so, latency information in the arbitration of the bus can be obtained, and it can be understood how much contention for the bus use right has occurred between the bus masters.

  For example, in the transaction between 3 and 9 clock cycles shown in FIG. 3, the latency measured by the latency measuring unit 15 is 2 clock cycles from when the request signal is asserted to when the grant signal is asserted. Here, if no contention occurs on the bus, assuming that the grant signal is asserted in one clock cycle, the bus contention has occurred for one clock cycle. On the other hand, in a transaction between 14 and 23 clock cycles, the latency measured by the latency measuring unit 15 is one clock cycle, and no contention occurs on the bus.

  It is the control register 20 that selects whether to measure the time from when a transfer request is issued until the transfer is completed or from when the transfer request is issued until the transfer permission is obtained as a latency measurement target. It may be possible to set exclusively. Alternatively, a new register may be added to the register 12 so that both values can be measured simultaneously.

  In the above description, the latency measuring unit 15 measures the latency from when the bus master A issues a transfer request until the transfer is completed, but the transfer is completed after the bus master A obtains the transfer permission from the arbiter. It may be configured to measure the latency up to. Also in this case, the number of transactions, the accumulated latency, the maximum value, and the minimum value are measured in the same manner as described above. By doing so, latency information in the slave device can be obtained, and it can be grasped whether the slave device can be controlled efficiently.

  For example, in FIG. 3, in the transaction between 3 and 9 clock cycles, the latency measured by the latency measuring unit 15 is 5 clock cycles from when the grant signal is asserted to when the done signal is asserted. Here, assuming that the shortest response time of the slave device is 5 clock cycles, the shortest response is obtained without any problem in the slave device. On the other hand, in the transaction between 14 and 23 clock cycles, the latency measured by the latency measuring unit 15 is 9 clock cycles, and it can be seen that a factor that delays the response occurs in the slave device.

  As a latency measurement target, it is exclusive in the control register 20 to select whether to measure from when a transfer request is issued until the transfer is completed, or when the transfer permission is acquired and until the transfer is completed. It may be possible to set to. Alternatively, a new register may be added to the register 12 so that both values can be measured simultaneously.

  In the above description, the example is applied when there are two bus masters and two slave devices, respectively. However, it can be similarly applied by increasing or decreasing each register in the bus information measuring unit.

  In the above description, the transaction is distinguished according to the transfer direction. However, when only one information of reading and writing is necessary, the distinction is not performed, and the register in the bus information measuring unit is reduced to one half. May be.

  When a specific bus master accesses only a specific slave device, the bus information measuring unit for the bus master may have a register only for the target slave device.

  According to the first embodiment, in a system configuration in which a plurality of bus masters and a plurality of slave devices exist, bus information can be collected for each bus master and each slave device.

  Next, Embodiment 2 according to the present invention will be described in detail with reference to the drawings. In the second embodiment, as a data processing apparatus connected to a host computer, a printer using a bus information collection circuit is taken as an example to improve the efficiency of debugging work, performance analysis work, and optimization work in software development for controlling the printer. The case will be described.

  FIG. 5 is a block diagram illustrating a configuration example of a printer using a bus information collection circuit. As shown in FIG. 5, a personal computer (PC) 40 and a printer 41 are connected by a USB cable. This USB is a high-speed serial bus communication standard, and is widely spread as a device for connecting various devices.

  The printer 41 includes a semiconductor integrated circuit 42 including the bus information collecting circuit described in the first embodiment, a memory card 43 connected to a memory card slot and the like, and a nonvolatile ROM 44 in which a control program for the semiconductor integrated circuit 42 is stored. A DRAM 45 used as a work memory area when the semiconductor integrated circuit 42 operates and a printing unit 46 such as a print head for printing are mounted.

  The semiconductor integrated circuit 42 shown in FIG. 5 is issued on the system bus, the CPU 51 that controls the entire printer 41, the ROM controller 52 that controls the reading of data to the ROM 44, the arbiter 53 that arbitrates the system bus 64, and the like. A decoder 54 that decodes the address of a transaction to be executed and identifies a target slave device, a peripheral circuit 55 that performs interrupt and timer control, a DRAM controller 56 that performs data read / write control on the DRAM 45, and a bus master function. A printing controller 57 for controlling the printing unit 46, a USB device controller 58 for connecting to the PC 40, a card controller 59 for controlling data transfer to the memory card 43, a DMA controller 60 for the card controller 59, in front A bus information collecting unit 61 corresponding to the bus information collecting circuit 1, a print image processing unit 62 having a bus master function and performing print image processing to generate print data; It is comprised with SRAM63 used as a work area.

  Here, there are a total of four bus masters connected to the system bus 64: the CPU 51, the print controller 57, the DMA controller 60, and the print image processing unit 62. As the slave device, four address spaces are allocated: a ROM area via the ROM controller 52, a DRAM area via the DRAM controller 56, an SRAM area of the SRAM 63, and a register area of each controller.

  The CPU 51, the print controller 57, and the print image processing unit 62 issue a transaction by mixing single transfer and burst transfer on the system bus 64.

  The arbiter 53 arbitrates the system bus usage right according to the priority of each bus master set by the CPU 51.

  The bus information collection unit 61 according to the second embodiment collects bus information of the CPU 51, the print controller 57, and the print image processing unit 62, and transfers the number of transactions and the number of data transfers, and the transfer of the ROM area and the SRAM area to the CPU 51. Latency from issuing a request to obtaining transfer permission, latency from issuing a transfer request for the DRAM area to the print controller 57 to completing transfer, transferring the DRAM area to the print image processing unit 62 A configuration is adopted in which the latency from when permission is obtained until transfer is completed is collected. The bus information collection unit 61 includes a transfer request signal from the CPU 51, print controller 57, and print image processing unit 62, a transfer direction signal indicating read / write and a transfer count signal, a transfer permission signal from the arbiter 53, and a decoder 54. A slave device identification signal and a transfer completion signal from each slave device are input.

  Next, with regard to debugging work, performance analysis work, and optimization work in software development of the printer 41, software development in which an image file compressed and stored in the memory card 43 is printed by the printing unit 46 will be described as an example.

  In the printing process, the following operation is performed in the semiconductor integrated circuit 42. The CPU 51 secures a buffer area for storing the image file on the DRAM 45, a buffer area for storing the expansion processing result of the image file, and a buffer area for storing the print data. The image file stored in the memory card 43 is written into the DRAM 45 by the card controller 59 and the DMA controller 60. Then, the CPU 51 reads the image file written in the DRAM 45, performs an expansion process, and writes the result in the DRAM 45.

  When the writing to the DRAM 45 is completed, the print image processing unit 62 reads the expansion processing result from the DRAM 45, performs the print image processing, and writes the print data to the DRAM 45. Then, the print controller 57 reads the print data from the DRAM 45 and transfers the print data to the print unit 46.

  Since these processes sequentially operate in parallel in units of a predetermined data size, a large amount of reading / writing from / to the DRAM 45 from each bus master occurs on the system bus 64. In addition, since a large load is imposed on the CPU 51 due to interrupt processing and image processing, interrupt processing and decompression processing programs and frequently referenced data are arranged on the SRAM 63 that operates at a higher speed than the ROM 44 and the DRAM 45, and processing is performed. Speeding up has been done.

  In the debugging work, performance analysis work, and optimization work in the software development of the above-described operation, the printer 41 is actually operated, and the bus information collection unit 61 collects bus information of the CPU 51, the print controller 57, and the print image processing unit 62. . The collected data is read by the CPU 51 from the register of the bus information collection unit 61, transferred to the PC 40 using a communication device such as the USB device controller 58, and displayed.

  For example, assume that the following data is obtained as bus information for the CPU 51.

[Read from ROM area]
Number of transactions: 1,257,349
Number of data transfers: 5,028,531
Latency accumulation: 25,435,834 clock cycles Latency maximum value: 134 clock cycles Latency minimum value: 1 clock cycle
[Read from SRAM area]
Number of transactions: 5,241,746
Number of data transfers: 20,966,984
Latency accumulation: 134,958,327 clock cycles Latency maximum value: 128 clock cycles Latency minimum value: 1 clock cycle The above latency measures the arbitration latency of the system bus 64 (from when a transfer request is issued until transfer permission is obtained) Thus, it can be seen that it takes about 20 clock cycles for reading from the ROM 44 area per transaction and about 26 clock cycles for reading from the SRAM 63 area. Further, assuming that the arbitration latency in the state where no competition occurs in the system bus 64 is one clock cycle, the arbitration latency of the CPU 51 is increased by 20 times or more due to the competition of the system bus 64, which affects the operation speed. I understand that.

  Therefore, in order to increase the operating speed of the CPU 51, it is sufficient to increase the priority of the CPU 51 in the arbiter 53 so that the system bus can be used preferentially even in a competitive state.

  Further, it is assumed that the following data is obtained as bus information for the print controller 57.

[Read from DRAM area]
Number of transactions: 105,453,210
Number of data transfers: 442,903,482 times
Latency accumulation: 3,921,400,639 clock cycles Latency maximum value: 45 clock cycles Latency minimum value: 30 clock cycles The above latency is measured from when a transfer request is issued until the transfer is completed. It can be seen that reading from the DRAM area per transaction takes about 37 clock cycles. If there is a restriction that the data transfer of 100,000 times to the printing unit 46 must be completed within 2 million clock cycles, the number of transactions necessary for the data transfer of 100,000 times is about 23,810 times. Is executed at the maximum latency, it is understood that the print controller 57 is operating at about 1.07 million clock cycles and about twice the performance of the constraint.

  Further, it is assumed that the following data is obtained as bus information for the print image processing unit 62.

[Read from DRAM area]
Number of transactions: 23,647,515
Number of data transfers: 47,293,103 times
Latency accumulation: 761,449,983 clock cycles Latency maximum value: 35 clock cycles Latency minimum value: 29 clock cycles
[Write to DRAM area]
Number of transactions: 105,453,210
Number of data transfers: 442,903,482 times
Latency accumulation: 2,847, 236, 670 clock cycles Latency maximum value: 32 clock cycles Latency minimum value: 26 clock cycles The above latency is the latency measured in the slave device (from transfer permission to transfer completion) Thus, it can be seen that reading from the DRAM 45 area per transaction takes about 32 clock cycles and writing to the DRAM 45 area takes about 27 clock cycles.

  As described above, in the DRAM 45, the read and write latencies are 29 and 26 clock cycles in the page hit state in which the same page is continuously accessed, and the read and write latencies are 35 and 30 in the page miss state in which different pages are accessed. Assuming that there are 32 clock cycles, it can be seen that when the print image processing unit 62 reads data from the DRAM 45 area, the ratio of the page miss state is high and efficient reading is not performed. Therefore, in order to efficiently access the DRAM 45 area, it is only necessary to adjust various buffer areas secured in the DRAM 45 area so that a page miss state does not occur as much as possible.

  As described above, according to the embodiment, in a configuration in which a plurality of bus masters and a plurality of slave devices exist, bus information is collected for each bus master and each slave device, and software development is performed based on the information. Debugging work, performance analysis work, and optimization work can be performed efficiently.

  In the second embodiment, the printer is described as an example of the data processing apparatus using the bus information collecting circuit according to the present invention. However, the present invention is not limited to this, and a plurality of bus masters and a plurality of slave devices are included. In the existing configuration, any device that collects bus information for each bus master and each slave device can be applied to other devices.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  Another object of the present invention is to supply a recording medium in which a program code of software realizing the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores it in the recording medium. Needless to say, this can also be achieved by reading and executing the programmed program code.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

FIG. 3 is a block diagram illustrating a configuration example of a bus information collection circuit according to the first embodiment. 3 is a block diagram illustrating a detailed configuration of a register 12 in Embodiment 1. FIG. 3 is a timing chart for explaining the operation of the bus information collecting circuit 1; 6 is a timing chart for explaining an operation in burst transfer. FIG. 3 is a block diagram illustrating a configuration example of a printer using a bus information collection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bus information collection circuit 2 Register interface 3 Register access control part 4 Bus information measurement part 5 Bus information measurement part 10 Bus operation information input part 12 Register 13 Operation control part 14 Transaction frequency measurement part 15 Latency measurement part 16 Maximum latency detection part 17 Minimum latency detector 20 Control register 21 Bus information register 22 Bus information register 23 Bus information register 24 Bus information register 30 Transaction count register 31 Latency accumulation register 32 Latency maximum value register 33 Latency minimum value register 40 PC
41 Printer 42 Semiconductor Integrated Circuit 43 Memory Card 44 ROM
45 DRAM
46 Printing part 51 CPU
52 ROM controller 53 Arbiter 54 Decoder 55 Peripheral circuit 56 DRAM controller 57 Print controller 58 USB device controller 59 Card controller 60 DMA controller 62 Print image processing unit 63 SRAM
64 System bus

Claims (10)

An input means for inputting a transaction issued to the bus for each bus master;
Measuring means for measuring bus information for each bus master based on the transaction input by the input means;
Storing means for storing for each slave device the bus information for each bus master measured by the measuring means,
A bus information collecting apparatus, wherein the bus information for each bus master can be read for each slave device.   2. The bus information collecting apparatus according to claim 1, wherein the measuring unit measures at least the number of transactions and a delay time as the bus information.   3. The bus information collecting apparatus according to claim 2, wherein the delay time is a delay time from a transfer request start by the bus master to a transfer completion in a slave device.   3. The bus information collecting apparatus according to claim 2, wherein the delay time is a delay time from a transfer request start by the bus master to a transfer start in a slave device.   3. The bus information collecting apparatus according to claim 2, wherein the delay time is a delay time from the start of transfer by the slave device to the completion of transfer at the slave device.   The delay time includes a delay time from a transfer request start by the bus master to a transfer completion at the slave device, a delay time from a transfer request start by the bus master to a transfer start at the slave device, and a transfer by the slave device. 3. The bus information collecting apparatus according to claim 2, wherein any one of a delay time from a start to a transfer completion in a slave device can be switched for each measurement target bus master.   A data processing apparatus comprising the bus information collecting apparatus according to claim 1. An input process for inputting a transaction issued to the bus for each bus master;
A measurement step of measuring bus information for each bus master based on the transaction input in the input step;
Storing the bus information for each bus master measured in the measurement step for each slave device,
A bus information collecting method, wherein the bus information for each bus master can be read for each slave device.   A program for causing a computer to function as each means of the bus information collecting device according to claim 1.   A computer-readable recording medium on which the program according to claim 9 is recorded.

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