JP2006119275A - Method for manufacturing exposure mask, exposure mask and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease a mask production period or a total device production (trial production) period including the production of a mask for a multi-step common mask. <P>SOLUTION: The entire exposure steps A to Y are assigned to each exposure mask (step Sm1) so as to unify the number of patterns (levels) per unit area in the entire exposure masks M1 to M5 necessary for the manufacture of a semiconductor device; and at least either data processing (step Sm2) or mask exposure (step Sm3) is carried out in a plurality of exposure steps as a unit assigned to each exposure mask as a unit. Thereby, data processing time and/or mask exposure time is equalized for entire masks M1 to M5, which prevents wasteful time such as waiting for completion of a mask in the manufacture of a device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, different exposure process patterns are arranged corresponding to a plurality of exposure processes assigned in an arbitrary combination from all exposure processes necessary for manufacturing one semiconductor device, and are shared by the different exposure processes. The present invention relates to a mask manufacturing method, the exposure mask, and a semiconductor device manufacturing method.

  In recent years, system LSIs have become mainstream in semiconductor devices incorporated in electronic equipment. The system LSI is obtained by integrating the main functions of an electronic device into a one-chip semiconductor LSI using a fine semiconductor manufacturing technique.

  In the development of system LSI, a plurality of wafers that have been manufactured using wafer process technologies (CMOS, bipolar, high-frequency applications, high-voltage applications, etc.) that have been used to maximize the performance of each functional block. IC is made into one chip. In this one-chip manufacturing, the wafer process is being shared to some extent, but there is a limit to complete sharing. As a result, an increase in the number of steps in the wafer process, a photomask (hereinafter referred to as “exposure mask”). ”Or simply“ mask ”).

  Unlike general-purpose products, custom or semi-custom products such as the above-mentioned system LSI or gate array tend to be a small variety of products, and the ratio of exposure mask price to the production cost per single chip is high. Reduction of mask price is an important issue.

As one of the measures to reduce the exposure mask price, an exposure mask in which different patterns are arranged on one exposure mask so as to be shared by a plurality of exposure processes has been proposed (for example, see Patent Document 1).
Hereinafter, such an exposure mask is particularly referred to as a “multi-process shared mask”. The multi-process shared mask is based on the premise that it is shared by a plurality of processes. By arranging a mask pattern for a plurality of exposure processes on one mask and reducing the total number of masks, the material cost of the exposure mask and The manufacturing cost is reduced.

In a normal exposure mask, one mask has any one of mask patterns for an exposure process in a semiconductor wafer process, such as an element isolation layer pattern, a transistor gate pattern, and a wiring pattern.
On the other hand, in a multi-process shared exposure mask, a plurality of types of mask patterns are arranged in a combination of a plurality of different exposure processes, for example, an element isolation layer pattern, a transistor gate pattern, and a contact hole pattern.

When a mask is procured for a total of three exposure processes, for example, an element isolation layer pattern, a transistor gate pattern, and a contact hole pattern, as in this example, normally, each exposure mask is one, and a total of three exposure masks. The mask price for a total of 3 masks is included in the production cost. On the other hand, if three exposure process patterns are combined and arranged on a single mask in a multi-process shared mask, the total mask price can be reduced, so the cost of about two masks can be reduced. it can.
Japanese Utility Model Publication No. 05-008935

  The above-mentioned Patent Document 1 does not describe a specific pattern arrangement reference, that is, a reference regarding a combination of patterns arranged on one mask.

By the way, in general-purpose semiconductor devices, once a device is designed and a required number of masks are manufactured, the amount of wafer input is determined in consideration of the demand in the device market. Yield, etc. are the main factors (elements) for bringing the right amount of product to market at the right time.
On the other hand, in the manufacture of a small variety of semiconductor devices, it is more strongly required than a general-purpose product how quickly the device can be introduced into a prototype or mass production line of an electrical product incorporating the device. . For this reason, in the manufacture of a small variety of semiconductor devices, in addition to the above-described elements, it is an important factor for timely product shipment to shorten the period of device design, mask fabrication, and the like.

  The problem to be solved by the present invention is to manufacture a total number of devices (or prototypes) including the mask fabrication period and mask fabrication in the number of exposure masks (multi-process shared mask) necessary for the fabrication of one semiconductor device. A new criterion for the combination of patterns to be arranged on each mask, which is appropriate from the viewpoint of shortening the period, is proposed, and an exposure mask manufacturing method using the criterion, the exposure mask, and the exposure mask manufacturing It is to provide a method of manufacturing a semiconductor device including steps.

  In the exposure mask manufacturing method according to the present invention, different exposure process patterns are arranged corresponding to a plurality of exposure processes assigned in an arbitrary combination from all the exposure processes necessary for manufacturing one semiconductor device. A method of manufacturing an exposure mask shared by an exposure process, wherein all the exposure processes are performed for each exposure mask with the goal of aligning the number of patterns per unit area in all exposure masks necessary for manufacturing the semiconductor device. An exposure process assigning step, a data processing step for creating exposure mask data, and a mask exposure step for transferring a pattern based on the data to a photosensitive layer of a mask substrate. The plurality of exposure processes in which at least one of the processing and the mask exposure is assigned to each exposure mask are simply performed. To run as.

  A method of manufacturing a semiconductor device according to the present invention is an exposure mask in which a plurality of patterns are arranged in each mask in an arbitrary combination from patterns necessary for forming a semiconductor device on a semiconductor substrate, and all exposure masks are produced in advance. A method for manufacturing a semiconductor device, comprising: a manufacturing step; and a device forming step of forming a semiconductor device using all the exposure masks in the order in which the necessary patterns are formed. , With the goal of aligning the number of patterns per unit area in all the exposure masks, assigning all exposure processes necessary for forming the semiconductor device to each mask, and assigning the exposure mask data Data processing steps to be created and a pattern based on the data on the photosensitive layer of the mask substrate Includes a step of mask exposure to copy, the, at least one of the steps of the mask exposure and the data processing, executes the plurality of exposure processes assigned for each of the exposure mask as a unit.

  In the present invention, preferably, in the assigning step of the exposure process, the patterns of all the exposure processes are classified into a plurality of levels according to the number of patterns per unit area, and a combination of the levels corresponds to all the exposure masks. With the goal of being the same, the exposure process is assigned to each exposure mask.

  In the present invention, preferably, in the assigning step of the exposure step, when the number of patterns per unit area is a first reference, the second reference having the next highest priority is used in the device manufacturing of each pattern. As described above, the exposure process is assigned to each exposure mask.

  According to such a method for manufacturing an exposure mask and a method for manufacturing a semiconductor device, different patterns corresponding to a plurality of exposure processes are arranged on all the exposure masks. At this time, the number of patterns per unit area is used as a reference for assigning a plurality of exposure processes to each exposure mask, and the target is to make this number of patterns uniform for all exposure masks. Therefore, all the exposure masks after the exposure process is assigned have almost the same number of patterns per unit area.

In the present invention, a plurality of exposure processes in which at least one of data processing and mask exposure (pattern transfer to the photosensitive layer on the mask substrate) for producing such an exposure mask is assigned to each exposure mask are performed. Run as a unit. For example, in data processing for producing an exposure mask, the processing is executed in units of data relating to patterns for a plurality of exposure steps assigned to the mask. Alternatively, mask exposure, that is, the pattern is transferred to the photosensitive layer on the mask substrate in units of patterns for a plurality of exposure steps assigned to the exposure mask.
In such data processing and mask exposure, data processing time or mask exposure time (for example, EB drawing time) is determined in proportion to the number of patterns per unit area. As described above, in the present invention, the number of patterns per unit time is almost the same for all exposure masks at the time of assigning the exposure process, so that there is almost no time difference between all exposure masks for data processing and mask exposure. .

  In addition, if the order in which each pattern is used in device manufacturing is used as a second reference having the next highest priority, there is a possibility that an exposure mask having a necessary pattern will be completed in a timely manner when necessary in device manufacturing. Becomes higher.

In the exposure mask according to the present invention, different exposure process patterns are arranged corresponding to a plurality of exposure processes assigned in an arbitrary combination from all the exposure processes necessary for manufacturing one semiconductor device. All of the exposure masks that are shared exposure masks necessary for manufacturing the semiconductor device have almost the same number of patterns per unit area.
Preferably, when the patterns of all the exposure steps are classified into a plurality of levels according to the number of patterns per unit area, the patterns are arranged on each exposure mask so that the combination of levels is substantially equal.
Alternatively, preferably, at least one pattern of all the levels is arranged in each of all exposure masks necessary for manufacturing the semiconductor device, and used for device manufacturing of patterns classified into any one level. In consideration of the order, patterns classified into other levels are assigned.

  According to the present invention, there is not much time difference between all exposure masks for data processing and mask exposure, and as a result, a data processing device, a mask drawing device, etc. are not occupied for a long time in the production of a specific exposure mask, Wasteful waiting time is reduced. In addition, since there is no exposure mask with an extremely long production time, it is possible to smoothly manufacture a semiconductor device in parallel with the mask production. As a result, not only the mask manufacturing time can be shortened, but also the advantage that it is easy to shorten the semiconductor device manufacturing (or prototyping) period including the mask manufacturing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The present embodiment relates to a multi-process shared mask in which a plurality of types of patterns are arranged by assigning a plurality of exposure processes and shared by the plurality of exposure processes. The present invention also relates to a method for manufacturing a multi-process shared mask and a method for manufacturing a semiconductor device including a step of creating a multi-process shared mask. In the following description, the multi-process shared mask is simply referred to as a “mask”.

FIG. 1 shows a basic processing flow in manufacturing a semiconductor device including steps for manufacturing a mask.
First, in the first step Sm1, it is determined which exposure process of semiconductor device manufacturing is assigned to each mask. This assignment determines the combination of patterns to be placed on each mask. Here, as an example, a case where a total of 25 exposure processes from the exposure process A to the exposure process Y are assigned to a total of five masks M1 to M5 is taken as an example.

  When the combination of patterns to be arranged on each of the masks M1 to M5 is determined, data processing and mask exposure are executed according to the combination (steps Sm2 and Sm3), and the actual mask pattern is developed on the mask substrate through development and etching. The light shielding film or the semi-light shielding film is formed (step Sm4), thereby completing the masks M1 to M5.

On the other hand, in the device manufacturing method shown in FIG. 1, in response to a request to advance the device completion time as much as possible, a wafer is loaded for device manufacture at an appropriate timing during mask fabrication (step Sd0). Production begins.
FIG. 1 illustrates a case where the masks M1 to M5 are completed in this order, and the supply of the masks M1 to M5 is made in time for the exposure processes A, C, E, H, and L, respectively. In this way, the mask production schedule and the device production schedule starting from the wafer loading are determined so that the timing of the mask production and the timing of the exposure process that is used first are matched as much as possible.

The present embodiment proposes an appropriate mask manufacturing method from the viewpoint of shortening such a mask manufacturing period, and further, a total device manufacturing (or prototyping) period including mask manufacturing.
Hereinafter, steps Sm1 to Sm3 in FIG. 1 will be described in detail.

  In general, when assigning an exposure process as in step Sm1, the following combinations (configurations) of patterns arranged on one mask and their criteria are considered.

First, a configuration based on the lowest price of the mask set can be employed.
Secondly, it is possible to adopt a configuration based on the fact that patterns of processes that require the same degree of transfer accuracy in a semiconductor lithography process are collected on a single mask. As the second configuration, for example, a process requiring high accuracy such as an element isolation layer or a transistor gate layer is performed on the same mask, and a process requiring less accuracy such as well formation or pad formation is performed using another mask. This is the case when consolidating into one sheet.
Third, it is possible to adopt a configuration in which patterns of the same reference are integrated into the same mask with reference to inversion and non-inversion of pattern data such as positive and negative in the process of manufacturing a mask.
Furthermore, fourthly, it is possible to adopt a configuration based on the fact that patterns in a process having the same reduction projection magnification at the time of transfer in a semiconductor lithography process are collected on the same mask.

  In the present invention, a new standard is proposed in place of a standard generally conceivable from the viewpoint of manufacturing such a mask. The reference is the number of patterns per unit area, that is, the pattern density. In the present invention, in step Sm1 shown in FIG. 1, the allocation of the exposure process is determined for each mask with the goal that all masks for manufacturing one semiconductor device have the same pattern density.

  Generally, a pattern having a high pattern density is often required to have a high transfer accuracy as a reference in the above-described second configuration. However, the transfer accuracy is the accuracy of a mask exposure apparatus (for example, an EB drawing apparatus), the quality and performance (especially resolving power) of the material and photosensitive resin of the mask light-shielding film or semi-light-shielding film, and the etching accuracy of the light-shielding film or semi-light-shielding film. The pattern density is determined by design data, which is comprehensively determined by the mask manufacturing process, and is a factor that affects data processing time and EB drawing time. Therefore, in the present invention, the pattern density, that is, the number of patterns per unit area, is used as a reference closely related to the mask manufacturing time.

  However, it is rare that the pattern density is completely uniform with a mask set of several tens of sheets.Therefore, as a preferable exposure process allocation method, the number of patterns per unit area is classified into several levels. It is desirable to have the same alignment with the mask. In this way, it is possible to make the pattern densities substantially uniform for all masks in a simple and substantially sufficient manner.

In the present invention, methods other than the level classification can be adopted, but a preferred embodiment using this level classification will be described below with reference to the drawings.
Here, as an example, the level of pattern density is indicated by levels 1 to 5. Level 1 has the highest pattern density range, Level 5 has the lowest pattern density range, and levels 2 to 4 in between are the pattern density sequentially and stepwise from level 1 to level 5. Each has a range in which is reduced.

[Example 1]
Table 1 below shows a correspondence example between a total of 25 exposure processes from exposure process A to exposure process Y assigned to the five masks M1 to M5 and each level.

[Table 1]
<Correspondence between level and process>
Level 1 A, B, C, D, E
Level 2 ... F, G, H, I, J
Level 3 ... K, L, M, N, O
Level 4 P, Q, R, S, T
Level 5: U, V, W, X, Y

FIG. 2 shows correspondence between input data, a data processing device, and a mask in the first embodiment. Here, the alphabets “A” to “Y” indicating the exposure process are also used as corresponding patterns and data codes, respectively. For convenience, the level is indicated by a number attached to the lower right of the alphabet. For example, both level A data A and pattern A are indicated by “A ₁ ”, and level 2 data F and pattern F are indicated by “F ₂ ”. The same applies to other data and patterns.

First, the completed mask will be described.
A total of five patterns of levels 1 to 5 are arranged on each of the five masks, that is, the masks M1, M2, M3, M4, and M5. Specifically, a level 1 pattern A ₁ , a level 2 pattern F ₂ , a level 3 pattern K ₃ , a level 4 pattern P ₄ , and a level 5 pattern U ₅ are arranged on the first mask M ₁ . ing.

Similarly, a total of five patterns of levels 1 to 5 are arranged on the other four masks M2 to M5.
That the mask M2, the pattern _{B 1} Level 1, the pattern _{G 2} Level 2, Level 3 of the pattern _{L 3,} the pattern _{Q 4} of Level 4, and a pattern _{V 5} Level 5 is arranged.
On the mask M3, a level 1 pattern C ₁ , a level 2 pattern H ₂ , a level 3 pattern M ₃ , a level 4 pattern R ₄ , and a level 5 pattern W ₅ are arranged.
In the mask M4, a level 1 pattern D ₁ , a level 2 pattern I ₂ , a level 3 pattern N ₃ , a level 4 pattern S ₄ , and a level 5 pattern X ₅ are arranged.
In the last mask M5, a level 1 pattern E ₁ , a level 2 pattern J ₂ , a level 3 pattern O ₃ , a level 4 pattern T ₄ , and a level 5 pattern Y ₅ are arranged.
In this way, in the first embodiment, since the five masks M1 to M5 are arranged so that the average levels are equal, the pattern density between the masks, that is, the number of patterns per unit area is substantially the same. Are aligned.

In the first embodiment, in step Sm2 of the data processing shown in FIG. 1, data processing for mask production is executed in units of five patterns for each mask.
First, five patterns of design data (hereinafter simply referred to as data) corresponding to the respective masks are input to five data processing devices DP1 to DP5. Specifically, the first data processing device DP1 includes a first data group D1, that is, level 1 pattern data A ₁ , level 2 pattern data F ₂ , level 3 pattern data K ₃ , level 4. Pattern data P ₄ and level 5 pattern data U ₅ are input.

Similarly, design data for five patterns of levels 1 to 5 is input to the other four data processing devices DP2 to DP5.
That is, the data processor DP2 receives the second data group D2, that is, the level 1 pattern data B ₁ , the level 2 pattern data G ₂ , the level 3 pattern data L ₃ , and the level 4 pattern data Q _4. , And level 5 pattern data V ₅ are input.
In the data processing device DP3, a third data group D3, that is, level 1 pattern data C ₁ , level 2 pattern data H ₂ , level 3 pattern data M ₃ , level 4 pattern data R ₄ , and data W ₅ of the pattern of the level 5 is input.
In the data processing device DP4, a fourth data group D4, that is, level 1 pattern data D ₁ , level 2 pattern data I ₂ , level 3 pattern data N ₃ , level 4 pattern data S ₄ , and, the data X ₅ pattern level 5 is input.
Then, in the last data processing device DP5, the fifth data group D5, that is, level 1 pattern data E ₁ , level 2 pattern data J ₂ , level 3 pattern data O ₃ , and level 4 pattern data T ₄ and level 5 pattern data Y ₅ are input.

  These five data processing devices DP1 to DP5 convert the inputted design data into mask exposure data, and output the data to an exposure drawing device (pattern exposure system) (not shown). The exposure drawing apparatus may be any of a pattern generator, a contact printer, a photo repeater, an electron beam (EB) drawing apparatus, and a laser drawing apparatus. Generally, an EB drawing apparatus is used. Hereinafter, the exposure drawing apparatus uses an EB drawing apparatus.

In the next mask exposure step Sm3, the latent image pattern is transferred to the photosensitive layer on the mask substrate by EB drawing.
In the subsequent mask pattern formation step Sm4, development and etching are performed to pattern the light shielding film of the mask. Thereby, the pattern of the light shielding film is formed on the mask substrate.
Through the above steps, the five masks M1 to M5 having the patterns of levels 1 to 5 described first are completed.

  As described above, in the first embodiment, data processing is performed in units of one of the first to fifth data groups D1 to D5 corresponding to the five patterns arranged in each mask. In each data group, since each level from level 1 to level 5 is prepared one by one, if the data processing amount is almost the same and the capabilities of the data processing devices DP1 to DP5 are the same, the data processing The time is also almost the same with five devices. In the first embodiment, the data processing time is substantially equal for the five masks M1 to M5. As a result, the time difference for manufacturing the masks is reduced accordingly.

  Next, by comparing Example 1 with Comparative Example 1, this effect will be clarified using specific numerical values (time).

<Comparative Example 1>
Comparative Example 1 is a case where patterns having the same transfer accuracy are arranged on the same mask from the viewpoint of mask fabrication as in the second configuration described above. Here, it is assumed that the transfer accuracy correlates with the pattern density (level), and the pattern of the total 25 exposure processes from the exposure process A to the exposure process Y is applied to a total of five masks M1 to M5 as in the first embodiment. Deploy. Accordingly, the correspondence between each process and each level is the same as in Table 1 described above.

FIG. 3 shows the correspondence between the input data, the data processing device, and the mask in Comparative Example 1.
In the first comparative example shown in FIG. 3, unlike the first embodiment shown in FIG. 2, only one level pattern is arranged on one mask. In FIG. 3 that is, the pattern _A 1 of level _1, the B _1, C 1, _{D 1} and _{E 1} is disposed on the mask M1, pattern _F 2 level 2 mask _M2, G _2, H 2, _{I 2} and J ₂ is arranged, level 3 patterns K ₃ , L ₃ , M ₃ , N ₃ and O ₃ are arranged on the mask M ₃ , and level 4 patterns P ₄ , Q ₄ , R ₄ , S ₄ and the like are arranged on the mask M _4. T ₄ is arranged, and level 5 patterns U ₅ , V ₅ , W ₅ , X ₅ and Y ₅ are arranged on the mask M 5.

In addition, because of the arrangement for each level, patterns of the same level are collected in each of the first to fifth data groups D1 to D5 input to the data processing devices DP1 to DP5, respectively.
Since level 1 has the largest number of patterns per unit area, data processing takes time. On the other hand, level 5 has the smallest number of patterns per unit area, so the data processing time is short. The other levels 2 to 4 are data processing times corresponding to the levels.
In the comparative example 1, the data processing time (H: hour) for each level of the pattern corresponding to one exposure process is as shown in Table 2 below.

[Table 2]
<Data processing time>
Level 1 ... 10H
Level 2 ・ ・ ・ 8H
Level 3 ... 6H
Level 4 ... 4H
Level 5 2H

As a result, the data processing time is the longest for the mask M1 in which level 1 patterns are collected. Since the data processing time for the level 1 pattern is 10H, there are a total of 5 patterns. Time takes 50H.
If the data processing time of this mask M1 is as long as 50H, in the flowchart shown in FIG. 1, it takes a long time to supply the mask M1 to the exposure step A (step Sd1), and the wafer loading time is advanced in advance accordingly. If it is necessary and such measures are not taken, the device completion time will be delayed. On the other hand, since the other masks M2 to M5 are already completed, useless waiting time occurs.

On the other hand, in the first embodiment, as shown in FIG. 2, each pattern from level 1 to level 5 is arranged on each mask as shown in FIG. The total processing time of ˜5 is 30H.
As a result, when comparing the masks that require the most data processing time, a time reduction of 20H (= 50H-30H) is achieved.
Therefore, when the same number of data processing apparatuses are used, the mask manufacturing time required first can be shortened by 20H due to the shortening of the data processing time, and the completion of the device can be accelerated accordingly.

As is clear from this time comparison, if the level is biased between masks as in Comparative Example 1, the data processing time of a mask with a large number of patterns and a large data scale becomes a bottleneck, which delays the mask delivery time. This can delay device manufacturing.
In the first embodiment, it is possible to prevent a delay in mask delivery due to an increase in data processing time, and thus a delay in device manufacturing, by eliminating a level deviation as much as possible between masks.

[Example 2]
FIG. 4 shows correspondence between input data, a data processing device, and a mask in the second embodiment.
In the first embodiment described above, data processing is performed in units of the exposure process assigned to each of the masks M1 to M5 in the assignment of the exposure process in step Sm1 shown in FIG.
On the other hand, in Example 2, mask exposure, for example, EB drawing, is performed in units of exposure processes assigned to the respective masks M1 to M5 to shorten the EB drawing time.

  Other points, that is, the pattern arrangement of the completed mask (assignment of exposure process), the correspondence between the 25 exposure processes shown in Table 1 and each level 1 to 5, and the first to fifth data groups D1 to D5 The combination of data is the same as in the first embodiment. However, the input data (first to fifth data groups D1 to D5) shown in FIG. 4 is EB drawing data input to the EB drawing devices EB1 to EB5, and the data processing method is arbitrary in the second embodiment. It is.

  In the second embodiment, the same exposure process assignment (combination of patterns to be arranged in each mask) as in the first embodiment is determined in step Sm1 shown in FIG. 1, and data processing for mask production is executed in step Sm2. After that, in the next step Sm3, EB drawing is executed with one of the pattern data groups D1 to D5 assigned to each mask determined in step Sm1 as a unit.

  First, five patterns of EB drawing data (any one of data groups D1 to D5) for each mask are input to five EB drawing devices EB1 to EB5. Specifically, the first data group D1 is input to the first EB drawing apparatus EB1. Similarly, data groups D2 to D5 for five patterns of levels 1 to 5 are input to the other four data EB drawing devices EB2 to EB5.

In step Sm3 of mask exposure, the latent image pattern is transferred to the photosensitive layer on the mask substrate by EB drawing.
In the subsequent mask pattern formation step Sm4, development and etching are performed to pattern the light shielding film of the mask. Thereby, the pattern of the light shielding film is formed on the mask substrate.
Through the above steps, the five masks M1 to M5 having the patterns of levels 1 to 5 described first are completed.

  As described above, in the second embodiment, mask exposure (for example, EB drawing) is performed in units of one of the first to fifth data groups D1 to D5 corresponding to the five patterns arranged in each mask. In each data group, since each level from level 1 to level 5 is one by one, the data volume at the time of EB drawing (data volume) is almost the same, and the capabilities of the EB drawing devices EB1 to EB5 are the same. If it is the same, the EB drawing time is almost the same for the five devices. In the second embodiment, as a result of the EB drawing time being substantially equal for the five masks M1 to M5, an effect that the time difference for manufacturing the mask is small is obtained.

  Next, by comparing Example 2 with Comparative Example 2, this effect will be clarified using specific numerical values (time).

<Comparative example 2>
FIG. 5 shows the correspondence between the input data, the EB drawing apparatus, and the mask in Comparative Example 2.
The comparative example 2 shown in FIG. 5 is different from the comparative example 1 shown in FIG. 3 in that processing based on the exposure process assigned to each mask M1 to M5 is not data processing but EB drawing.
Other points, that is, the pattern arrangement of the completed mask (assignment of exposure process), the correspondence between the 25 exposure processes shown in Table 1 and each level 1 to 5, and the first to fifth data groups D1 to D5 The data combination is the same as in Comparative Example 1.

In the first to fifth data groups D1 to D5, the level 1 data is data of the pattern having the largest number of patterns per unit area, so that it takes time for EB drawing. Since the number of patterns per pattern is the smallest, the EB drawing time is also short. The other levels 2 to 4 are EB drawing times corresponding to the levels.
In such Comparative Example 2, the EB drawing time (H: hour) for each level of the pattern corresponding to one exposure process is as shown in Table 3 below.

[Table 3]
<EB drawing time>
Level 1 ... 5H
Level 2 ... 4H
Level 3 ... 3H
Level 4 2H
Level 5 ... 1H

As a result, the EB drawing time is the longest in the mask M1 in which the level 1 patterns are collected. Since the EB drawing time of the level 1 pattern is 5H and there are a total of 5 patterns, the EB drawing of the mask M1 is performed. Time takes 25H.
If the EB drawing time of the mask M1 is as long as 25H, in the flowchart shown in FIG. 1, the time until the mask M1 is supplied to the exposure step A (step Sd1) is long, and the wafer loading time is advanced in advance accordingly. If it is necessary and such measures are not taken, the device completion time will be delayed. On the other hand, since the other masks M2 to M5 are already completed, useless waiting time occurs.

On the other hand, in the second embodiment, as shown in FIG. 4, since each pattern from level 1 to level 5 is arranged on each mask one by one, the EB drawing time per mask is the level shown in Table 3 above. The total of the EB drawing times of 1 to 5 is 15H.
As a result, when comparing the masks that require the longest EB drawing time, a time reduction of 10H (= 25H-15H) is achieved.
Therefore, when the same number of EB lithography apparatuses are used, by shortening the EB lithography time, it is possible to shorten the mask preparation time required for the first time by 10H, and to speed up the completion of the device.

As is clear from this time comparison, if there is a bias in the level between masks as in Comparative Example 2, the EB drawing time of a mask with a large number of patterns and a large amount of EB drawing data becomes a bottleneck, and the mask delivery time is delayed. This causes a delay in device manufacture.
In the second embodiment, it is possible to prevent a delay in mask delivery due to an increase in the EB drawing time, and thus a delay in device manufacture, by eliminating the level deviation between the masks as much as possible.

[Example 3]
In the third embodiment, both the data processing and the EB drawing are performed by using the exposure process assigned to each of the masks M1 to M5 in the assignment of the exposure process in step Sm1 shown in FIG. 1 to shorten the data processing time and the EB drawing time. Plan. Since Example 3 is a combination of Example 1 and Example 2, detailed description thereof is omitted here.
FIG. 6 shows correspondence between input data, a data processing device, an EB drawing device, and a mask in the third embodiment.

  In the third embodiment, both data processing and mask exposure (for example, EB drawing) are performed in units of one of first to fifth data groups D1 to D5 corresponding to five patterns arranged in each mask. . In each data group, since each level from level 1 to level 5 is prepared one by one, the data processing amount is almost the same. For this reason, assuming that the capacities of the data processing devices DP1 to DP5 are the same, the data processing time is substantially the same for the five devices. Further, since the data volume at the time of EB drawing is almost the same, assuming that the capabilities of the EB drawing devices EB1 to EB5 are the same, the EB drawing time is also substantially the same for the five devices. In the third embodiment, each of the data processing time and the EB drawing time is substantially equal for the five masks M1 to M5. As a result, an effect that the time difference for manufacturing the masks is small is obtained. .

  Next, by comparing Example 3 with Comparative Example 3, this effect will be clarified using specific numerical values (time).

<Comparative Example 3>
FIG. 7 shows correspondence between input data, a data processing device, an EB drawing device, and a mask in Comparative Example 3. Since the comparative example 3 is a combination of the comparative example 1 shown in FIG. 3 and the comparative example 2 shown in FIG. 5, detailed description thereof is omitted here.
In the first to fifth data groups D1 to D5 shown in FIG. 7, the level 1 data is the pattern data having the largest number of patterns per unit area, and therefore requires both data processing and EB drawing. On the other hand, since level 5 has the smallest number of patterns per unit area, the time is short for both data processing and EB drawing. The other levels 2 to 4 are data processing time and EB drawing time corresponding to the level.

In the comparative example 3, the data processing time for each level of the pattern corresponding to one exposure process has already been shown in Table 2, and the EB drawing time has already been shown in Table 3.
Referring to Tables 2 and 3, the longest (data processing time + EB drawing time) is the mask M1 in which patterns of level 1 are collected, and the longest (data processing time + EB drawing time) is The sum of the data processing time 50H of the mask M1 calculated in the comparative example 1 and the EB drawing time 25H of the mask M1 calculated in the comparative example 2, that is, 75H.

  If the (data processing time + EB writing time) of this mask M1 is as long as 75H, in the flow chart shown in FIG. 1, it takes a long time to supply the mask M1 to the exposure step A (step Sd1), and the wafer loading timing accordingly. If such measures are not taken, the device completion time will be delayed. On the other hand, since the other masks M2 to M5 are already completed, useless waiting time occurs.

On the other hand, in Example 3, since each pattern from level 1 to level 5 is arranged one by one in each mask as shown in FIG. 6, (data processing + EB drawing time) per mask is 30H that is the sum of the processing times of levels 1 to 5 in Table 2 above, and 15H that is the sum of the processing times of levels 1 to 5 in Table 3 is 45H.
As a result, when the masks that require the most (data processing time + EB drawing time) are compared, a time reduction of 30H (= 75H−45H) is achieved.
Therefore, when the same number of data processing devices and the same number of EB drawing devices are used, the (mask time required for EB drawing time) can be shortened by 30 hours. Can expedite the completion of the device.

As is clear from this time comparison, if the level is biased between the masks as in Comparative Example 3, the number of patterns is large and the time delay of data processing and EB drawing becomes a bottleneck, which delays the mask delivery time, which makes device manufacturing Cause delay.
In the third embodiment, it is possible to prevent a delay in mask delivery due to an increase in both the data processing time and the EB drawing time, and thus a delay in device manufacturing, by eliminating the level deviation between the masks as much as possible. .

[Example 4]
In Example 4, a total of 30 exposure process patterns from Step A to Step Z3 are arranged on five masks. The correspondence between the 30 steps and each level is as shown in Table 4 below.

[Table 4]
<Correspondence between level and process>
Level 1 ... A, B, C, D, E, F
Level 2 ... G, H, I, J, K, L
Level 3 ... M, N, O, P, Q, R
Level 4 ... S, T, U, V, W, X
Level 5: Y1, Y2, Y3, Z1, Z2, Z3

FIG. 8 shows correspondence between input data, a data processing device, an EB drawing device, and a mask in the fourth embodiment. FIG. 9 shows the correspondence between the device manufacturing process number, process name, level, and execution date.
Each device manufacturing process used in Example 4 is a breakdown of a total of 30 process numbers P01 to P30 as shown in the table of FIG. Further, FIG. 9 shows the number of days calculated from the process start date for the schedule for performing each process. The masks M1 to M5 used in each process are arranged with six patterns of levels as shown in FIG.

In the fourth embodiment, as shown in FIG. 8, one data processing device DP and five EB drawing devices EB1 to EB5 are used. Data (design data) is input to the data processing device DP for each level, and the process of converting the data into EB drawing data is executed in units of pattern data groups arranged for each mask shown in FIG. To do. The processed data (EB drawing data) is input to each EB drawing device for each data group, and EB drawing is executed for each data group.
The data processing time for each level per process is increased from 5 to 6 in the data groups D1 to D5 than in the second embodiment, but the data processing speed is slightly longer than in the second embodiment. Therefore, it is the same as Table 2 described above.

  Hereinafter, also in Example 4, the comparison with the comparative example is performed as in the other examples. Here, as an example, the masks M1 and M2 are compared in data processing time, and the time difference at which mask fabrication can be started is compared.

<Comparative example 4>
FIG. 10 shows correspondence between input data, a data processing device, an EB drawing device, and a mask in Comparative Example 4. This comparative example 4 is common to the other comparative examples in that the arrangement patterns in the masks M1 to M5 are aligned at a single level, and the other basic configuration is the same as that of the fourth embodiment shown in FIG. To do. However, in the data processing device DP and each of the EB drawing devices EB1 to EB5, processing (data conversion or EB drawing) is executed in units of a single level pattern data group.

  Since the first data group D1 shown in FIG. 10 is all level 1 data, it takes considerable time for both data processing and EB drawing. On the other hand, since the fifth data group D5 is all level 5 data, the time required for both data processing and EB drawing is short. The other data groups D2 to D4 have data processing time and EB drawing time according to their levels.

In the comparative example 4, the data processing time for each level of the pattern corresponding to one exposure process has already been shown in Table 2, and the EB drawing time has already been shown in Table 3.
Since the mask M1 has six level 1 patterns, the data processing time of each pattern is 10H from Table 2, and the time required for the data processing time for manufacturing the mask M1 is 60H (= 10H in total). × 6: about 2.5 days).

  On the other hand, in Example 4, the level of each mask was averaged as in Configuration Example 4, and the order of each exposure step in device manufacturing was taken into account when varying the level. That is, the mask M1 shown in FIG. 8 corresponds to the process number P01 that is performed earliest in the level 1 when the exposure process of device manufacturing is viewed in the order of early, that is, in the order of smaller process numbers in FIG. A pattern for step A is arranged. In addition, the step of arranging on the same mask together with the step A includes three steps (Y1, Y2, Y3) of level 5 of process numbers P02 to P04 and one step (S) of level 4 of process number P05. select.

Therefore, the data processing time for manufacturing the mask M1 (FIG. 8) of Example 4 is 20 steps (= (10H × 1)) in which level 1 is 1 step, level 4 is 1 step, and level 5 is 4 steps. + (4H × 1) + (2H × 4): about 0.83 days).
Therefore, when the data processing time required for manufacturing the mask M1 is compared between Example 4 and Comparative Example 4, the data processing time for the mask M1 of Example 4 (FIG. 8) is about the mask M1 of Comparative Example 4. 40H (= 60H-20H = 40H: about 1.66 days) is shorter than the data processing time.

Here, when the case where the mask M1 is used in the device manufacturing process in the process chart shown in FIG. 9 is considered, the mask is required earliest in the process A of process number P01.
However, in the configuration of the mask M1 of Comparative Example 4 (FIG. 10), the mask fabrication is not started until the data processing of the other arrangement steps (B, C, D, E, F) is completed. By selecting the configuration of the mask M1 as shown in FIG. 4 (FIG. 8), it becomes possible to start the mask fabrication earlier (in this example, about 1.66 days earlier). A mask can be applied as early as 66 days.

  Here, the effect has been described only for the data processing of the first mask M1, but the delay due to the EB drawing time and the same effect can be obtained with other masks, and the exposure process in actual device manufacturing as in the fourth embodiment. Considering the order of use of the items has an extremely large effect as a whole. Therefore, it is possible to establish a schedule in which mask manufacturing and device manufacturing are very closely linked, and it is possible to greatly shorten the period from the start of mask manufacturing data processing to the completion of an actual device.

[Example 5]
The fifth embodiment is a generalization of the fourth embodiment, and for this purpose, a coefficient LD generated by arbitrarily weighting the mask level and the process execution date is newly introduced. A pattern (process) is assigned to each mask on the basis of the coefficient LD. Hereinafter, this method will be described in detail.

FIG. 11 shows the correspondence between the device manufacturing process number, process name, level, execution date, and coefficients.
In the fifth embodiment, as shown in FIG. 11, a level coefficient L is set by multiplying the mask level by an arbitrary coefficient α (α: natural number). Here, as a specific example, α = 3. Also, an implementation date coefficient D is set by multiplying an arbitrary coefficient β (β: natural number) on the implementation date of each step. Here, β = 2 is set as a specific example. Then, a new coefficient LD is set by multiplying the level coefficient L and the implementation date coefficient D. Each coefficient LD for the processes P01 to P30 takes a numerical value as shown in FIG. The weighting coefficients α and β can be set freely. Here, the ratio is set to 3: 2.

Next, the steps P01 to P30 in the chart shown in FIG. 11 are sorted by the value of the coefficient LD, and are arranged in ascending order. Then, in the order of increasing coefficient LD, the mask No. (No. 1 to No. 5 are assigned to a total of five masks here). The chart after the assignment is shown in FIG.
Finally, as shown in FIG. 13, each process P01-P30 in the chart shown in FIG. Rearrange every one. Thereby, the process assigned to each mask M1 (No. 1), M2 (No. 2), M3 (No. 3), M4 (No. 4) and M5 (No. 5) is determined.

  FIG. 14 shows the correspondence between input data, a data processing apparatus, an EB drawing apparatus, and a mask in the fifth embodiment based on FIG.

  In the fifth embodiment, in addition to the pattern level of each process, information on the process execution date can be arbitrarily reflected, so that a profit that the pattern can be assigned to each mask more efficiently can be obtained.

  As mentioned above, although embodiment of this invention was described based on Examples 1-5, the range of this invention is not limited to an Example.

  In the first to fifth embodiments, it has been described that five EB drawing apparatuses are prepared and the five masks M1 to M5 are processed in parallel. In Examples 1 to 3, five data processing devices were also prepared. However, the present invention can also be applied to time-series processing in which one or both of the data processing apparatus and the EB drawing apparatus are used as one unit. That is, if the levels 1 to 5 are evenly distributed with five masks and the number of patterns per unit area is substantially equalized, then five masks M1 to M5 are produced compared to a case where this is not considered at all. , Can be performed at evenly closer intervals. For this reason, it is difficult to wait for the completion of a mask that takes a longer time to manufacture than other masks in device manufacturing, and the device manufacturing becomes smooth.

  In the first to fifth embodiments, the level is set to five levels, and five masks are taken up. However, the number of level masks is not limited to this, and the present invention can be applied to other cases. It is.

In Example 4, pattern arrangement was performed in consideration of the use order (process number) of the exposure process in device manufacture. When this is expanded, in the present invention, when the level, that is, the number of patterns per unit area is used as the first reference, the order of use of the exposure process can be used as the second reference. In Example 5, these two criteria can be reflected at an arbitrary ratio.
Actually, in the first to third embodiments, the pattern arrangement is such that the second reference is applied. That is, as shown in FIG. 1, the exposure steps A to Y are used in device manufacturing in alphabetical order. However, in the five masks M <b> 1 to M <b> 5 of Examples 1 to 3, the arrangement within each level is as follows. The order of use of the exposure process is adapted. Specifically, level 1 patterns A1, B1, C1, D1, and E1 are arranged on the masks M1 to M5, respectively. For this reason, it is assumed that the masks M1 to M5 are used in ascending order. At this time, for other levels, for example, level 2, the patterns F2, G2, H2, I2, and J2 are arranged in the masks M1 to M5 in alphabetical order, and conform to the order in which the masks are used. The same applies to other levels 2 to 5.
Therefore, there is an effect that time waste such as waiting for the completion of the mask in the device manufacture is unlikely to occur.

  In the present invention, in order to evenly distribute the levels and to average the mask manufacturing time, it is desirable that the average level is uniform for all the masks. As such a method, it is desirable to arrange at least one pattern of every level in each mask. However, in the present invention, it is not an essential requirement to make the average level uniform for all masks, and a pattern arrangement in which the average level difference is reduced from the state of a single level mask as in Comparative Examples 1 to 4 can be used. That's fine.

  Further, the number of device processes and the corresponding mask levels in Examples 4 and 5 are not limited to the above description, and the process selected in manufacturing the mask can be freely determined in consideration of the order of the device processes. Can be selected.

According to the present embodiment, in manufacturing a mask used in a lithography process, a mask manufacturing time is determined by determining a combination of pattern processes arranged in the same mask so as to shorten a data processing time and a mask drawing time. Can be shortened.
In general, the data processing time and drawing time of a pattern for a process with a large data scale are long, and conversely, the data processing time and drawing time of a pattern for a process with a small data scale are short. For this reason, in particular, in the case of the third embodiment, a reduction in data processing time and a reduction in mask drawing time are combined to provide a synergistic effect that the total mask manufacturing time can be further reduced.

In embodiment of this invention, it is a figure which shows the flow of a basic process in manufacture of the semiconductor device containing each step for preparation of a mask. It is a figure which shows a response | compatibility with the input data in Example 1, a data processor, and a mask. It is a figure which shows a response | compatibility with the input data in the comparative example 1, a data processor, and a mask. It is a figure which shows a response | compatibility with the input data in Example 1, a data processor, and a mask. It is a figure which shows a response | compatibility with the input data in the comparative example 2, EB drawing apparatus, and a mask. FIG. 10 is a diagram illustrating correspondence between input data, a data processing device, an EB drawing device, and a mask in Embodiment 3. It is a figure which shows a response | compatibility of the input data in the comparative example 3, a data processing apparatus, EB drawing apparatus, and a mask. FIG. 10 is a diagram illustrating a correspondence between input data, a data processing device, an EB drawing device, and a mask according to a fourth embodiment. It is a table | surface which shows the response | compatibility of the manufacturing number of a device in Example 4, a process name, a level, and an implementation date. It is a figure which shows a response | compatibility of the input data in the comparative example 4, a data processor, EB drawing apparatus, and a mask. It is a table | surface which shows the response | compatibility of the device manufacturing process number in Example 5, a process name, a level, and an implementation date. FIG. 12 is a chart after the steps shown in FIG. 11 are sorted in ascending order of the coefficient LD. Each process shown in FIG. It is a chart after rearranging every. FIG. 10 is a diagram illustrating correspondence between input data, a data processing device, an EB drawing device, and a mask according to a fifth embodiment.

Explanation of symbols

M1 to M5 ... exposure mask, DP1 to DP5 ... data processing device, EB1 to EB5 ... EB drawing device, A to Y ... pattern or data, D1 to D5 ... data group, L ... mask level coefficient, D ... for each step Implementation date coefficient, LD: coefficient used for assigning each process (pattern) to the mask

Claims (9)

An exposure mask manufacturing method in which patterns of different exposure processes are arranged corresponding to a plurality of exposure processes assigned in an arbitrary combination from all exposure processes necessary for manufacturing one semiconductor device, and are shared by the different exposure processes. Because
With the goal of aligning the number of patterns per unit area in all exposure masks necessary for manufacturing the semiconductor device, an allocation step of an exposure process that allocates all the exposure processes to each exposure mask;
A data processing step of creating exposure mask data;
A mask exposure step of transferring a pattern based on the data to the photosensitive layer of the mask substrate,
A method for manufacturing an exposure mask, wherein at least one of the data processing and the mask exposure is performed in units of the plurality of exposure processes assigned to each of the exposure masks. In the assigning step of the exposure process, the pattern of all the exposure processes is classified into a plurality of levels according to the number of patterns per unit area, and the target is that the combination of the levels is the same for all the exposure masks The method for manufacturing an exposure mask according to claim 1, wherein the exposure process is assigned to each exposure mask. In the assigning step of the exposure process, when the number of patterns per unit area is a first reference, the order used in device manufacture of each pattern is the second reference having the next highest priority, and each of the exposure processes The method for manufacturing an exposure mask according to claim 1, wherein assignment to an exposure mask is performed. An exposure mask in which different exposure process patterns are arranged corresponding to a plurality of exposure processes assigned in an arbitrary combination from all the exposure processes necessary for manufacturing one semiconductor device, and is shared by the different exposure processes. ,
An exposure mask in which all the exposure masks necessary for manufacturing the semiconductor device have almost the same number of patterns per unit area. The pattern is arranged on each exposure mask so that the combination of levels is substantially equal when the patterns of all the exposure processes are classified into a plurality of levels according to the number of patterns per unit area. The exposure mask as described. In consideration of the order in which at least one pattern of all the levels is arranged in each of all exposure masks necessary for manufacturing the semiconductor device, and the pattern is classified into any one level. The exposure mask according to claim 4, wherein patterns classified into other levels are assigned. An exposure mask manufacturing step for preparing all exposure masks in advance by arranging a plurality of patterns in each mask in an arbitrary combination from patterns required when forming a semiconductor device on a semiconductor substrate, and all the exposure masks, A method of manufacturing a semiconductor device, including a device forming step of forming a semiconductor device using the necessary patterns in the order in which they are formed,
The step of producing the exposure mask comprises:
With the goal of aligning the number of patterns per unit area with all the exposure masks, an allocation step of an exposure step that allocates all the exposure steps necessary for forming the semiconductor device to each mask;
A data processing step of creating exposure mask data;
A mask exposure step of transferring a pattern based on the data to the photosensitive layer of the mask substrate,
A method of manufacturing a semiconductor device, wherein at least one of the data processing and the mask exposure is performed in units of the plurality of exposure processes assigned to each exposure mask. In the assigning step of the exposure process, the pattern of all the exposure processes is classified into a plurality of levels according to the number of patterns per unit area, and the target is that the combination of the levels is the same for all the exposure masks The method for manufacturing a semiconductor device according to claim 7, wherein the exposure process is assigned to each exposure mask. In the assigning step of the exposure process, when the number of patterns per unit area is a first reference, the order used in device manufacture of each pattern is the second reference having the next highest priority, and each of the exposure processes The method for manufacturing a semiconductor device according to claim 7, wherein assignment to an exposure mask is performed.

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