JP2006115615A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a power supply circuit that can surely reduce power consumption while having a simple constitution. <P>SOLUTION: A power supply voltage VDD outputted by a first constant voltage circuit 3 can be varied to a minimum voltage minimally necessary for second constant voltage circuits 4A to 4C to always output power supply voltages VOUTa to VOUTc without the need for separately installing a conventional external circuit, a voltage switching control circuit or the like by varying the power supply voltage VDD outputted by the first constant voltage circuit 3 according to synchronizing signals S2a to S2c that express variations and magnitudes of the power supply voltages VOUTa to VIUTc that are fed back to the first constant voltage circuit 3 from the second constant voltage circuits 4A to 4C. By this, power wastefully consumed at the second constant voltage circuits 4A to 4C can be reduced without complicating a circuit constitution, and also power consumption can surely be reduced while having the simple constitution. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power supply circuit, and is suitable for application when a supplied power supply voltage is converted into an arbitrary voltage and output.

  In recent years, portable devices such as portable telephones and portable audio players are widely used. Since these mobile devices are required to extend the operation time of the battery, various kinds of power consumption are reduced.

  For example, a power supply circuit for a portable device has been proposed in which each circuit unit is designed to supply energy (power) as efficiently as possible to reduce power consumption. A conventional power supply circuit will be described.

  As shown in FIG. 5, the power supply circuit 100 reduces the power supply voltage VIN supplied from the DC power supply 101 to the desired power supply voltage VDD by the first constant voltage circuit 102, and reduces the power supply voltage VDD to a plurality of second constant voltages VDD. The voltage circuits 103A to 103C convert the power supply voltages VOUTa to VOUTc required by each circuit unit (not shown) in the subsequent stage and output them.

  In such a power supply circuit 100, for example, a switching regulator is used for the first constant voltage circuit 102, and a series regulator is used for the second constant voltage circuits 103A to 103C.

  In practice, the switching regulator has a feature that the efficiency is high but the noise and the ripple of the output voltage are large and the accuracy of the output voltage is low, and the series regulator has the feature that the accuracy of the output voltage is high although the efficiency is low.

  That is, in the power supply circuit 100, the power supply voltage VIN is lowered to the power supply voltage VDD close to each of the power supply voltages VOUTa to VOUTc required by each circuit unit in the subsequent stage with a highly efficient switching regulator, and then the power supply voltage VDD is output. A series regulator with high voltage accuracy, which converts each power supply voltage VOUTa to VOUTc required by each circuit unit in the subsequent stage and outputs it, thereby making it more accurate than a power supply circuit consisting only of a switching regulator or series regulator. High output voltage can be output with low power consumption.

  The power supply circuit 100 operates only necessary circuits (for example, the second constant voltage circuits 103A and 103B) among the second constant voltage circuits 103A to 103C according to the operation state of each circuit unit in the subsequent stage. Thus, by outputting only the necessary power supply voltages (for example, power supply voltages VOUTa and VOUTb), the power consumption can be further reduced.

  An example of the circuit configuration of the first constant voltage circuit 102 is shown in FIG. The first constant voltage circuit 102 lowers the power supply voltage VIN input via the input terminal 110 to a desired power supply voltage VDD, and supplies it to a load (second constant voltage circuit not shown) via the output terminal 111. 103A to 103C), and includes a switching transistor 112, a rectifying transistor 113, a smoothing circuit 114, a voltage dividing circuit 115, and a control circuit 116.

  The switching transistor 112 is a pMOS type FET, and its source is connected to the input terminal 110 and its gate is connected to the control circuit 116.

  The rectifying transistor 113 is an nMOS type FET, and its drain is connected to the drain of the switching transistor 112, its gate is connected to the control circuit 116, and its source is grounded.

  The switching transistor 112 and the rectifying transistor 113 are alternately turned on / off by a control signal supplied from the control circuit 116.

  The smoothing circuit 114 includes a coil 114A and a capacitor 114B. One end of the coil 114A is connected to the drain of the switching transistor 112 (the drain of the rectifying transistor 113), and the other end of the coil 114A is a capacitor. One end of 114B is connected to the output terminal 111, and the other end of the capacitor 114B is grounded.

  Here, in the first constant voltage circuit 102, when the rectifying transistor 113 is turned off and the switching transistor 112 is turned on, the input terminal 110 and one end of the coil 114A are electrically connected through the switching transistor 112. As a result, the power supply voltage VIN supplies energy (electric power) to the coil 114A and the capacitor 114B, and also supplies energy to the load (second constant voltage circuits 103A to 103C) (not shown) via the output terminal 111. To do. At this time, energy is stored in the coil 114A, and the capacitor 114B is charged.

  From this state, when the switching transistor 112 is turned off and the rectifying transistor 113 is turned on, the input terminal 110 and one end of the coil 114A are electrically disconnected. As a result, back electromotive force is generated at both ends of the coil 114A and the rectifying action of the rectifying transistor 113 works, so that the energy stored in the coil 114A is not shown via the output terminal 111 (second constant (not shown)). Voltage circuit 103A-103C). At this time, the capacitor 114B is discharged.

  As described above, the first constant voltage circuit 102 repeatedly turns on / off the switching transistor 112 and the rectifying transistor 113 to repeatedly charge and discharge the coil 114A and the capacitor 114B. As a result, the potential of the output terminal 111 is smoothed. The output terminal 111 can output a stable power supply voltage VDD.

  Further, in the first constant voltage circuit 102, the fluctuation of the power supply voltage VDD is fed back to the control circuit 116 via the voltage dividing circuit 115.

  The voltage dividing circuit 115 includes two resistors 115A and 115B connected in series between the output terminal 111 and GND. The voltage dividing circuit 115 divides the power supply voltage VDD by the resistance ratio of the resistors 115A and 115B, and obtains the resulting voltage ( Hereinafter, this is also referred to as a divided voltage) Vx is supplied to the control circuit 116.

  The control circuit 116 includes a reference voltage generation circuit 116A, a triangular wave generation circuit 116B, a comparator 116C, and a drive circuit 116D. The control circuit 116 uses the divided voltage Vx supplied from the voltage dividing circuit 115 as the second voltage of the comparator 116C. Input to the non-inverting input terminal.

  Further, the reference voltage Vxr from the reference voltage generating circuit 116A is input to the first non-inverting input terminal of the comparator 116C, and the triangular wave signal from the triangular wave generating circuit 116C is input to the inverting input terminal.

  As a result, the comparator 116C compares the differential voltage between the divided voltage Vx and the reference voltage Vxr with the triangular wave signal, and when the level (voltage) of the differential voltage is higher than the triangular wave signal, the comparator 116C is high. A PWM (Pulse Width Modulation) signal that is a (High) level and is low when it is low is generated, and this PWM signal is output to the drive circuit 116D.

  The drive circuit 116D has a first output terminal connected to the gate of the switching transistor 112 and a second output terminal connected to the gate of the rectifying transistor 113. The drive circuit 116 outputs a control signal for turning on the switching transistor 112 and turning off the rectifying transistor 113 when the PWM signal supplied from the comparator 116C is at a low level, and when the PWM signal is at a high level. A control signal for turning off the switching transistor 112 and turning on the rectifying transistor 113 is output.

  Thus, when the divided voltage Vx becomes lower than the reference voltage Vxr, the first constant voltage circuit 102 increases the ON time of the switching transistor 112 and increases the power supply voltage because the power supply voltage VDD becomes lower than the desired voltage at this time. When VDD is raised and the divided voltage Vx becomes higher than the reference voltage Vxr, the power supply voltage VDD becomes higher than a desired voltage at this time. Therefore, the OFF time of the switching transistor 112 is increased to lower the power supply voltage VDD. As a result, the divided voltage Vx and the reference voltage Vxr can be matched to output the desired power supply voltage VDD from the output terminal 111.

  Next, FIG. 7 illustrates an example of a circuit configuration of the second constant voltage circuits 103 </ b> A to 103 </ b> C serving as a load of the first constant voltage circuit 102. Since the circuit configurations of the second constant voltage circuits 103A to 103C are all the same, only the second constant voltage circuit 103A will be described here, and the second constant voltage circuits 103B and 103C will be described. Is omitted.

  The second constant voltage circuit 103A converts the power supply voltage VDD input from the first constant voltage circuit 102 via the input terminal 120 into a predetermined power supply voltage VOUTa required by the circuit unit in the subsequent stage, and converts this. This is a series regulator that outputs from the output terminal 121 to a subsequent circuit portion, and includes an output control transistor 122, a voltage dividing circuit 123, and a control circuit 124. Incidentally, the output control transistor 122 and the voltage dividing circuit 123 are collectively referred to as an output stage.

  The output control transistor 122 is a pMOS type FET, the source is connected to the input terminal 120, the gate is connected to the control circuit 124, and the drain is connected to the output terminal 121 and the voltage dividing circuit 123. It is connected.

  The voltage dividing circuit 123 includes two resistors 123A and 123B connected in series between the output terminal 121 (the source of the output control transistor 122) and GND, and outputs the power supply voltage VOUTa to the resistors 123A and 123B. The voltage is divided by the resistance ratio, and the resulting divided voltage Vy is supplied to the control circuit 124.

  The control circuit 124 includes a reference voltage generation circuit 124 A and a differential amplifier 124 B that operates with the power supply voltage VDD supplied from the first constant voltage circuit 102, and the divided voltage Vy from the voltage dividing circuit 123. Is input to the non-inverting input terminal of the differential amplifier 124B, and the reference voltage Vyr from the reference voltage generating circuit 124A is input to the inverting input terminal of the differential amplifier 124A.

  The differential amplifier 124B amplifies the differential voltage between the input divided voltage Vy and the reference voltage Vyr, and supplies the amplified differential voltage to the gate of the output control transistor 122 as a control signal.

  Thus, when the divided voltage Vy becomes lower than the reference voltage Vyr, the control circuit 124 reduces the level of the control signal supplied to the gate of the output control transistor 122 because the power supply voltage VOUTa becomes lower than the desired voltage at this time. If the output control transistor 122 is controlled so that the power supply voltage VOUTa increases and the divided voltage Vy becomes higher than the reference voltage Vyr, the power supply voltage VOUTa becomes higher than the desired voltage at this time. The output control transistor 122 is controlled so that the level of the control signal supplied to the gate of the control transistor 112 is increased and the power supply voltage VOUTa is decreased.

  As a result, the control circuit 124 can output a desired stable power supply voltage VOUTa from the output terminal 121.

  Further, the second constant voltage circuits 103B and 103C having the same configuration also include, for example, a voltage dividing circuit 123 having a resistance value different from that of the second constant voltage circuit 103A, so that the input power supply voltage VDD is the power supply voltage. A power supply voltage VOUTb or a power supply voltage VOUTc different from VOUTa can be converted and output.

  By the way, the second constant voltage circuit 103A having the circuit configuration as described above is a step-down series regulator. Therefore, in order to output a desired power supply voltage VOUTa, at least the desired power supply voltage VOUTa is required due to its characteristics. An input voltage of about (for example, 1.5 [V]) + 0.3 [V] (that is, power supply voltage VDD) is required.

  Similarly, the second constant voltage circuit 103B requires a power supply voltage VDD of at least about power supply voltage VOUTb (for example, 2.0 [V]) + 0.3 [V], and the second constant voltage circuit 103C requires at least a power supply voltage VDD. A power supply voltage VDD of about voltage VOUTc (for example, 2.8 [V]) + 0.3 [V] is required.

  Therefore, the power supply voltage VDD output from the first constant voltage circuit 102 is the highest power supply voltage (in this case, 2.8 [V]) + 0.3 [V] among the power supply voltages VOUTa to VOUTc. Required at a minimum.

  Therefore, in the power supply circuit 100, the power supply voltage VDD output from the first constant voltage circuit 102 is the voltage that is the minimum required to output the desired power supply voltages VOUTa to VOUTc from the second constant voltage circuits 103A to 103C. Is set to a maximum value (2.8 [V] +0.3 [V] = 3.1 [V]), and thereby, wasted power consumed by the second constant voltage circuits 103A to 103C As much as possible, power consumption is reduced.

  However, in the power supply circuit 100, as described above, for example, the second constant voltage circuit 103C is stopped from this state, and only the desired power supply voltages VOUTa and VOUTb are output from the second constant voltage circuits 103A and 103B. At this time, the minimum required voltage (2.0 [V] +0.3 [V] = 2.3 [V]) as the power supply voltage VDD is set to the set voltage (3 .1 [V]), and this difference becomes wasteful power.

  That is, in the power supply circuit 100, the set power supply voltage VDD is not necessarily the minimum necessary voltage except when all the second constant voltage circuits 103A to 103B are operated to output the power supply voltages VOUTa to VOUTC. In other cases, useless power may be generated.

Therefore, conventionally, as a power supply circuit that converts the power supply voltage VDD output from the first constant voltage circuit to an arbitrary power supply voltage VOUT by the second constant voltage circuit and outputs the power supply voltage, the power supply voltage VOUT There has been proposed one that can switch the voltage value of the voltage VDD (see, for example, Patent Document 1).
JP 2003-235250 A

  However, in such a power supply circuit, since the voltage value of the power supply voltage VDD is actually switched according to a signal supplied from the outside, the external circuit that generates such a signal or the power supply voltage VDD according to this signal A voltage switching control circuit or the like for switching the voltage value is separately required, and the power consumption increases by operating these external circuits and the voltage switching control circuit. As a result, the power consumption is reduced. In addition, there is a problem that the circuit configuration becomes complicated by incorporating a voltage switching control circuit and the like.

  The present invention has been made in view of the above points, and an object of the present invention is to propose a power supply circuit capable of reliably reducing power consumption while having a simple configuration.

  In order to solve such a problem, in the power supply circuit of the present invention, the first voltage conversion circuit that converts the power supply voltage from the DC power supply to an arbitrary first voltage and outputs the first voltage conversion circuit, and the first voltage conversion circuit In a power supply circuit having at least one second voltage conversion circuit that converts the first voltage into an arbitrary second voltage and outputs the second voltage, the value indicates the value of the second voltage output by the second voltage conversion circuit Feedback means for feeding back the signal from the second voltage conversion circuit to the first voltage conversion circuit is provided, and the value of the second voltage that is fed back from the second voltage conversion circuit by the feedback means. The first voltage is changed in accordance with a signal indicating.

  As a result, the first voltage output from the first voltage conversion circuit and the second voltage conversion circuit output the second voltage without separately providing a conventional external circuit, voltage switching control circuit, or the like. Can be changed to the minimum voltage required for the minimum.

  According to the present invention, a first voltage conversion circuit that converts a power supply voltage from a DC power supply into an arbitrary first voltage and outputs the first voltage, and a first voltage from the first voltage conversion circuit is output as an arbitrary first voltage. In the power supply circuit having at least one second voltage conversion circuit that converts and outputs the voltage to the second voltage, a signal indicating the value of the second voltage output from the second voltage conversion circuit is output to the second voltage conversion circuit. Feedback means is provided for feedback from the first voltage conversion circuit to the first voltage conversion circuit, and the first voltage conversion circuit receives a signal indicating the value of the second voltage fed back from the second voltage conversion circuit by the feedback means. By changing the voltage of 1, the first voltage output from the first voltage conversion circuit can be converted into the second voltage conversion without providing a conventional external circuit or voltage switching control circuit separately. The minimum required for the circuit to output the second voltage. Since the voltage can be changed to a small voltage, the wasteful power consumed by the second voltage conversion circuit can be reduced without complicating the circuit configuration, and thus the power consumption can be surely reduced with a simple configuration. A power supply circuit that can be reduced can be realized.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Overall Configuration of Power Supply Circuit In FIG. 1, reference numeral 1 denotes a power supply circuit as a whole, and the power supply voltage VIN supplied from the DC power supply 2 is supplied to the first constant voltage circuit 3 and the second constant voltage circuits 4A to 4C. Input to the control circuits 4A1 to 4C1. The first constant voltage circuit 3 lowers the input power supply voltage VIN to a desired power supply voltage VDD, and supplies the power supply voltage VDD to the output stages 4A2 to 4C2 of the second constant voltage circuits 4A to 4C.

  The second constant voltage circuits 4A to 4C operate the control circuits 4A1 to 4C1 with the input power supply voltage VIN, and output with control signals S1a to S1c (detailed in FIG. 3) output from the control circuits 4A1 to 4C1. By controlling the stages 4A2 to 4C2, the power supply voltage VDD supplied to the output stages 4A2 to 4C2 is converted into the respective power supply voltages VOUTa to VOUTc required by each circuit unit in the subsequent stage and output.

  In this way, the power supply circuit 1 can convert the power supply voltage VIN supplied from the DC power supply 2 into the respective power supply voltages VOUTa to VOUTc required by the subsequent circuit units and output them.

  The power supply circuit 1 operates only necessary circuits (for example, the second constant voltage circuits 4A and 4B) among the second constant voltage circuits 4A to 4C in accordance with the operation state of each circuit unit in the subsequent stage. Thus, only necessary power supply voltages (for example, power supply voltages VOUTa and VOUTb) can be output.

  Further, the power supply circuit 1 includes signals (hereinafter also referred to as synchronization signals) S2a to S2c synchronized with the control signals S1a to S1c output from the control circuits 4A1 to 4C1 included in the second constant voltage circuits 4A to 4C. Is fed back from each of the second constant voltage circuits 4A to 4C to the first constant voltage circuit 3 (details will be described later).

(2) Configuration of First and Second Constant Voltage Circuits First, the circuit configuration of the first constant voltage circuit 3 is shown in FIG. The first constant voltage circuit 3 lowers the power supply voltage VIN input via the input terminal 10 to an arbitrary power supply voltage VDD, and supplies it to the second constant voltage circuits 4A to 4C via the output terminal 11. The switching regulator is supplied to the output stages 4A2 to 4C2, and includes a switching transistor 12, a rectifying transistor 13, a smoothing circuit 14, and a control circuit 15.

  The switching transistor 12 is a pMOS type FET, and its source is connected to the input terminal 10 and its gate is connected to the control circuit 15.

  The rectifying transistor 13 is an nMOS type FET, the drain thereof is connected to the drain of the switching transistor 12, the gate thereof is connected to the control circuit 15, and the source is grounded.

  The switching transistor 12 and the rectifying transistor 13 are alternately turned on / off by a control signal supplied from the control circuit 15.

  The smoothing circuit 14 includes a coil 14A and a capacitor 14B. One end of the coil 14A is connected to the drain of the switching transistor 12 (the drain of the rectifying transistor 13), and the other end of the coil 14A is a capacitor. The one end of 14B is connected to the output terminal 11, and the other end of the capacitor 14B is grounded.

  Here, in the first constant voltage circuit 102, when the rectifying transistor 13 is turned off and the switching transistor 12 is turned on, the input terminal 10 and one end of the coil 14A are electrically connected via the switching transistor 12. . As a result, the power supply voltage VIN supplies energy to the coil 14A and the capacitor 14B, and also supplies energy to the output stages 4A2 to 4C2 of the second constant voltage circuits 4A to 4C via the output terminal 11. To do. At this time, energy is stored in the coil 14A, and the capacitor 14B is charged.

  From this state, when the switching transistor 12 is turned off and the rectifying transistor 13 is turned on, the input terminal 10 and one end of the coil 14A are electrically disconnected. As a result, back electromotive force is generated at both ends of the coil 14A and the rectifying action of the rectifying transistor 13 works, so that the energy stored in the coil 14A passes through the output terminal 11 to the second constant voltage circuits 4A to 4A. It is supplied to 4C output stages 4A2 to 4C2. At this time, the capacitor 14B is discharged.

  As described above, the first constant voltage circuit 3 alternately turns on / off the switching transistor 12 and the rectifying transistor 13 to cause the coil 14A and the capacitor 14B to repeatedly charge and discharge, resulting in the potential of the output terminal 11 being changed. And a stable power supply voltage VDD can be output from the output terminal 11.

  Further, the first constant voltage circuit 3 inputs synchronization signals S2a to S2c fed back from the second constant voltage circuits 4A to 4C to the control circuit 15 via feedback input terminals TIa to TIc.

  Here, for convenience of explanation, before describing the details of the control circuit 15 of the first constant voltage circuit 3, the circuit configurations of the second constant voltage circuits 4A to 4C will be described.

  The circuit configuration of the second constant voltage circuits 4A to 4C is shown in FIG. Since the circuit configurations of the second constant voltage circuits 4A to 4C are all the same, only the second constant voltage circuit 4A will be described here, and the second constant voltage circuits 4B and 4C will be described. Is omitted.

  The second constant voltage circuit 4A receives a power supply voltage VDD input from the first constant voltage circuit 3 via the first input terminal 20 as a desired power supply voltage required by a subsequent circuit unit (not shown). This is a series regulator that converts it to VOUTa and outputs it from the output terminal 21 to the subsequent circuit portion, and includes an output control transistor 22, a voltage dividing circuit 23, and a control circuit 4A1. Incidentally, in this case, the output control transistor 22 and the voltage dividing circuit 23 become the output stage 4A2.

  The output control transistor 22 is a pMOS type FET, the source thereof is connected to the first input terminal 20, the gate is connected to the control circuit 4A1, and the source is further connected to the output terminal 21 and the voltage dividing circuit 23. And connected to.

  The voltage dividing circuit 23 includes two resistors 23A and 23B connected in series between the output terminal 21 (the source of the output control transistor 22) and GND, and outputs the power supply voltage VOUTa to the resistors 23A and 23B. The voltage is divided by the resistance ratio, and the resulting divided voltage V2 is supplied to the control circuit 4A1.

  The control circuit 4A1 includes a reference voltage generation circuit 24 and a differential amplifier 26 that operates with the power supply voltage VIN supplied from the DC power supply 2 through the second input terminal 25, and is supplied from the voltage dividing circuit 23. The divided voltage V2 is input to the non-inverting input terminal of the differential amplifier 25, and the reference voltage V2r from the reference voltage generating circuit 24 is input to the inverting input terminal of the differential amplifier 25.

  The differential amplifier 26 amplifies the differential voltage between the input divided voltage V2 and the reference voltage V2r, and supplies the amplified differential voltage to the gate of the output control transistor 22 as the control signal S1a.

  Thus, when the divided voltage V2 becomes lower than the reference voltage V2r, the control circuit 4A1 reduces the level (voltage) of the control signal S1a to reduce the power supply voltage VOUTa. When the output control transistor 22 is controlled so as to increase, and the divided voltage V2 becomes higher than the reference voltage V2r, the level of the control signal S1a is increased because the power supply voltage VOUTa becomes higher than a desired voltage at this time. The output control transistor 22 is controlled so that the power supply voltage VOUTa decreases.

  As a result, the control circuit 4A1 can output a desired power supply voltage VOUTa from the output terminal 21.

  The control circuit 4A1 is also configured to output a signal (that is, a synchronization signal) S2a synchronized with the control signal S1a from the differential amplifier 26. The synchronization signal S2a is output to the first signal via the feedback output terminal TOa. The constant voltage circuit 3 is fed back.

  That is, the control circuit 4A1 feeds back to the first constant voltage circuit 3 the power supply voltage VOUTa by feeding back to the first constant voltage circuit 3 a synchronization signal S2a synchronized with the control signal S1a that is changed according to the fluctuation of the power supply voltage VOUTa. It is made to be able to convey the fluctuations.

  As described above, the second constant voltage circuit 4A outputs the desired power supply voltage VOUTa and feeds back the synchronization signal S2a indicating the fluctuation of the power supply voltage VOUTa to the first constant voltage circuit 3.

  Similarly, the second constant voltage circuits 4B and 4C also output desired power supply voltages VOUTb and VOUTc, and feed back synchronization signals S2b and S2c indicating fluctuations in the power supply voltages VOUTb and VOUTc to the first constant voltage circuit 3. It is made to do.

  Incidentally, these synchronization signals S2a, S2b, and S2c are set so that the levels thereof become smaller as the corresponding power supply voltages VOUTa, VOUTb, and VOUTc are larger. That is, these synchronization signals S2a, S2b, and S2c are, for example, control signal S1a + predetermined voltage V (> VOUTa, VOUTb, VOUTc) −power supply voltage VOUTa, control signal S1b + predetermined voltage V−power supply voltage VOUTb, and control signal S1c + predetermined voltage. It is set to be V-power supply voltage VOUTc.

  Actually, the levels of the control signals S1a, S1b, and S1c are almost zero at the normal time. For example, when the relationship of the power supply voltage VOUTc> VOUTb> VOUTa is established, the synchronization signal S2a> S2b> S2c is satisfied. That is, the synchronization signals S2a, S2b, and S2c are signals that indicate fluctuations and magnitudes of the corresponding power supply voltages VOUTa, VOUTb, and VOUTc.

  Here, the control circuit 15 (FIG. 2) of the first constant voltage circuit 3 will be described. The control circuit 15 includes a reference voltage generation circuit 15A, a differential amplifier 15B, a triangular wave generation circuit 15C, a comparator 15D, and a drive circuit 15E, and is used for feedback from the second constant voltage circuits 4A to 4C. The synchronization signals S2a, S2b, and S2c input through the input terminals TIa to TIc are input to the first, second, and third inverting input terminals of the differential amplifier 15B.

  Further, the differential amplifier 15B receives the reference voltage V1r from the reference voltage generation circuit 15A at its non-inverting input terminal. As a result, the differential amplifier 15B amplifies the differential voltage between the reference signal V1r and the signal having the lowest level among the synchronization signals S2a, S2b, and S2c, and supplies the amplified differential voltage as an output signal to the comparator 15D. To do.

  The comparator 15D inputs the output signal supplied from the differential amplifier 15B to the inverting input terminal, and inputs the triangular wave signal supplied from the triangular wave generating circuit 116C to the non-inverting input terminal.

  As a result, the comparator 15D compares the output signal supplied from the differential amplifier 15B with the triangular wave signal. When the level of the output signal becomes lower than the level of the triangular wave signal, the comparator 15D becomes high (High) level and becomes low. A PWM (Pulse Width Modulation) signal having a (Low) level is generated, and this PWM signal is output to the drive circuit 15E.

  The drive circuit 15E has a first output terminal connected to the gate of the switching transistor 12, and a second output terminal connected to the gate of the rectifying transistor 13. The drive circuit 15E outputs a control signal for turning on the switching transistor 12 and turning off the rectifying transistor 13 when the PWM signal supplied from the comparator 15D is at a low level, and when the PWM signal is at a high level. A control signal for turning off the switching transistor 12 and turning on the rectifying transistor 13 is output.

  Thus, in the first constant voltage circuit 3, the signal having the lowest level among the synchronization signals S2a, S2b, and S2c fed back by controlling the ON time of the switching transistor 12 by the control circuit 15 matches the reference voltage V1r. To work.

  Here, the internal configuration of the above-described differential amplifier 15B will also be described. As shown in FIG. 4, the differential amplifier 15B includes a non-inverting input differential transistor 30, three inverting input differential transistors 31a, 31b, and 31c connected in parallel, and these differential transistors. A current mirror circuit 32 serving as a load of 30 and 31a to 31c and an amplifying transistor 33 are provided.

  The differential transistor 30 for non-inverting input is a pMOS type FET, and a reference voltage V1r is supplied to its gate. Also, the three inverting input differential transistors 31a, 31b, and 31c connected in parallel are pMOS-type FETs, and the synchronization signals S2a, S2b, and S2c are supplied to the respective gates.

  In the pMOS-type FET, the smaller the voltage supplied to the gate, the more the source and drain are opened (that is, more current flows between the source and drain). For example, among the synchronization signals S2a, S2b, and S2c, Of the inverting input differential transistors 31a, 31b, and 31c, the source and drain of the differential transistor 31c to which the synchronization signal S2c is supplied to the gate is most open.

  As a result, the synchronization signal S2c supplied to the gate of the differential transistor 31c becomes a differential object with respect to the reference voltage V1r, and the reference voltage is generated between the differential transistor 30 for non-inverting input and the differential transistor 31c for inverting input. A differential voltage between V1r and the synchronization signal S2c is detected. The differential voltage is amplified via the current mirror circuit 32 and the amplifying transistor 33 and output as an output signal.

  Thus, the differential amplifier 15 has a configuration in which a plurality of inverting input differential transistors made of pMOS-type FETs are connected in parallel. The differential voltage between the signal having the lowest level and the reference voltage V1r can be amplified and output.

(3) Operation and Effect In the above configuration, the power supply circuit 1 operates, for example, all of the second constant voltage circuits 4A, 4B, and 4C. When the power supply voltages VOUTa, VOUTb, and VOUTc satisfying the power supply voltage VOUTc>VOUTb> VOUTa are output from 4C, the fluctuations of the power supply voltages VOUTa, VOUTb, and VOUTc are indicated, and at this time, the synchronization signal S2a>S2b> S2c is satisfied. The synchronization signals S2a, S2b, and S2c are fed back from the second constant voltage circuits 4A, 4B, and 4C to the first constant voltage circuit 3.

  The first constant voltage circuit 3 matches the synchronization signal S2c having the lowest level with the reference voltage V1r among the synchronization signals S2a, S2b, and S2c fed back from the second constant voltage circuits 4A, 4B, and 4C. It works to let you.

  As a result, the first constant voltage circuit 3 at this time outputs the supplied power supply voltage VIN, and the second constant voltage circuits 4A, 4B, and 4C output the power supply voltages VOUTa, VOUTb, and VOUTc, respectively. It is converted into a power supply voltage VDD that is the maximum value (about power supply voltage VOUTc + 0.3 [V]) of the minimum required minimum voltage, and is output.

  Further, for example, when the power supply circuit 1 stops the operation of the second constant voltage circuit 4C from this state and shifts to the state in which only the power supply voltages VOUTa and VOUTb are output from the second constant voltage circuits 4A and 4B, The synchronization signals S2a and S2b are fed back to the first constant voltage circuit 3 from the constant voltage circuits 4A and 4B.

  At this time, since the synchronization signal S2a> S2b, the first constant voltage circuit 3 operates so that the synchronization signal S2b having a low level matches the reference voltage V1r.

  As a result, the first constant voltage circuit 3 at this time uses the power supply voltage VDD as the minimum required for the second constant voltage circuits 4A and 4B to output the power supply voltages VOUTa and VOUTb, respectively. The voltage is changed to the maximum value (power supply voltage VOUTb + 0.3 [V] or so).

  Further, for example, when the power supply circuit 1 stops the operation of the second constant voltage circuit 4B from this state and shifts to a state in which only the power supply voltage VOUTa is output from the second constant voltage circuit 4A, the first constant voltage circuit 3 Is changed to the minimum voltage (about power supply voltage VOUTa + 0.3 [V]) necessary for the second constant voltage circuit 4A to output the power supply voltage VOUTa.

  As described above, the power supply circuit 1 generates the synchronization signals S2a, S2b, and S2c indicating the fluctuations and magnitudes of the power supply voltages VOUTa, VOUTb, and VOUTc from the second constant voltage circuits 4A, 4B, and 4C. The voltage circuit 3 is fed back, and the power supply voltage VDD is changed from the first constant voltage circuit 3 according to the synchronization signals S2a, S2b, and S2c.

  As a result, the power supply circuit 1 always obtains the power supply voltage VDD that is the maximum value among the minimum voltages required by the second constant voltage circuits 4A, 4B, and 4C from the first constant voltage circuit 3 at all times. Can be output.

  In addition, the power supply circuit 1 supplies synchronization signals S2a, S2b, and S2c synchronized with the control signals S1a, S1b, and S1c generated by the second constant voltage circuits 4A, 4B, and 4C to the first constant voltage circuit 3. This is a configuration in which a feedback path is simply added, and does not require a separate circuit such as a conventional external circuit or a voltage switching control circuit, and thus can be realized with a simple circuit configuration.

  Further, in the power supply circuit 1, the control circuits 4A1, 4B1, and 4C1 of the second constant voltage circuits 4A, 4B, and 4C are not supplied from the power supply voltage VDD supplied from the first constant voltage circuit 3, but from the DC power supply 2. The operation is performed with the supplied power supply voltage VIN.

  In practice, for example, when the control circuits 4A1, 4B1, and 4C1 are operated at the power supply voltage VDD, the power supply voltages VOUTa, VOUTb, and VOUTc must be extremely low. The power supply voltage VDD supplied to 4B1 and 4C1 also becomes extremely low, and as a result, the operations of the control circuits 4A1, 4B1, and 4C1 may become unstable.

  Therefore, if the control circuits 4A1, 4B1, and 4C1 are operated with the power supply voltage VIN that is always stable and equal to or higher than the power supply circuit 1, these operations can be stabilized, for example, the power supply voltage VOUTa, Even when the voltages of VOUTb and VOUTc must be extremely low, it is possible to sufficiently cope with this, and the power consumption can be surely reduced.

  According to the above configuration, the power supply circuit 1 responds to the synchronization signals S2a to S2c indicating the fluctuations and magnitudes of the power supply voltages VOUTa to VOUTc fed back from the second constant voltage circuits 4A to 4C to the first constant voltage circuit 3. Thus, by changing the power supply voltage VDD output from the first constant voltage circuit 3, the power supply output from the first constant voltage circuit 3 can be provided without separately providing a conventional external circuit, voltage switching control circuit, or the like. Since the voltage VDD can always be changed to the minimum voltage necessary for the second constant voltage circuits 4A to 4C to output the power supply voltages VOUTa to VOUTc, the first voltage without changing the circuit configuration. Therefore, it is possible to reduce wasteful power consumed by the second constant voltage circuits 4A to 4C, and thus it is possible to reliably reduce power consumption while having a simple configuration.

(4) Other Embodiments In the above-described embodiment, the power supply circuit 1 is provided with the second constant voltage circuits 4A, 4B, and 4C that output predetermined power supply voltages VOUTa, VOUTb, and VOUTc. Although the case has been described, the present invention is not limited to this. For example, at least one second constant voltage circuit whose output voltage is variable may be provided.

  In such a second constant voltage circuit with variable output voltage, for example, a variable resistor is used in the voltage dividing circuit of the output stage, so that the output voltage is changed to the power supply voltage VOUTa, VOUTb, or VOUTc. For example, the output voltage is changed to the power supply voltage VOUTa, VOUTb, or VOUTc in accordance with the operation state of the circuit unit in the subsequent stage.

  In this way, even when one of the second constant voltage circuits changes the output voltage to the power supply voltage VOUTa, VOUTb, or VOUTc, this change is fed back to the first constant voltage circuit 3 as the above-described synchronization signal. As a result, the power supply voltage VDD output from the first constant voltage circuit 3 can always be changed to the minimum voltage necessary for the second constant voltage circuit to output the output voltage.

  In the above embodiment, the control circuits 4A1, 4B1, and 4C1 of the second constant voltage circuits 4A, 4B, and 4C are operated with the power supply voltage VIN supplied from the DC power supply 2. As described above, for example, if there is no situation where the voltages of the power supply voltages VOUTa, VOUTb, and VOUTc are extremely low, the control circuits 4A1, 4B1, and 4C1 are supplied from the first constant voltage circuit 3. You may make it operate | move with the power supply voltage VDD.

  Further, in the above-described embodiment, the power supply voltage VDD output from the first constant voltage circuit 3 is the minimum necessary for the second constant voltage circuits 4A to 4C to always output the power supply voltages VOUTa to VOUTc. Although the case where the voltage is changed to the voltage has been described, the present invention is not limited to this, and the power supply voltage VDD is an optimum voltage required by the second constant voltage circuits 4A to 4C of the power supply circuit 1. What should be changed.

  Furthermore, in the above-described embodiment, as the signals indicating the values of the power supply voltages VOUTa, VOUTb, and VOUTc are synchronized with the control signals S1a, S1b, S1c and the corresponding power supply voltages VOUTa, VOUTb, and VOUTc are larger, Although the case where the synchronization signals S2a, S2b, and S2c set so that the level is reduced is described, the present invention is not limited to this, and the values of the power supply voltages VOUTa, VOUTb, and VOUTc are shown. Other signals may be used as long as the signals are generated by the second constant voltage circuits 4A to 4C.

  Further, in the above-described embodiment, the power supply voltage VIN from the DC power supply 2 is converted into the power supply voltage VDD as the first voltage and is stepped down to the first constant voltage circuit 3 which is a first voltage conversion circuit that outputs the first voltage conversion circuit. However, the present invention is not limited to this. For example, a step-up switching regulator or a step-up / step-down switching regulator may be used for the first constant voltage circuit 3. As described above, even when a step-up switching regulator or a step-up / step-down switching regulator is used, a power supply circuit capable of reducing power consumption can be realized by the technical idea described in the above embodiment.

  Furthermore, in the above-described embodiment, the second voltage conversion circuit is a second voltage conversion circuit that converts the power supply voltage VDD from the first constant voltage circuit 3 into power supply voltages VOUTa to VOUTc as the second voltages and outputs them. Although the case where the step-down type series regulator is used for the constant voltage circuits 4A to 4C has been described, the present invention is not limited to this. For example, the step-down type switching regulator or the step-up / step-down circuit is used for the second constant voltage circuits 4A to 4C. A pressure-type switching regulator may be used, and as described above, even when a step-down switching regulator or a step-up / step-down switching regulator is used as the second constant voltage circuits 4A to 4C, the above-described embodiment has been described. With the technical idea, a power supply circuit that can reduce power consumption can be realized.

  Further, in the above-described embodiment, the synchronization signals S2a to S2c as signals indicating the values of the power supply voltages VOUTa to VOUTc output from the second constant voltage circuits 4A to 4C are output from the second constant voltage circuits 4A to 4C. The case where the differential amplifier 26, the feedback output terminals TOa to IOc, and the feedback input terminals TIa to TIc are used as feedback means for feedback to the first constant voltage circuit 3 has been described. The invention is not limited to this, and feedback means having various configurations may be used.

  The present invention can be widely used for a power supply circuit that converts a supplied power supply voltage into a desired power supply voltage.

It is a basic diagram which shows the whole structure of the power supply circuit in this Embodiment. It is a basic diagram which shows the structure of the 1st constant voltage circuit in this Embodiment. It is a basic diagram which shows the structure of the 2nd constant voltage circuit in this Embodiment. It is a basic diagram which shows the internal structure of a differential amplifier. It is a basic diagram which shows the structure of the conventional power supply circuit. It is a basic diagram which shows the structure of the conventional 1st constant voltage circuit. It is a basic diagram which shows the structure of the 2nd conventional constant voltage circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,100 ... Power supply circuit, 2, 101 ... DC power supply, 3, 102 ... First constant voltage circuit, 4A, 4B, 4C, 103A, 103B, 103C ... Second constant voltage circuit, 15B, 26, 124B... Differential amplifier, S1a, S1b, S1c ... Control signal, S2a, S2b, S2c ... Sync signal, TIa, TIb, TIc ... Feedback input terminal, TOa, TOb, TOc ... For feedback Output terminal.

Claims (9)

A first voltage conversion circuit that converts a power supply voltage from a DC power supply into an arbitrary first voltage and outputs the first voltage, and converts the first voltage from the first voltage conversion circuit into an arbitrary second voltage A power supply circuit having at least one second voltage conversion circuit that outputs the
Feedback means for feeding back a signal indicating the value of the second voltage output from the second voltage conversion circuit from the second voltage conversion circuit to the first voltage conversion circuit;
The first voltage conversion circuit includes:
The power supply circuit, wherein the first voltage is changed in accordance with a signal indicating the value of the second voltage fed back from the second voltage conversion circuit by the feedback means. The first voltage conversion circuit includes:
In response to a signal indicating the value of the second voltage fed back from the second voltage converter circuit by the feedback means, the second voltage converter circuit supplies the second voltage. The power supply circuit according to claim 1, wherein the power supply circuit is changed so as to have a minimum voltage necessary for output. The first voltage conversion circuit includes:
In response to a signal indicating the value of the second voltage fed back from the second voltage conversion circuit by the feedback means, each of the plurality of second voltage conversion circuits receives the first voltage. 2. The power supply circuit according to claim 1, wherein the power supply circuit is changed so as to have a maximum value of minimum voltages required to output the voltage of 2. The power supply circuit according to claim 1, wherein the second voltage conversion circuit is operated with the power supply voltage from the DC power supply. The power supply circuit according to claim 1, wherein the second voltage conversion circuit is operated with the first voltage from the first voltage conversion circuit. The first voltage conversion circuit includes:
The power supply circuit according to claim 1, wherein the power supply circuit is a step-down switching regulator. The first voltage conversion circuit includes:
The power supply circuit according to claim 1, wherein the power supply circuit is a step-up switching regulator. The first voltage conversion circuit includes:
The power supply circuit according to claim 1, wherein the power supply circuit is a step-up / step-down switching regulator. The second voltage conversion circuit includes:
The power supply circuit according to claim 1, wherein the power supply circuit is a step-down series regulator, a step-down switching regulator, a step-up switching regulator, or a step-up / step-down switching regulator.

Images