JP2006115183A - Packet telemetry processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein frame timing signals are usually distributed to the mounted apparatus, a system is utilized where packets outputted in a previously decided period so as not to get congested are simply subjected to time-division processing, so that the output timing of the packets output from the apparatuses is required to be adjusted, and a new original design must be carried out for each satellite. <P>SOLUTION: A buffer memory used for a packet telemetry is provided to each of the mounted apparatuses, and when the packet telemetry outputs of the mounted apparatuses get congested, the packets are subjected to multiplexing based on the priority of the mounted apparatuses designated through a packet priority table. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a packet telemetry processing device mounted on an artificial satellite.

When packet telemetry from the packet telemetry source is stopped for a long time, it is necessary on the ground because a plurality of received packet telemetry data less than the amount of data required for the transfer frame stays in the buffer for a long time without being output. If telemetry data becomes unavailable at the timing and packet telemetry does not resume, the telemetry data staying in the buffer cannot be output, so the total amount of data received from multiple packet telemetry is equal to the period of the output data. Even when the amount of data is less than that, the remaining packet telemetry that does not reach the frame is multiplexed and output within a fixed time at the timing of the delay timeout signal obtained by delaying the timeout signal from the timer circuit using the delay circuit. Things It is shown (for example, see Patent Document 1.).

JP 11-98184 A (FIG. 1)

  Conventionally, a timing signal is distributed to an on-board device, and a packet that is output during a predetermined period is simply time-division multiplexed so as not to be congested. There is a problem that a packet output timing adjustment work is required and a new design unique to each satellite must be performed.

  The present invention has been made in order to solve the above-described problem. A packet telemetry buffer memory is provided for each mounted device, and packet multiplexing is normally performed even when the packet telemetry output of each mounted device is congested. An object of the present invention is to obtain an apparatus for performing a conversion process.

  The packet telemetry processing device of the present invention outputs a timing signal for each of a plurality of mounted devices, and a packet multiplexing circuit that multiplexes a plurality of packet data output from the corresponding mounted devices in a time division manner, A frame multiplexing circuit that multiplexes frame data from a plurality of frame buffers that store packet data multiplexed by the packet multiplexing circuit and packet data for each other mounted device, and the frame multiplexing circuit includes a priority table. And a frame priority table that is controlled based on the priority information.

  A buffer memory for packet telemetry is provided for each installed device, and a device that normally performs packet multiplexing processing can be obtained even when the packet telemetry output of each installed device is congested. There is an effect that a usable device is obtained.

  Artificial satellites are equipped with devices with various functions. These devices include bus devices with the purpose of maintaining satellite functions such as attitude control and thermal control of satellites, high-power transmitters for communication broadcasting satellites, remote sensors for observation satellites, etc. And mission equipment (payload equipment) for achieving the original mission as a satellite.

  The bus device receives and decodes command signals transmitted from the ground, multiplexes the command processing device that transmits the command signals to each device, and the telemetry signals output from each device in the satellite. A device called a telemetry processing device that performs transmission is included.

  Here, the command signal is a signal transmitted from the ground to instruct the operation state of each device of the artificial satellite. On the contrary, the command signal is artificial to notify the operation state of each device in the satellite. A signal transmitted from the satellite to the ground is called a telemetry signal.

  In recent data handling processing, CSDDS (Consultative Committee for Space Data Systems) recommendation for interfacing with payload devices in a packet format has become mainstream.

  In telemetry processing according to the CCSDS recommendation, variable-length packet telemetry output from a payload device or bus device is multiplexed into a fixed-length frame called a VCDU (Virtual Channel Data Unit) (the packet length is larger than the data area of the VCDU). If it is large, the packet is divided into a plurality of frames and transmitted.

  Telemetry data includes HK (House Keeping) data for notifying the status of bus devices and payload devices, and observation data and calibration data of payload devices. In general, observation data, calibration data, etc. are recorded in a data recorder when not visible, and reproduced and transmitted when visible. Further, the HK data includes a steady monitor item that is transmitted in real time when visible, and a non-steady monitor item that is transmitted on demand when necessary.

Embodiment 1 FIG.
FIG. 1 is a diagram showing Embodiment 1 of a packet telemetry processing apparatus according to the present invention, wherein 1 is a mounted device A, 2 is a mounted device B, 3 is a mounted device C, 4 is a mounted device D, and 5 is a mounted device E. , 6 is a packet multiplexing circuit, 7 is a frame buffer A, 8 is a frame buffer B, 9 is a frame buffer C, 10 is a frame multiplexing circuit, 11 is a frame priority table, 16 is packet data of the mounted device A, 17 Is the packet data of the mounted device C, 18 is the packet data of the mounted device D, 20 is the packet data of the mounted device E, 30 is the multiplexed packet data of the packet multiplexing circuit, and 31 is the frame Buffer A transmission request signal, 32 is a transmission instruction signal for frame buffer A, 33 is frame data of frame buffer A, and 34 is a frame buffer. Transmission request signal for frame B, 35 for transmission instruction signal for frame buffer B, 36 for frame data of frame buffer B, 37 for transmission request signal for frame buffer C, 38 for transmission instruction signal for frame buffer C, 39 for frame buffer C frame data, 40 is a multiplexed frame of the frame multiplexing circuit, 41 is frame priority table priority information from the frame priority table, 45 is a timing signal for the mounted device A, 46 is a timing signal for the mounted device B , 47 are timing signals for the mounted device C.

  The packet multiplexing circuit 6 outputs a timing signal 45 for the mounted device A to the mounted device A1, a timing signal 46 for the mounted device B to the mounted device B1, and a timing signal 47 for the mounted device C to the mounted device C1. On the other hand, the packet data 16 of the mounted device A output from the mounted device A1, the packet data 17 of the mounted device B output from the mounted device B2, and the packet data 18 of the mounted device C output from the mounted device C3. Multiplex into divisions.

  That is, the packet multiplexing circuit 6 multiplexes three types of packet data transmitted over physically different signal lines in a time-division manner by distributing timing signals to each mounted device at a timing that does not overlap in time. To do.

  The frame buffer A7 stores the multiplexed packet data 30 of the packet multiplexing circuit output from the packet multiplexing circuit 6, and when the multiplexed packet data 30 of the packet multiplexing circuit is received, the transmission request signal 31 of the frame buffer A Is output.

Similarly, the frame buffer B8 stores the packet data 19 of the mounted device D from the mounted device D4, and outputs the transmission request signal 34 of the frame buffer B when the packet data 19 of the mounted device D is received.
Similarly, the frame buffer C9 stores the packet data 20 of the mounted device E from the mounted device E5, and outputs the transmission request signal 37 of the frame buffer C when the packet data 20 of the mounted device E is received.

  Here, the packet data 19 of the mounted device D and the packet data 20 of the mounted device E are composed of a 6-byte header portion and a variable length data portion, and telemetry information of each mounted device is set in the data portion.

  When the frame multiplexing circuit 10 receives the frame buffer A transmission request signal 31 from the frame buffer A7, the frame buffer B transmission request signal 34 from the frame buffer B8, and the frame buffer C transmission request signal 37 from the frame buffer C9. Based on the priority information 41 of the frame priority table from the frame priority table 11, a transmission instruction signal 32 for the frame buffer A, a transmission instruction signal 35 for the frame buffer B, and a transmission instruction signal 38 for the frame buffer C are output.

  The frame buffer A7 is a buffer for generating the input packet data 16 of the variable-length mounted device A, the packet data 17 of the mounted device B, and the packet data 18 of the mounted device C as fixed-length frames. After data accumulates in the frame buffer A7 and reaches a predetermined fixed length, the frame buffer A7 sends the frame buffer A transmission request signal 31 to the frame multiplexing circuit 10, and then the frame buffer A7 receives the frame buffer A from the frame multiplexing circuit 10. The frame data 33 of the frame buffer A, which is the data stored in the frame buffer A 7 when the transmission instruction 32 is received, is output to the frame multiplexing circuit 10.

  Note that the input packet data 16 of the mounted device A, the packet data 17 of the mounted device B, and the packet data 18 of the mounted device C have variable lengths, and there may be a break in the fixed-length frame in the middle of each packet data. is there. In this case, since the packet data portion that has not entered the frame needs to be placed at the beginning of the next frame, the frame buffer A7 is composed of buffers for a plurality of frames.

Here, the frame data 33 of the frame buffer A is composed of a 6-byte header part, a 2-byte head packet position information part, and a fixed-length data part, and the packet data 16 of the mounted device A multiplexed in the data part. The packet data 17 of the mounted device B and the packet data 18 of the mounted device C are inserted.
In the head packet position information portion, the head position information of the packet excluding the packet that is entered from the middle in the data portion is set.

  Similarly, the frame buffer B8 outputs the frame data 36 of the frame buffer B when it receives the transmission instruction signal 35 for the frame buffer B, and similarly, the frame buffer C9 receives the transmission instruction signal 38 for the frame buffer C. At this time, the frame data 39 of the frame buffer C is output. The operations and configurations of the frame buffers B8 and C9 are the same as those of the frame buffer A7.

  The frame multiplexing circuit 10 multiplexes the frame data 33 of the frame buffer A, the frame data 36 of the frame buffer B, and the frame data 39 of the frame buffer C based on the priority information 41 of the frame priority table of the frame priority table 11. The multiplexed frame 40 of the frame multiplexing circuit is output.

  That is, in the frame multiplexing circuit 10, even when output requests from the frame buffer A7, the frame buffer B8, and the frame buffer C9 are congested, based on the information in the frame priority table as shown in FIG. For each output slot, control is performed so that data having a higher priority is preferentially output from the frame data 33 of the frame buffer A, the frame data 36 of the frame buffer B, and the frame data 39 of the frame buffer C.

FIG. 4 is a diagram illustrating an example of the frame priority table.
The frame priority table defines the timing at which one frame is output on the time axis as one slot, and defines which frame buffer is preferentially output for each slot.

In FIG. 4, in slot 1, the priority is in the order of frame data A, B, C.
When the frame data A, B, and C from the frame buffers A, B, and C come at the same time, the frame data A is output, and the frame data B and C are output after the next slot. Will be.

  In slot 2, the priority is in the order of the frame data A, C, B. Therefore, when the frame data A, B, C from the frame buffers A, B, C come simultaneously, first, the frame data A is Since the frame data C and B are output after the next slot, they are held in each frame buffer.

  In slot 3, since the priorities are in the order of frame data A, B, and C, when the frame data A, B, and C from the frame buffers A, B, and C come simultaneously, first, the frame data A is Since the frame data B and C are output after the next slot, they are held in each frame buffer.

  In slot 4, the priority is in the order of frame data B, A, and C. Therefore, when the frame data A, B, and C from the frame buffers A, B, and C come simultaneously, first, the frame data B is Since the frame data A and C are output after the next slot, they are held in each frame buffer.

  In slot 5, the priority is in the order of frame data C, A, and B. Therefore, when the frame data A, B, and C from the frame buffers A, B, and C come simultaneously, first, the frame data C Since the frame data A and B are output after the next slot, they are held in each frame buffer.

  By considering the frequency of packet data output by each mounted device and appropriately setting the frame priority for each slot, it is possible to output data smoothly even during output congestion of each mounted device.

  The example shown in FIG. 4 is an example in which the largest amount of frame data A is output from the frame buffer A. In the slots 1 to 3, the setting of the frame A is increased. The same condition is repeated in the period of slot 5.

  As described above, for each of a plurality of mounted devices, a timing signal is output, and a plurality of packet data output from the corresponding mounted devices are multiplexed in a time division manner, and multiplexed. A frame multiplexing circuit that multiplexes frame data from a plurality of frame buffers that store data, and a frame priority table that controls the packet multiplexing circuit based on priority information in the priority table, for each mounted device. A buffer memory for packet telemetry is provided, and there is an effect that a device that normally performs packet multiplexing processing can be obtained even when the packet telemetry output of each mounted device is congested.

Embodiment 2. FIG.
FIG. 2 is a diagram showing a second embodiment of the packet telemetry processing apparatus of the present invention, wherein 12 is a packet buffer A, 13 is a packet buffer B, 14 is a packet buffer C, 15 is a packet priority table, and 21 is a packet buffer. A is a transmission request signal for A, 22 is a transmission instruction signal for packet buffer A, 23 is packet data for packet buffer A, 24 is a transmission request signal for packet buffer B, 25 is a transmission instruction signal for packet buffer B, and 26 is packet buffer B Packet data, 27 is a transmission request signal of the packet buffer C, 28 is a transmission instruction signal for the packet buffer C, 29 is packet data of the packet buffer C, 42 is priority information of the packet priority table, 48 is a packet priority table Mode selection signals 1-11 16～20,30～41 is the same as the first embodiment.

  By inserting the packet buffer A12, the packet buffer B13, and the packet buffer C14 between the mounted device A1, the mounted device B2, and the mounted device C3 and the packet multiplexing circuit 6, respectively, the packet data 16 of the mounted device A and the mounted device B The packet data 17 and the packet data 18 of the mounted device C are temporarily buffered, and the packet multiplexing circuit 6 performs packet multiplexing processing based on the priority information 42 of the packet priority table from the packet priority table 15. .

  The packet multiplexing circuit 6 outputs a timing signal 45 for the mounted device A, a timing signal 46 for the mounted device B, and a timing signal 47 for the mounted device C. On the other hand, the packet data 16 of the mounted device A output from the mounted device A1. The packet data 17 of the mounted device B output from the mounted device B2 and the packet data 18 of the mounted device C output from the mounted device C3 are multiplexed.

  When the packet data 16 of the mounted device A is input to the packet buffer A12, a transmission request signal 21 of the packet buffer A is output to the packet multiplexing circuit 6. When the packet multiplexing circuit A6 receives the transmission request signal 21 of the packet buffer A from the packet buffer A12, the packet multiplexing circuit A6 multiplexes the packet data 16 of the mounted device A based on the priority information 42 of the packet priority table of the packet priority table 15. A transmission instruction signal 22 for the packet buffer A is transmitted to the packet buffer A12 at a possible timing. The packet buffer A12 outputs the packet data 23 of the packet buffer A at the timing when the transmission instruction signal 22 for the packet buffer A is received from the packet multiplexing circuit 6.

  The packet buffer B13 for buffering the packet data 17 of the mounted device B and the packet buffer C14 for buffering the packet data 18 of the mounted device C are multiplexed by the packet multiplexing circuit by performing the same processing as the packet buffer A12. Packet data 30 is generated.

Here, the packet priority table 15 is a table in which priorities are arranged for packets to be multiplexed, and the priority can be switched by a mode selection signal 48 of the packet priority table. Here, the mode selection signal 48 in the packet priority table is obtained by decoding a command signal sent from the ground to the satellite by the command processing unit.
The processing after the frame buffer A7 is the same as that of the first embodiment.

FIG. 5 is a diagram illustrating an example of a packet priority table.
In the packet priority table, each mode is assigned according to the priority of the output data of each mounted device depending on the operation phase of the satellite.

For example, in the case of an experimental satellite, mode 1 is used when the on-board device A is being tested, mode 2 is used when the on-board device B is being tested, and mode 3 is used when the on-board device C is being tested. It is.
By switching according to each mode determined in this way, the packet data A, B, C output from each mounted device and stored in the packet buffers A, B, C can be acquired in priority order when necessary. It becomes.

  For example, in mode 1, packet data A, B, C from packet buffers A, B, C can be acquired in the priority order, and in mode 2, packet data B, C, A in priority order. In the case of mode 3, the packet data C, A, and B can be acquired in the priority order.

  As described above, packet telemetry packet buffer memory for each mounted device and multiple packet buffer memories are output timing signals, and multiple packet data output from the corresponding mounted device is packet priority. Priority table for packet multiplexing circuit for multiplexing by table, frame multiplexing circuit for multiplexing frame data from a plurality of frame buffers for storing data multiplexed by packet multiplexing circuit, and packet multiplexing circuit With the frame priority table that is controlled based on the priority information of each device, a buffer memory for packet telemetry is provided for each installed device, and packet multiplexing processing is normally performed even when the packet telemetry output of each installed device is congested. There is an effect that an apparatus for performing can be obtained.

Embodiment 3 FIG.
FIG. 3 is a diagram showing Embodiment 3 of the packet telemetry processing apparatus of the present invention, 43 is a packet priority control circuit, 44 is priority information of the packet priority control circuit, transmission request from the packet buffer, and status signal during transmission processing 1-14 and 16-41 are the same as those described in the second embodiment.

  By inserting the packet buffer A12, the packet buffer B13, and the packet buffer C14 between the mounted device A1, the mounted device B2, and the mounted device C3 and the packet multiplexing circuit 6, respectively, the packet data 16 of the mounted device A and the mounted device B The packet data 17 and the packet data 18 of the mounted device C are temporarily buffered, and packet multiplexing processing is performed based on a method in which the packet priority control circuit 43 prioritizes the side that has received the transmission request first.

  When the packet data 16 of the mounted device A is input to the packet buffer A12, a transmission request signal 21 of the packet buffer A is output to the packet multiplexing circuit 6. When the packet multiplexing circuit 6 receives the transmission request signal 21 of the packet buffer A from the packet buffer A12, the packet multiplexing circuit 6 sends the packet data 16 of the mounted device A to the packet buffer A12 at a timing that can be multiplexed based on the instruction of the packet priority control circuit 43 The transmission instruction signal 22 for the packet buffer A is transmitted.

  The packet buffer A12 outputs the packet data 23 of the packet buffer A at the timing when the transmission instruction signal 22 for the packet buffer A is received from the packet multiplexing circuit 6. The packet buffer B13 for buffering the packet data 17 of the mounted device B and the packet buffer C14 for buffering the packet data 18 of the mounted device C are also subjected to the multiplexing of the packet multiplexing circuit by performing the same processing as the packet buffer A12. Packet data 30 is generated.

  Here, when the packet priority control circuit 43 receives a transmission request from a packet buffer to be multiplexed and a status signal 49 during transmission processing, it does not execute packet multiplexing processing of other buffers. If no other transmission request is received, a transmission instruction is immediately issued to the packet buffer, and the packet multiplexing process of another buffer is being executed, or another transmission request is already received. Performs the control to output the priority information 44 of the packet priority control circuit to the packet buffer when the processing is completed.

FIG. 6 is a diagram illustrating an example of a packet priority control circuit.
The packet transmission request buffer circuit 52 buffers the transmission request signal 21 of the packet buffer A, the transmission request signal 24 of the packet buffer B, and the transmission request signal 27 of the packet buffer C in the order of reception time, and is the earliest in waiting for transmission processing. The information 51 of the packet buffer that issued the transmission request is notified. The packet priority transmission instruction circuit 53 looks at the status signal 50 during packet transmission processing, and when the transmission processing is not being performed, the packet priority transmission instruction circuit 53 based on the information 51 of the packet buffer that has issued the transmission request earliest in the transmission processing waiting. The priority information 44 of the control circuit is output.
The processing after the frame buffer A7 is the same as that of the first embodiment.

  As described above, the packet telemetry packet buffer memory for each installed device and multiple packet buffer memories output timing signals and packet priority control for multiple packet data output from the corresponding installed devices. A priority multiplexing table, a packet multiplexing circuit for multiplexing by the circuit, a frame multiplexing circuit for multiplexing frame data from a plurality of frame buffers for storing data multiplexed by the packet multiplexing circuit, and a packet multiplexing circuit. By providing a frame priority table that is controlled based on the priority information of each device, a buffer memory for packet telemetry is provided for each installed device, and even if packet telemetry output of each installed device is congested, packets are normally transmitted. There is an effect that a device for performing multiplexing processing can be obtained.

It is a figure which shows Embodiment 1 of the packet telemetry processing apparatus of this invention. It is a figure which shows Embodiment 2 of the packet telemetry processing apparatus of this invention. It is a figure which shows Embodiment 3 of the packet telemetry processing apparatus of this invention. It is a figure which shows an example of a frame priority table. It is a figure which shows an example of a packet priority table. It is a figure which shows an example of a packet priority control circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Onboard equipment A, 2 Onboard equipment B, 3 Onboard equipment C, 4 Onboard equipment D, 5 Onboard equipment E, 6 Packet multiplexing circuit, 7 Frame buffer A, 8 Frame buffer B, 9 Frame buffer C, 10 Frame multiplexing Circuit, 11 frame priority table, 12 packet buffer A, 13 packet buffer B, 14 packet buffer C, 15 packet priority table, 16 packet data of mounted device A, 17 packet data of mounted device B, 18 of mounted device C Packet data, 19 Packet data of onboard equipment D, 20 Packet data of onboard equipment E, 21 Transmission request signal of packet buffer A, 22 Transmission instruction signal for packet buffer A, 23 Packet data of packet buffer A, 24 packets Buffer B transmission request signal, 25 packet buffer B transmission instruction signal, 26 packet buffer B packet data, 27 packet buffer C transmission request signal, 28 packet buffer C transmission instruction signal, 29 packet buffer C packet data, 30 Packet multiplexed circuit multiplexed packet data, 31 Frame buffer A transmission request signal, 32 Frame buffer A transmission instruction signal, 33 Frame buffer A frame data, 34 Frame buffer B transmission request signal, 35 Frame buffer B , 36 frame buffer B frame data, 37 frame buffer C transmission request signal, 38 frame buffer C transmission instruction signal, 39 frame buffer C Frame data, 40 frames multiplexed circuit multiplexed frame, 41 frame priority table priority information, 42 packet priority table priority information, 43 packet priority control circuit, 44 packet priority control circuit priority information, 45 Timing signal for device A, 46 timing signal for device B, 47 timing signal for device C, 48 mode selection signal in packet priority table, 49 transmission request from packet buffer and status signal during transmission processing, 50 packet transmission processing Medium status signal, 51 Information on the packet buffer that issued the transmission request earliest in waiting for transmission processing, 52 packet transmission request buffer circuit, 53 packet priority transmission instruction circuit.

Claims (3)

A packet multiplexing circuit that outputs a timing signal for each of a plurality of mounted devices and multiplexes a plurality of packet data output from the corresponding mounted devices in a time division manner,
A frame multiplexing circuit for multiplexing frame data from a plurality of frame buffers for storing packet data multiplexed by the packet multiplexing circuit and packet data for each other mounted device;
A frame priority table for controlling the frame multiplexing circuit based on priority information in the priority table;
A packet telemetry processing apparatus comprising: A packet buffer memory provided for packet telemetry for each installed device;
A packet multiplexing circuit that outputs a timing signal to a plurality of the packet buffer memories and multiplexes a plurality of packet data output from a corresponding mounted device;
In the packet multiplexing circuit, based on the priority for each mounted device, a packet priority table for performing multiplexing processing,
The packet telemetry processing device according to claim 1, further comprising: In the packet multiplexing circuit, receiving a transmission request from the packet buffer and a status signal during transmission processing, a packet priority control circuit for performing multiplexing processing;
The packet telemetry processing device according to claim 2, further comprising:

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