JP2006109294A - Quantization device and quantization method of pwm signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a quantization device and a quantization method which improve a quantization accuracy in quantization processing of a PWM signal. <P>SOLUTION: A quantization device (1) is provided with: an amplifier (16) inputting a PWM signal and generating a signal which is the inputted PWM signal multiplied by a predetermined number in the direction of a time axis; and a quantization circuit (6) receiving an output signal from the amplifier (16), quantizing a time width of "H" or "L" section of the output signal, and outputting the signal as a digital signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a quantization technique for converting an analog signal into a digital value, and more particularly to an apparatus and method for quantizing a pulse width of a PWM signal into a digital value.

  FIG. 10A is a configuration diagram of a conventional quantization circuit that quantizes (digitizes) the time width of the ON period ("H" period) or the OFF period ("L" period) of the PWM signal. is there. Note that the PWM signal is a signal obtained by changing the time width of an on (“H”) period or an off (“L”) period in a certain cycle in accordance with the amplitude of an analog signal. FIG. 10B illustrates the operation timing of the conventional quantization circuit. FIG. 10B shows an example in which the time width of the section Tx of the PWM signal is quantized.

  Conventionally, when the time width of the PWM signal is quantized (digitized), the logical sum (OR operation) of the PWM signal and a quantized clock having a predetermined period is taken to obtain the time width (Tx of the PWM signal). ) To obtain the number of clocks that appear (see FIG. 10B). That is, the OR gate 4 performs a logical OR operation between the PWM signal and the quantized clock, and the counter 3 counts the number of clock pulses appearing at the output of the OR gate 4 in one cycle of the PWM signal.

  The quantization accuracy of the quantization circuit 5 (that is, a value indicating how small the time width fluctuation of the PWM signal can be detected) is inversely proportional to the cycle of the quantization clock. An analog value smaller than the quantization accuracy is rounded down or rounded up at the time of quantization. Therefore, an error (quantization error) below the quantization accuracy is included in the quantization result. Hereinafter, the quantization error will be described in detail.

  FIGS. 11A to 11C are diagrams for explaining the quantization error when the time width of the section (Tx) in which the PWM signal is “L” is quantized. In the following description, the counter 3 counts at the rising timing of the quantization clock.

  With reference to FIG. 11A, a description will be given of the quantization error that occurs at the moment when the PWM signal changes from “H” to “L”, that is, at the start of quantization.

  In FIG. 11A, it is assumed that the PWM signal is changed from “H” to “L” during one period ΔTA of the quantization clock. In the period of ΔTA, the output of the counter 3 does not change regardless of the timing at which the PWM signal becomes “L”. In this case, the error at the start of quantization is a maximum of one cycle of the quantization clock.

  FIGS. 11B and 11C are diagrams for explaining an error that occurs at the moment when the PWM signal changes from “L” to “H”, that is, at the end of quantization. FIG. 11B shows a case where the PWM signal changes from “L” to “H” in the interval where the quantization clock is “H”, and in the interval of ΔTB, the PWM signal becomes “H”. The output of the counter 3 is not changed at any timing (it remains “6”). Further, FIG. 11C shows a case where the PWM signal becomes “H” in the “L” section of the quantization clock, and the timing when the PWM signal becomes “H” in the ΔTC section. The output of the counter 3 does not change at any timing (it remains “7”).

  Therefore, the error at the end of quantization is a maximum of ± 0.5 period of the quantization clock. That is, when quantization is performed by the quantization circuit having the configuration illustrated in FIG. 10, the quantization result may include a quantization error corresponding to +1.5 to −0.5 periods of the quantization clock.

An example using a quantization circuit is a digital PLL (see non-patent literature). Compared with a conventional analog PLL, the digital PLL has advantages such as chip size reduction, noise resistance, and easy replacement when changing processes.
“A Digitally Controlled PLL for SoC Applications”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL39.NO.5, MAY 2004)

  As described above, since the quantization accuracy is inversely proportional to the cycle of the quantization clock, it is conceivable to increase the frequency of the quantization clock in order to increase the quantization accuracy. However, increasing the frequency of the quantization clock is disadvantageous in terms of current consumption. In addition, there is a case where the upper limit of the frequency of the quantization clock is limited due to the restriction due to the upper limit of the allowable operating frequency of the counter 3 that counts the number of clocks, and the quantization accuracy cannot be increased.

  Further, in order to improve the jitter characteristic, which is an important characteristic of the PLL, it is necessary to increase the resolution (quantization accuracy) when quantizing the output signal of the phase comparator (PD) which is a PWM signal. However, it is desired to improve the quantization accuracy of the quantization circuit.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a quantization apparatus and a quantization method that improve the quantization accuracy during the quantization process of the PWM signal.

  The quantization apparatus according to the present invention receives a PWM signal, generates an amplifier that multiplies the input PWM signal by a predetermined number in the time axis direction, receives an output signal from the amplifier, and outputs a pulse of the output signal. A quantization circuit for quantizing the width.

  The quantization amplifier according to the present invention is used by being arranged in a preceding stage of a quantization circuit that quantizes the width of an analog signal in the time axis direction and converts it into a digital signal. The quantization amplifier receives a PWM signal and generates a signal obtained by multiplying the input PWM signal by a predetermined number in the time axis direction.

  The quantization method according to the present invention includes a step of inputting a PWM signal, generating a signal obtained by multiplying the input PWM signal by a predetermined number in the time axis direction, and quantizing the pulse width of the signal multiplied by the predetermined number to obtain a digital signal. Outputting.

  According to the present invention, by amplifying the input PWM signal in the time axis direction and then performing quantization by the quantization circuit, the size of the quantization clock with respect to the PWM signal can be relatively reduced, and the quantum signal can be substantially reduced. The quantization accuracy can be improved by acting in the same way as when the quantization clock is reduced.

  Embodiments of a quantization apparatus and a quantization method of the present invention will be described below with reference to the accompanying drawings.

Embodiment 1
(Configuration of quantizer)
FIG. 1 shows a configuration of a quantization apparatus according to the present invention. The quantization device 1 includes an inverter gate 2 that inverts a PWM signal, a delay amplifier (quantization amplifier) 16 that amplifies the inverted PWM signal in the time axis direction, and a quantum of the PWM signal amplified in the time axis direction. A quantization circuit 6 that performs quantization, and an oscillator 7 that generates a quantization clock.

  The quantization circuit 6 includes an OR gate 4 and a counter 3. The OR gate 4 calculates the logical sum of the delayed amplified output signal from the delay amplifier 16 and the quantized clock from the oscillator 7. The counter 3 counts the number of pulses that appear in the output of the OR gate 4 for each period of the PWM signal.

  The delay amplifier 16 is disposed in front of the quantization circuit 6 in order to improve the quantization accuracy, and has a function of amplifying the input PWM signal in the time axis direction. That is, the delay amplifier 16 expands the width of the input PWM signal in the time axis direction by a predetermined number of times.

  In the present embodiment, the original PWM signal is multiplied by a predetermined number in the time axis direction by the delay amplifier 16, and the quantization circuit 6 performs quantization using the signal. As described above, by multiplying the time width of the PWM signal by a predetermined number in the preceding stage of quantization, the size of the quantization clock with respect to the PWM signal can be made relatively small, which is substantially the same as when the quantization clock is made small. As a result, the quantization accuracy can be improved.

  FIG. 2 shows a detailed configuration of the delay amplifier 16. The delay amplifier 16 includes an N-stage circuit system (N is an integer, N = 1, 2, 3,...). The circuit system of each stage includes signal width detection circuits 9, 11, 13,..., RS latch type delay circuits 17, 18, 19,..., And delay chain circuits 10, 12, 14,. Specifically, the first-stage circuit system includes a first signal width detection circuit 9, a first RS latch type delay circuit 17, and a first delay chain circuit 10. The second stage circuit system includes a second signal width detection circuit 11, a second RS latch type delay circuit 18, and a second delay chain circuit 12. The third-stage circuit system includes a third signal width detection circuit 13, a third RS latch type delay circuit 19, and a third delay chain circuit 14. Note that FIG. 2 shows a configuration up to the third level for convenience of explanation. Outputs from each stage are connected by a NOR gate (adder) 15.

  The signal width detection circuits 9, 11, 13... Are circuits for detecting the time width of the PWM signal on section (“H” section) or off section (“L” section). The RS latch type delay circuits 17, 18, 19,... Are circuits for guaranteeing the minimum value of the pulse width in the “H” section of the input signal. Details of these circuits will be described later.

  The delay chain circuits 10, 12, 14... Generate temporally continuous signals reflecting the detection results based on the detection results by the signal width detection circuits 9, 11, 13. The n-th delay chain circuit includes (n−1) delay elements. Each delay element has a delay time TD. For example, the second delay chain circuit 12 includes one delay element 20, and the third delay chain circuit 14 includes two delay elements 20.

  The outputs from the delay chain circuits 10, 12, 14... Of each stage and the PWM signal input via the inverter 2 are input to the NOR gate 15, and the logical sum of these signals is calculated and output as a delayed amplified output signal. The The delayed amplification output signal is a signal obtained by amplifying the original PWM signal by a predetermined factor in the time axis direction.

(Signal width detection circuit)
Details of the signal width detection circuits 9, 11, 13... Will be described. The signal width detection circuits 9, 11, 13... Detect how many times the signal width (pulse width) of the input PWM signal is based on the delay time TD of the delay element 20. For example, the first signal width detection circuit 9 detects that the signal width of the PWM signal is one or more times the delay time TD, and the second signal width detection circuit 11 detects that the signal width of the PWM signal is the delay time. The third signal width detection circuit 13 detects that the signal width of the PWM signal is three times or more of the delay time TD. Similarly, the n-th signal width detection circuit detects that the signal width of the PWM signal is n times or more of the delay time TD.

  FIG. 4 shows a specific configuration of the signal width detection circuits 9, 11, 13,. In the signal width detection circuit shown in FIG. 4, the drain and source of the P-channel MOS transistor and the N-channel MOS transistor are connected in common to constitute one switch. By using two of these switches and turning on only one of the switches based on the PWM signal, the signal from the delay element 20 or the ground potential is output. Thereby, the three-terminal switch used in the configuration of the signal width detection circuit shown in FIG. 2 can be realized. FIG. 5 shows another configuration of the signal width detection circuits 9, 11, 13,. In FIG. 5, a signal width detection circuit is configured using an AND gate. Also with this configuration, results logically similar to those of the configuration of FIG. 4 can be obtained.

(RS latch type delay circuit)
Details of the configuration and operation of the RS latch type delay circuits 17, 18, 19... Will be described.

  As shown in FIG. 2, the first RS latch type delay circuit 17 includes an RS latch 17 a and a delay element 20. The second, third,..., Nth RS latch type delay circuits have the same configuration. FIG. 6 shows three specific configuration examples of the RS latch circuit 17a included in the RS latch type delay circuit. 6A is an example in which an OR gate and an AND gate are combined, FIG. 6B is an example in which two OR gates are combined, and FIG. 6C is an example in which two NAND gates are combined. Show. FIG. 7 shows the operation timing of the RS latch circuit 17a.

  As shown in FIG. 7, when the time width during which the input S is “H” is equal to or less than the time TD, the RS latch circuit 17a converts the time width to a width equal to the time TD and outputs the converted time width (see “ (Refer to the part indicated by “A”). When the time width during which the input S is “H” is larger than the time TD, the RS latch circuit 17a outputs the input S as it is as the output Y (see the portion indicated by “B” in the figure).

  The purpose of the RS latch circuit 17a is to set a signal width equal to or shorter than the delay time TD to a time TD as shown in FIG. 3 (j), like the output signal of the third signal width detection circuit 13 shown in FIG. Is converted to a signal having a time width of. This conversion is for the following reason.

  When a signal having a time width equal to or shorter than the delay time TD is input to the third delay chain circuit 14, a whisker pulse having a width equal to or shorter than the delay time TD is output to the output of the third delay chain circuit 14 and the final output of the delay amplifier 16. May occur, and the subsequent quantization circuit 6 may malfunction. In order to prevent this, the minimum time width of the output of the RS latch type delay circuit is secured by the RS latch circuit 17a.

(Operation of quantizer)
With reference to FIG. 3, the operation of the quantization apparatus 1 shown in FIG. 1 will be described. FIG. 3 is a diagram showing the operation timing of the delay amplifier 16. Here, as an example, the amplification factor in the time axis direction is doubled.

  Assume that a PWM signal having a time width of 3.5 × TD is input as shown in FIG. The quantization apparatus 1 quantizes a section (Tx) having a time width of 3.5 × TD. Here, TD is a delay time of one delay element 20.

  The first signal width detection circuit 9, the second signal width detection circuit 11, the third signal width detection circuit 13,..., How many times the delay time TD the input PWM signal has. Is detected.

  Since the output of the signal width detection circuit of each stage is sequentially input to the signal width detection circuit of the next stage, as shown in FIGS. 3B, 3E and 3I, the signal width detection circuit of each stage The start of the “H” section of the output signal is a timing obtained by sequentially delaying the start of the section Tx of the PWM signal. The end of the “H” section of the output signal of the signal width detection circuit at each stage coincides with the end timing of the section Tx of the PWM signal. That is, the output of the signal width detection circuit at each stage is sequentially delayed, and the signal width of the output signal is gradually reduced.

  In this example, since the pulse width of the PWM signal is 3.5 × TD, the signal width (“H” section) does not appear in the output of the fourth signal width detection circuit (not shown). This is because the signal is transmitted in the order of the first signal width detection circuit 9, the second signal width detection circuit 11, and the third signal width detection circuit 13 only when the PWM signal that is the input signal is “H”. In addition, when passing through each signal width detection circuit, the signal is transmitted after being delayed by time TD. As a result, when the PWM signal as an input signal appears up to the output of the Nth signal width detection circuit (N is an integer value), the signal width is between N × TD and (N + 1) × TD. I can judge. In this example, as shown in FIG. 3 (i), since the signal (“H” period) appears until the output of the third signal width detection circuit 13, the width of the input PWM signal is 3 × TD. To 4 × TD can be detected.

  The signals detected by the first signal width detection circuit 9, the second signal width detection circuit 11, the third signal width detection circuit 13 and the like (see FIGS. 3B, 3E, and 3I) are The first RS latch-type delay circuit 17, the second RS latch-type delay circuit 18, the third RS latch-type delay circuit 19, the first delay chain circuit 10, the second delay chain circuit 12, and the third Amplified in the time axis direction by the delay chain circuit 14 (see FIGS. 3D, 3H, and 3M).

  In the example shown in FIG. 3, the signal detected up to the third signal width detection circuit 13 passes through the third RS latch type delay circuit 19 and appears at the output of the third delay chain circuit 14. Three delay elements (19b, 14a, 14b) are routed. Further, the output of the third delay chain circuit 14 is obtained by ORing the outputs of the delay elements 19b, 14a and 14b. Therefore, the output of the third delay chain circuit 14 becomes a signal equivalent to a delay of 3 × TD added to the detected time width of 3 × TD (see FIG. 3M).

  The delayed amplified output signal that is the final output is the logical sum of the PWM signal that is the input signal and the outputs of the first delay chain circuit 10, the second delay chain circuit 12, and the third delay chain circuit 14 described above. Therefore, the input PWM signal is equivalent to a signal amplified twice in the time axis direction (see FIG. 3 (n)).

  Here, the error of the delay amplifier 16 will be considered. As described above, the signal width detection circuit of the quantizer detects that the width of the input PWM signal having a width of 3.5 × TD is between 3 × TD and 4 × TD. This means that a detection error of ± 0.5 × TD may occur. Further, the output signal of the signal width detection circuit is amplified in the time axis direction by an amplification factor (2 in this example) by the RS latch type delay circuit and the delay chain circuit. That is, the output of the delay amplifier 16 may include an error of (± 0.5 × TD × amplification factor). Thus, in order to obtain high quantization accuracy by the quantization device, the error {± 0.5 × TD × amplification factor} of the delay amplifier 16 is set to the quantization clock period of the quantization circuit 6. It is necessary to make it sufficiently small. For example, when the quantization clock is 100 MHz (period = 10 nsec), the delay time TD and the amplification factor are set so that the error {± 0.5 × TD × amplification factor) of the delay amplifier 16 is less than 2 nsec.

  Increasing the amplification factor in the time axis direction can be dealt with by increasing the number of delay elements included in each stage delay chain circuit.

  The delay amplifier 16 using a delay element has a characteristic that it is vulnerable to fluctuations in the semiconductor process, power supply voltage, temperature, and the like. In order to overcome this problem, in the configuration of the quantization device shown in FIG. 1, the semiconductor structure (bipolar or CMOS) on the process of the delay element 20 and the oscillator 7 that generates the quantization clock is shared. Further, it is preferable that the circuit characteristics (CR delay time, inverter delay time, circuit constant, etc.) of the delay element 20 and the oscillator 7 are the same.

  In addition, although the quantization of the PWM signal has been described, the present invention is not limited to the PWM signal as long as the width of the analog signal in the time axis direction is quantized in the quantization circuit. However, the same applies.

Embodiment 2
FIG. 8 shows another configuration example of the PWM signal quantization apparatus of the present invention. The quantization apparatus 1b of this example further includes a second quantization circuit 21 and a quantization circuit control circuit 22 that controls the two quantization circuits 6 and 21 in addition to the configuration shown in FIG.

  In the quantization apparatus 1 shown in FIG. 1, depending on the magnitude relationship between the duty ratio of the PWM signal and the amplification factor of the delay amplifier 16, before the quantization circuit 6 finishes quantizing the delayed amplification output signal, the next PWM signal is processed. It may be necessary to start quantization. For example, when the amplification factor of the delay amplifier 16 is N and the duty ratio of the PWM signal is larger than (100 / N)%, the next PWM signal is output before the quantization circuit 6 finishes quantizing the delay amplification output signal. Quantization must be started, causing a problem.

  In order to solve this problem, a plurality of quantization circuits subsequent to the delay amplifier 16 are provided so that each quantization circuit performs quantization in order. The control circuit 22 obtains timing information for starting quantization based on the delayed amplification output signal (or PWM signal), and initializes the quantization circuit 6 and the second quantization circuit 21 based on the timing. The first control signal and the second control signal are output. As a result, even if one quantization circuit is processing, the other quantization circuit can execute the quantization of the next PWM signal, so that the above problem can be solved.

Embodiment 3
A configuration when the quantizing devices 1 and 1b of the respective embodiments are applied to a PLL will be described with reference to FIG. The PLL 100 includes a phase comparator 101, a quantization device 103, a digital filter 105, an oscillator 107, and a frequency divider 109. The quantization device 1, 1b of the present invention shown in FIG. 1 or FIG. 8 is applied to the quantization device 101.

  In the dividing period 109, the frequency of the output signal of the oscillator 107 is divided by a predetermined number (N). The phase comparator 101 compares the frequency of the reference signal REF with the frequency of the input signal from the frequency divider 109, and outputs a PWM signal having an on period (or an off period) proportional to the phase difference. The quantization device 103 quantizes the PWM signal and outputs the result. The digital filter 105 integrates and smoothes the quantization result from the quantization device 103. The oscillator 107 outputs a signal CLK having a frequency corresponding to the output of the digital filter 105 (N times the frequency of the reference signal REF).

  Since the above-described PLL applies the quantization devices 1 and 1b of the present invention to the quantization device 101, the resolution (quantization accuracy) when the output signal of the phase comparator is quantized can be improved. Jitter characteristics can be improved.

  The present invention can reduce a quantization error when quantizing the width of the analog signal in the time axis direction, and is useful, for example, for a PWM signal quantization apparatus.

The figure which shows the structure of the quantization apparatus of the PWM signal in the 1st Embodiment of this invention Diagram showing the configuration of the delay amplifier Operation timing diagram of delay amplifier, (a) input PWM signal, (b) output of first signal width detection circuit, (c) output of first RS latch type delay circuit, (d) first delay chain circuit (E) the output of the second signal width detection circuit, (f) the output of the second RS latch type delay circuit, (g) the output of the delay element in the second delay chain circuit, (h) the second (I) the output of the third signal width detection circuit, (j) the output of the third RS latch type delay circuit, and (k) the first stage in the third delay chain circuit. Output of delay element, (l) Output of delay element of second stage in third delay chain circuit, (m) Output of third delay chain circuit, (n) Delay amplification output signal The figure which shows the structural example of a signal width detection circuit The figure which shows another structural example of a signal width detection circuit The figure which shows three structural examples of RS latch circuit Operation timing diagram of RS latch circuit The figure which shows the structure of the quantization apparatus of the PWM signal in the 2nd Embodiment of this invention. The figure which shows the structure at the time of applying the quantization apparatus based on this invention to PLL. (A) Configuration diagram of conventional PWM signal quantization circuit, (b) Operation timing diagram The figure for demonstrating the quantization error of the quantization circuit of the conventional PWM signal

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1b Quantizer 3 Counter 4 OR gate 6 Quantization circuit 9, 11, 13 Signal width detection circuit 10, 12, 14 Delay chain circuit 15 NOR gate (adder)
16 Delay amplifier (amplifier for quantization)
17, 18, 19 RS latch type delay circuit 17a RS latch circuit 20 Delay element 21 Second quantization circuit 22 Quantization circuit control circuit 26 Quantization circuit 27 Ring oscillator 100 PLL
101 Phase comparator 103 Quantizer 105 Digital filter 107 Oscillator 109 Minute period

Claims (8)

An amplifier for inputting a PWM signal and generating a signal obtained by multiplying the inputted PWM signal by a predetermined number in the time axis direction;
A quantization apparatus comprising: a quantization circuit that receives an output signal from the amplifier and quantizes a pulse width of the output signal. And a second quantization circuit that receives the output signal from the amplifier and quantizes the pulse width of the output signal, and a control circuit that controls the two quantization circuits.
2. The quantization apparatus according to claim 1, wherein the control circuit controls the two quantization circuits based on a PWM signal input to the amplifier or an output signal from the amplifier.   An oscillator that generates a clock signal referred to when quantizing in the quantization circuit; and the amplifier includes a delay element, and the delay element and the oscillator are generated in the same semiconductor structure. The quantization apparatus according to claim 1.   An oscillator that generates a clock signal referred to when quantizing in the quantization circuit; and the amplifier includes a delay element, and the delay element and the oscillator are generated to have the same circuit characteristics. The quantization apparatus according to claim 1, characterized in that:   The amplifier includes an RS latch type delay circuit, the RS latch type delay circuit includes a delay element and an RS latch circuit, and an output signal of the RS latch circuit is delayed by a delay time of the delay element, and the RS latch circuit The quantization apparatus according to claim 1, wherein the quantization apparatus transmits the reset input to the reset input. Placed in the previous stage of the quantization circuit that quantizes the width of the analog signal in the time axis direction and converts it into a digital signal, inputs a PWM signal, and generates a signal obtained by multiplying the input PWM signal by a predetermined number in the time axis direction Quantization amplifier characterized by. A circuit system of a plurality of stages, and an adding means for calculating a logical sum of outputs of the circuit systems of each stage,
The circuit system of each stage is
A signal width detection circuit for detecting a width of an on period or an off period of the PWM signal;
A delay chain circuit that generates a signal having a width proportional to the signal width detected by the signal width detection circuit,
7. The adding means generates a signal amplified by a predetermined number of times in the time axis direction of the inputted PWM signal by calculating a logical sum of outputs of circuit systems at respective stages. Quantization amplifier. A step of inputting a PWM signal, generating a signal obtained by multiplying the input PWM signal by a predetermined number in the time axis direction, and quantizing a pulse width of the signal multiplied by the predetermined number and outputting as a digital signal A quantization method characterized by the following.

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