JP2006108587A - Stacked module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked module that can realize miniaturization. <P>SOLUTION: An output matching circuit 20 includes a first capacitor C21 and a second capacitor C22, and is connected to the next thing in the semiconductor circuit. The first capacitor C21 is a chip component, and is mounted on the surface of a multilayered substrate 10. The second capacitor C22 is composed of a pair of capacitor electrodes located on both sides of dielectric layers 101 to 10n. The first capacitor C21 and the second capacitor C22 are mutually connected in parallel. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a laminated module.

  As this type of laminated module, a power amplification module, a voltage controlled oscillator (VCO) and the like are known. In order to meet the demand for miniaturization and high density, power amplification modules and VCOs use multilayer substrates, and semiconductor devices such as amplifier circuits and passive devices such as capacitors are mounted on the multilayer substrates. In many cases, a structure in which a part of the structure is embedded in a multilayer substrate is employed.

  In addition, since the amplifier circuit constituting the output stage generally has a low output impedance, it is necessary to match the load, and an output matching circuit is provided as means for this. The output matching circuit can widen the bandwidth by lowering the Q value of the circuit, and can also reduce the matching deviation even when the component characteristics vary. In order to reduce the Q value of the circuit, it is necessary to use a capacitor having a large capacity.

  Since the output matching circuit is a circuit for matching the circuits, it is preferable that the circuit constants can be easily adjusted. For this reason, a chip-capacitor whose circuit constant (capacitance value) can be easily changed is generally used as the capacitor of the output matching circuit.

  However, as the capacitance of the chip-capacitor increases, the self-resonant frequency decreases, the Q value deteriorates, and the loss increases. For this reason, when a large-capacity chip-capacitor is used to realize an output matching circuit having a low Q value of the circuit, there arises a problem that the loss of the entire output matching circuit increases.

  In order to reduce the loss caused by the large-capacity chip-capacitor, a method for obtaining a large capacity by connecting a plurality of small-capacity chip-capacitors in parallel has been known. However, in the method in which a plurality of chip-capacitors are connected in parallel, the number of components increases and the occupied area on the multilayer substrate increases, so that there is a problem that miniaturization of the product is prevented accordingly.

  On the other hand, Patent Document 1 and Patent Document 2 disclose a multilayer module that is downsized by forming a capacitor of an output matching circuit inside a multilayer substrate. However, in the multilayer modules disclosed in Patent Document 1 and Patent Document 2, since the capacitor is formed inside the multilayer substrate, the capacitance of the capacitor cannot be adjusted. For this reason, there exists a problem that circuit design and manufacture become very difficult.

  Patent Document 3 discloses a multilayer module that can adjust the circuit constant of the output matching circuit by providing capacitor electrodes constituting the output matching circuit on the surface of the multilayer substrate and trimming the capacitor electrodes.

However, the multilayer module disclosed in Patent Document 3 has a problem in that it is necessary to finely process the capacitor electrode by using a device such as a laser for trimming, which requires a lot of labor for adjusting the circuit constants. It was.
JP-A-11-298264 JP 2002-57511 A JP 2002-359321 A

  An object of the present invention is to provide a small stacked module.

  Another object of the present invention is to provide a laminated module capable of easily adjusting the circuit constant of the output matching circuit.

  Still another object of the present invention is to provide a laminated module that can reduce the loss of the output matching circuit.

  Still another object of the present invention is to provide a laminated module capable of reducing the Q value of an output matching circuit.

  In order to solve the above-described problem, the multilayer module according to the present invention includes a multilayer substrate and an output matching circuit. The multilayer substrate includes a dielectric layer. The output matching circuit includes a first capacitor and a second capacitor, and is connected to a subsequent stage of the semiconductor circuit. The first capacitor is a chip component and is mounted on the surface of the multilayer substrate. The second capacitor is composed of a pair of capacitor electrodes arranged on both sides of the dielectric layer. The first capacitor and the second capacitor are connected in parallel to each other.

  As described above, in the laminated module according to the present invention, since the output matching circuit is connected to the subsequent stage of the semiconductor circuit, impedance matching is obtained between the load connected to the output matching circuit and the semiconductor circuit. be able to.

  The output matching circuit includes a first capacitor. The first capacitor is a chip component and is mounted on the surface of the multilayer substrate. For this reason, the capacitance value can be easily adjusted by removing the first capacitor and replacing it with another chip-capacitor having a different capacitance value.

  The second capacitor is composed of a pair of capacitor electrodes arranged on both sides of the dielectric layer. For this reason, the L capacitor (inductance component) can be reduced, the self-resonance frequency can be increased, and a high Q value can be obtained even when the capacity is increased.

  In the output matching circuit, the first capacitor and the second capacitor are connected in parallel to each other. With this configuration, since the ratio between the capacity of the first capacitor and the capacity of the second capacitor can be arbitrarily set, the degree of freedom in design increases.

  For example, the capacity ratio of the second capacitor can be increased, and the capacity of the first capacitor can be reduced accordingly. This increases the self-resonant frequency of the first capacitor and increases the Q value, thereby reducing the loss of the entire output matching circuit. At the same time, since the combined capacitance value of the first and second capacitors does not change, the Q value of the output matching circuit is kept low.

  If the first capacitor (chip-capacitor) is reduced in capacity by appropriately setting the ratio between the capacity of the first capacitor and the capacity of the second capacitor, the size of the first capacitor is reduced accordingly. This reduces the mounting space for chip components on the multilayer substrate. Thereby, size reduction (density increase) of the whole laminated module is achieved.

  By adjusting the ratio between the capacitance of the first capacitor and the capacitance of the second capacitor, the capacitance of the first capacitor is set to a value within a predetermined range, for example, a capacitance value between 1 pF and 2 pF. The first capacitor can be replaced, that is, the capacitance value can be finely adjusted with a small step size. This is because the assortment of commercially available capacitors is abundant, for example, in the range of 1 pF to 2 pF, and in this range, there is an assortment of fine increments, for example, every 0.1 pF.

As described above, according to the present invention, the following effects can be obtained.
(A) A small stacked module can be provided.
(B) It is possible to provide a laminated module capable of easily fine-tuning the circuit constant of the output matching circuit.
(C) A laminated module capable of reducing the loss of the output matching circuit can be provided.
(D) It is possible to provide a stacked module that can lower the Q value of the output matching circuit.

  Other features of the present invention and the operational effects thereof will be described in more detail by way of examples with reference to the accompanying drawings.

  FIG. 1 is an electric circuit diagram showing an embodiment of a laminated module according to the present invention. In the figure, the laminated module is a part including an output matching circuit of a power amplifier module, for example. The laminated module according to the present invention may include an output matching circuit such as a module other than the power amplifier module, for example, a VCO module.

  In FIG. 1, the stacked module includes a semiconductor circuit 60 and an output matching circuit 20. The semiconductor circuit 60 includes an input matching circuit 611, an interstage matching circuit 612, power amplification elements 621 and 622, and DC bias circuits 631 and 632. The power amplifying elements 621 and 622 are made of semiconductor elements such as bipolar transistors and FETs, for example.

  The output matching circuit 20 has a function of matching the output impedance of the circuit connected to the input terminal T41 with the input impedance of the circuit connected to the output terminal T42. In the figure, the output matching circuit 20 includes an input terminal T41, inductors L21 and L22, a first capacitor C21, a second capacitor C22, a capacitor C23, a DC cut capacitor C51, and an output terminal T42. .

  One end of the inductor L21 is connected to the input terminal T41, and the other end is connected to one end of the first and second capacitors C21 and C22 and to one end of the inductor L22. The other ends of the first and second capacitors C21 and C22 are grounded to GND.

  The other end of the inductor L22 is connected to one end of a capacitor C23 and a DC cut capacitor C51. The other end of the capacitor C23 is grounded to GND. The other end of the DC cut capacitor C51 is connected to the output terminal T42. For example, an isolator, a duplexer, a coupler, or the like is connected to the output terminal T42.

  In the output matching circuit 20, the inductors L21 and L22, the first and second capacitors C21 and C22, and the capacitor C23 constitute a kind of filter (LC circuit).

  When the pass frequency of the output matching circuit 20 is fo, the self-resonant frequency of the combined capacitance obtained by synthesizing the first capacitor C21 and the second capacitor C22 is preferably at least twice the pass frequency fo. More preferably, each of the first capacitor C21 and the second capacitor C22 has a self-resonance frequency that is twice or more the pass frequency fo.

  In the illustrated embodiment, the LC circuit includes a two-stage LC circuit, that is, an inductor L21, a first-stage LC circuit including first and second capacitors C21 and C22, an inductor L22, and a capacitor C23. However, the number of stages of the LC circuit is arbitrary. The first and second capacitors C21 and C22 are preferably provided in a first-stage (frontmost) LC circuit, that is, an LC circuit closest to the semiconductor circuit 60.

  In the laminated module described above, the DC bias circuits 631 and 632 apply a DC bias to the power amplification elements 621 and 622. The power amplifying element 621 amplifies the signal supplied via the input matching circuit 611. The signal amplified by the power amplifying element 621 is supplied to the power amplifying element 622 via the interstage matching circuit 612. The power amplifying element 622 further amplifies the supplied signal and supplies it to the input terminal T41. The output matching circuit 20 outputs the signal supplied to the input terminal T41 from the output terminal T42.

  2 is a partial cross-sectional view showing an embodiment of the layer configuration of the laminated module shown in FIG. 1, and FIG. 3 is a partially enlarged view of the laminated module shown in FIG. The illustrated laminated module includes an MMIC 21 and a multilayer substrate 10.

  The MMIC 21 includes at least a part of the semiconductor circuit 60 described above, for example, power amplification elements 621 and 622. The multilayer substrate 10 is configured by stacking dielectric layers 101 to 10n (n is a natural number).

  The MMIC 21 is mounted on the surface of the multilayer substrate 10. The input matching circuit 611, the interstage matching circuit 612, the DC bias circuits 631, 632, and the like may be formed on the surface of the multilayer substrate 10 or inside the multilayer substrate 10. The mounted component is protected by a shield 70.

  Next, circuit elements of the output matching circuit 20 will be described. In FIG. 3, the first capacitor C <b> 21 is mounted on the surface of the multilayer substrate 10. The second capacitor C22 is formed between the dielectric layers 101 to 10n. In the second capacitor C22, one of the pair of capacitor electrodes may be formed on the surface of the multilayer substrate 10. The inductors L21 and L22, the DC cut capacitor C51, and the like may be formed on the surface of the multilayer substrate 10 or may be formed inside the multilayer substrate 10.

  As described above, since the output matching circuit 20 is connected to the subsequent stage of the semiconductor circuit 60 in the multilayer module according to the present invention, the impedance of the semiconductor circuit 60 can be matched.

  The output matching circuit 20 includes a first capacitor C21. The first capacitor C <b> 21 is a chip component and is mounted on the surface of the multilayer substrate 10. For this reason, the capacitance value can be easily adjusted by removing the first capacitor C21 and replacing it with another chip-capacitor having a different capacitance value.

  The second capacitor C22 is constituted by a pair of capacitor electrodes arranged on both surfaces of one of the dielectric layers 101 to 10n or a plurality of layers adjacent to each other. For this reason, the L capacitor (inductance component) of the second capacitor C22 can be reduced, the self-resonance frequency can be increased, and a high Q value can be obtained even when the capacity is increased.

  In the output matching circuit 20, the first capacitor C21 and the second capacitor C22 are connected in parallel to each other. With this configuration, since the ratio between the capacitance of the first capacitor C21 and the capacitance of the second capacitor C22 can be arbitrarily set, the degree of freedom in design is increased.

  For example, the capacity ratio of the second capacitor C22 can be increased, and the capacity of the first capacitor C21 can be reduced accordingly. As a result, the self-resonant frequency of the first capacitor C21 increases and the Q value increases, so that the loss of the entire output matching circuit 20 is reduced. At the same time, since the combined capacitance value of the first and second capacitors does not change, the Q value of the output matching circuit is kept low.

  For L of the second capacitor C22, for example, the self-resonant frequency of the combined capacitance obtained by synthesizing the first capacitor C21 and the second capacitor C22 is more than twice the pass frequency fo of the output matching circuit 20. It is preferable to design as follows. For example, the capacitance of the first capacitor C21 is preferably set to a value smaller than the capacitance of the second capacitor C22. This is because the above-described excellent operational effects are remarkably exhibited.

  If the capacity of the first capacitor C21 and the capacity of the second capacitor C22 are appropriately set to reduce the capacity of the first capacitor (chip-capacitor), the first capacitor C21 is correspondingly reduced. Can be reduced in size, and the mounting space for chip components can be reduced. Thereby, size reduction (density increase) of the whole laminated module is achieved.

  Further, if the capacity of the first capacitor (chip-capacitor) is reduced, it is not necessary to connect the chip-capacitor in parallel to obtain a large capacity, so that the mounting space for chip components can be reduced and the number of components can be reduced. Cost reduction can be realized.

  Further, by adjusting the ratio of the capacitance of the first capacitor C21 and the capacitance of the second capacitor C22, the capacitance of the first capacitor C21 is set to a value within a predetermined range, for example, a capacitance value between 1 pF and 2 pF. Then, the first capacitor C21 can be replaced, that is, the capacitance value can be finely adjusted with a small increment of the capacitance value. This is because the assortment of commercially available capacitors is abundant, for example, in the range of 1 pF to 2 pF, and in this range, there is an assortment of fine increments, for example, every 0.1 pF. Moreover, if it is this range, it is because a commercially available capacitor with a small tolerance can be obtained.

  Next, the electrical characteristics of the laminated module according to the present invention will be described. 4 is a circuit diagram of the laminated module shown in FIGS. 1 to 3, FIG. 5 is a diagram showing insertion loss of the output matching circuit shown in FIG. 4, and FIG. 6 is a comparative example compared with the laminated module according to the present invention. FIG. 7 is a diagram showing insertion loss of the output matching circuit shown in FIG.

  In FIG. 4, for example, the capacitance of the first capacitor C21 is 3.6 pF, the capacitance of the second capacitor C22 is 6.3 pF, the output impedance of the semiconductor circuit 60 connected to the input terminal T41 is 3Ω, and the output terminal T42 The input impedance of the connected circuit was 50Ω. The pass frequency fo of the output matching circuit 20 is 1.75 GHz.

  The multilayer module of the comparative example shown in FIG. 6 includes a capacitor C81 instead of the first capacitor and the second capacitor. Capacitor C81 is a chip component and is disposed on the surface of the multilayer substrate. The capacitance of the capacitor C81 is set to 6.7 pF, for example. The pass frequency fo of the output matching circuit 80 is 1.75 GHz.

  In FIG. 5, the self-resonant frequency of the combined capacitance of the first and second capacitors is 3.5 GHz, which is approximately twice the pass frequency fo. The loss at the pass frequency (fo = 1.75 GHz) is −0.31 dB, and the loss at a frequency twice the pass frequency (2fo = 3.5 GHz) is −44 dB.

  The insertion loss of the output matching circuit in FIG. 4 is small at the pass frequency fo and large at a frequency twice the pass frequency (2fo = 3.5 GHz). For this reason, the laminated module according to the present invention has a small loss at the pass frequency fo, and a good frequency characteristic in which a harmonic twice as high as the pass frequency is greatly attenuated can be obtained.

  In FIG. 7, the self-resonant frequency of the capacitor C81 is 2.7 GHz, which is much smaller than twice the pass frequency fo. The loss at the pass frequency (fo = 1.75 GHz) is −0.47 dB, and the loss at a frequency twice the pass frequency (2fo = 3.5 GHz) is −27 dB.

  In the comparative example, the loss at the pass frequency fo is −0.47 dB, which is a very large loss. In addition, since the self-resonant frequency (2.7 GHz) is considerably smaller than twice the pass frequency fo, there is little attenuation of harmonics twice the pass frequency (2fo = 3.5 GHz), and good characteristics can be obtained. Absent.

  In the multilayer module, when the LC circuit of the output matching circuit is composed of a plurality of stages of LC circuits, it is preferable to provide the first capacitor and the second capacitor in the LC circuit of the foremost stage. In order to sufficiently reduce the Q of the circuit, generally, the LC circuit at the front stage requires a large capacity capacitor (for example, 5 pF to 20 pF). Therefore, if the present invention is applied to the LC circuit at the front stage, This is because a remarkable effect can be obtained.

  In the laminated module, “input impedance of the circuit connected to the output terminal T42” is preferably 10 times or more of “output impedance of the circuit connected to the input terminal T41”. This is because, as the impedances of the two are further away from each other, the above-described excellent operational effects are remarkably exhibited.

  4 and 5, the capacitance of the first capacitor C21 is 3.6 pF, but the capacitance value of the first capacitor C21 is arbitrary. For example, if the capacitance of the first capacitor C21 is set to 1 pF to 2 pF, which is smaller than 3.6 pF, the loss at the pass frequency fo is further reduced, and an optimum capacitance value is selected from among capacitors with a wide selection. it can.

  FIG. 8 is a front view showing another embodiment of the laminated module according to the present invention. In the figure, the same components as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and redundant description is omitted.

  In the illustrated stacked module, the output matching circuit 20 includes a first-stage LC circuit and a second-stage LC circuit. The first-stage LC circuit includes an inductor L21, a first capacitor C211, and second capacitors C221 and C222. The second-stage LC circuit includes an inductor L22, a first capacitor C212, and a second capacitor C223. The first capacitors C211 and C212 are mounted on the surface of the multilayer substrate 10. The second capacitors C221 to C223 are formed inside the multilayer substrate 10.

  In the illustrated multilayer module, the first capacitor and the second capacitor are provided in each of the LC circuits in a plurality of stages. However, the multilayer module has the same components as the multilayer module shown in FIGS. The effect of this can be achieved. Since the second capacitor is formed inside the multilayer substrate 10, even if the number thereof is increased, it does not hinder downsizing and cost reduction.

  Further, since the illustrated laminated module has a plurality of first and second capacitors, the degree of freedom in circuit design is increased accordingly.

  Although the contents of the present invention have been specifically described above with reference to the preferred embodiments, it is obvious that those skilled in the art can take various modifications based on the basic technical idea and teachings of the present invention. It is.

It is an electric circuit diagram which shows one Example of the laminated module which concerns on this invention. It is a fragmentary sectional view which shows one Example of the laminated constitution of the lamination | stacking module shown in FIG. It is the elements on larger scale of the lamination | stacking module shown in FIG. FIG. 4 is a circuit diagram of the laminated module shown in FIGS. 1 to 3. FIG. 5 is a diagram showing insertion loss of the output matching circuit of FIG. 4. It is a circuit diagram of the comparative example compared with the laminated module which concerns on this invention. It is a figure which shows the insertion loss of the output matching circuit of FIG. It is an electric circuit diagram which shows another Example of the lamination | stacking module which concerns on this invention.

Explanation of symbols

20 output matching circuit C21 first capacitor C22 second capacitor 10 multilayer substrate 101-10n dielectric layer

Claims (7)

A multilayer module including a multilayer substrate and an output matching circuit,
The multilayer substrate includes a dielectric layer;
The output matching circuit includes a first capacitor and a second capacitor, and is connected to a subsequent stage of the semiconductor circuit,
The first capacitor is a chip component and is mounted on the surface of the multilayer substrate,
The second capacitor is composed of a pair of capacitor electrodes disposed on both sides of the dielectric layer,
The first capacitor and the second capacitor are connected in parallel to each other,
Laminated module. A laminated module according to claim 1, wherein
The output matching circuit includes an inductor,
The inductor is a multilayer module that forms an LC circuit together with the first capacitor and the second capacitor. A laminated module according to claim 2, wherein
The first capacitor and the second capacitor are stacked modules in which one end is connected to the inductor and the other end is grounded. A laminated module according to any one of claims 1 to 3,
The multilayer module, wherein the self-resonant frequency of the first capacitor and the self-resonant frequency of the second capacitor are at least twice the passing frequency of the output matching circuit. A laminated module according to any one of claims 1 to 3,
A multilayer module in which a self-resonant frequency of a combined capacitance obtained by combining the first capacitor and the second capacitor is at least twice the passing frequency of the output matching circuit. A laminated module according to any one of claims 1 to 5,
The multilayer module, wherein a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor. A laminated module according to any one of claims 1 to 6,
Laminated module including power amplifier.

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