JP2006108550A - Variable-capacitance diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable-capacitance diode wherein the relative varying width of its depleted layer to its voltage variation is reduced, and the linearity of its voltage-resonance frequency characteristic is improved largely within the scope of its using voltage. <P>SOLUTION: The variable-capacitance diode is formed in a semiconductor substrate 1, and has an n-type impurity diffusing region 6 which constitutes a pn-junction together with a p-type impurity diffusing region 5. A capacitance C obtained when applying a reverse bias voltage (v) across electrodes 3, 4 of the variable-capacitance diode is represented by a function C(v) of the reverse bias voltage (v), and a resonance frequency (f) obtained at this time is represented by a function f(v) of the reverse bias voltage (v). Then, the variable-capacitance diode is such a diode that, when representing the function f(v) by the equation of f(v)=K'/√C, (K' is a constant), the difference of f'(v)=K/(1/√(C(v+0.05))-1/√(C(v-0.05))), (K is a constant), which is the difference of the function f(v) taken between v+0.05 and v-0.05 is forced to satisfy the equation of 0.95<f(v)/f(1)<1.05 within the scope of 1<v<3.5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to, for example, a supercapacitor variable capacitance diode (VCD), and more particularly to the structure of a variable capacitance diode used in a voltage controlled oscillator (VCO) or the like.

Conventionally, for example, a variable capacitance diode used as a capacitor in a voltage controlled oscillator has a pair of electrodes and a P-type impurity diffusion region and an N-type impurity diffusion region formed therebetween, and a reverse bias voltage is applied between the electrodes. By doing so, a depletion layer is formed at the PN junction, and a capacitor using this as a dielectric layer is constructed. However, such a variable capacitance diode has a large fluctuation of the oscillation frequency with respect to the input voltage in the working voltage region, particularly near the lower limit of the region, making voltage control of the oscillation frequency difficult.
As described above, the variable capacitance diode is used by forming a capacitor having a desired capacitance by depleting the PN junction by inputting a reverse bias voltage. Since the frequency characteristic with respect to the input voltage varies depending on the impurity concentration, the impurity concentration distribution determines the performance of the variable capacitance diode.
Non-Patent Document 1 shows an ideal VCD impurity concentration distribution in which the oscillation frequency is proportional to the input voltage (see FIG. 3A). A conventional variable capacitance diode is described in Patent Document 1.

However, in an actual variable capacitance diode, an N-type impurity diffusion region (N layer) is formed in a surface region of a semiconductor substrate such as silicon by a method such as ion implantation and thermal diffusion, and then a high-concentration and shallow P-type impurity diffusion is performed. A region (P layer) is formed. Therefore, the effective impurity concentration of the N-type impurity diffusion region is the difference between the N-type impurity concentration and the P-type impurity concentration, and the effective impurity concentration of the P-type impurity diffusion region is the difference between the P-type impurity concentration and the N-type impurity concentration. It is a difference. For this reason, the net impurity concentration distribution acting as a donor or acceptor is lower than the ideal impurity concentration distribution in the vicinity of the PN junction, and the fluctuation of the oscillation frequency with respect to the input voltage is ideal especially in the region where the input voltage of the variable capacitance diode is low. There was a large deviation from the proportional relationship (see Fig. 4). In order to approach such an ideal proportional relationship, the conventional voltage-controlled oscillator uses two variable capacitance diodes so as to compensate for the mutual displacement (see FIG. 1B). If the fluctuation of the oscillation frequency with respect to the input voltage of the variable capacitance diode is in an ideal proportional relationship, a single variable capacitance diode is sufficient for the voltage controlled oscillator as shown in FIG. can do. However, in reality, the conventional one is not in an ideal proportional relationship due to such circumstances, and it has not been put into practical use to approach this relationship.
Semiconductor Devices-Basic Theory and Process Technology-(SMJ, pages 84-85) Japanese Patent Laid-Open No. 5-167088

  The present invention provides a variable capacitance diode that greatly improves the linearity (proportionality) of voltage-resonance frequency in the operating voltage range.

One aspect of the variable capacitance diode of the present invention is a semiconductor substrate, a P-type impurity diffusion region formed in the semiconductor substrate, and an N-type formed in the semiconductor substrate and forming a PN junction with the P-type impurity diffusion region. An impurity diffusion region, a first electrode formed on the semiconductor substrate and electrically connected to the P-type impurity diffusion region, and formed on the semiconductor substrate and electrically connected to the N-type impurity diffusion region A capacitance C when a reverse bias voltage v is applied between the first electrode and the second electrode, and expressed as a function C (v) of the reverse bias voltage v. Is expressed by a function f (v) of the reverse bias voltage v, and the function f (v) is expressed by a proportional expression f (v) = K ′ / √C (K ′ is a constant). Between v + 0.05 and v−0.05 of the function f (v) The difference f ′ (v) = K / (1 / √ (C (v + 0.05)) − 1 / √ (C (v−0.05))) (K is a constant) is 1 <v <3.5 The following relational expression (1) is satisfied in the range.
0.95 <f (v) / f (1) <1.05 (1)

  The present invention provides a variable capacitance diode that greatly improves the linearity (proportionality) of voltage-resonance frequency in the operating voltage range.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, Embodiment 1 will be described with reference to FIGS.
1 is a voltage-controlled oscillator using a supercapacitor variable capacitance diode of this embodiment, FIG. 2 is a cross-sectional view and a plan view of a variable capacitance diode formed on a semiconductor substrate for explaining this embodiment, FIG. FIG. 3A is an impurity concentration distribution diagram of an ideal variable capacitance diode in which the oscillation frequency is proportional to the input voltage, and FIG. 3B is an ideal variable having the impurity concentration distribution shown in FIG. FIG. 4 is a characteristic diagram illustrating the input voltage-resonance frequency variation characteristics of the capacitance diode. FIG. 4 is a characteristic diagram illustrating the effective impurity concentration distribution of the conventional variable capacitance diode and the region depleted in the operating voltage range. ) Is a distribution diagram showing an effective impurity concentration distribution of the variable capacitance diode in this embodiment and a region depleted in the operating voltage range, and FIG. 5B is a variable having the effective impurity concentration distribution shown in FIG. FIG. 6 is a characteristic diagram showing the input voltage-resonance frequency variation characteristic of the quantum diode. FIG. 6 is a graph showing the effective impurity in the N-type impurity diffusion region of the variable capacitance diode described in this embodiment in comparison with the depletion layer width of the conventional variable capacitance diode. It is a characteristic figure which shows the depletion layer width depending on a density | concentration.

FIG. 2 is a cross-sectional view of a variable capacitance diode formed on a semiconductor substrate and a partially transparent plan view inside the semiconductor substrate for explaining this embodiment. A semiconductor substrate 1 such as silicon is a high concentration N + substrate, and an N− region (well region) 2 is formed in a surface region. In the N− region 2, a P-type impurity diffusion region 5 is formed in contact with the substrate surface, and an N-type impurity diffusion region 6 is formed in contact with the P-type impurity diffusion region 5 away from the substrate surface. A PN junction is formed at the boundary between the two regions. A first electrode 3 having external terminals is provided on the front surface of the semiconductor substrate 1, and a second electrode 4 having external terminals is provided on the back surface. The first electrode 3 is electrically connected to the P-type impurity diffusion region 5, and the second electrode 4 is electrically connected to the N-type impurity diffusion region 6.
In order to form the P-type impurity diffusion region 5 and the N-type impurity diffusion region 6, the N-type impurity diffusion region 6 is first formed deep in the surface region of the semiconductor substrate 1 by using a normal semiconductor technique of ion implantation and thermal diffusion. Form. Thereafter, a high-concentration and shallow P-type impurity diffusion region 5 is formed using a normal semiconductor technique of ion implantation and thermal diffusion. Therefore, the effective impurity concentration of the P-type impurity diffusion region 5 at this time is the remainder obtained by subtracting the N-type impurity concentration from the P-type impurity concentration, and the effective impurity concentration of the N-type impurity diffusion region 6 is determined from the N-type impurity concentration. The remaining P-type impurity concentration is subtracted.

Therefore, as described above, the net impurity concentration distribution acting as a donor or acceptor is lower than the ideal impurity concentration distribution in the vicinity of the PN junction, and in particular, in the region where the input voltage of the variable capacitance diode is low, oscillation with respect to the input voltage. The conventional variable capacitance diode has a frequency deviation greatly deviated from the ideal proportional relationship (see FIG. 4). In this embodiment, the N-type in the region where the input voltage of the variable capacitance diode is low. The effective impurity concentration of the impurity diffusion region 6 can be made closer to the ideal impurity concentration distribution than the conventional variable capacitance diode.
FIG. 5A shows the effective impurity concentration distribution of the variable capacitance diode described in this embodiment and the depleted region in the operating voltage range. The vertical axis represents the effective impurity concentration, and the horizontal axis represents the width of the depletion layer. Further, a depletion layer is generated when an input voltage (VR) that is a reverse bias voltage is applied. In this figure, a depletion region (depletion layer) (A) at the lower limit of the input voltage in the operating voltage range and a depletion region (depletion layer) (B) at the upper limit of the input voltage (VR) are shown. As shown in the figure, the effective impurity concentration of the P-type impurity diffusion region 5 (P layer) and the effective impurity concentration of the N-type impurity diffusion region 6 (N layer) are compared with the conventional one shown in FIG. It is very close to the ideal impurity concentration distribution.

  When the impurity concentration distribution (see FIG. 3A) of an ideal variable capacitance diode in which the resonance frequency is proportional to the input voltage is provided, an ideal input voltage-frequency change characteristic as shown in FIG. The variable capacitance diode is obtained. Also in this embodiment, the variable capacitance diode has an impurity concentration distribution that is close to ideal as shown in FIG. 5A. Therefore, as shown in FIG. The proportionality of the oscillation frequency is improved. In FIG. 5B, the vertical axis represents the resonance frequency (f), and the horizontal axis represents the input voltage (VR) (V). It can be seen that the linearity is almost linear between the upper limit and the lower limit of the input voltage VR, and the proportionality is improved. On the other hand, the conventional variable capacitance diode has an impurity concentration distribution considerably far from ideal as shown in FIG. 4, so that the proportionality between the input voltage and the oscillation frequency is poor in the operating voltage range. The linearity (proportionality) is greatly broken at the lower limit of the input voltage VR.

  Further, the effective impurity concentration of the N-type impurity diffusion region of the conventional variable capacitance diode has its peak concentration point outside the depletion region (A) end of the lower limit of the input voltage, which is near the PN junction. It is shown that the impurity concentration of is greatly reduced (see FIG. 4). However, as shown in FIG. 5A, the effective impurity concentration of the N-type impurity diffusion region of the variable capacitance diode of this example approximates the end of the depletion region (A) at the lower limit of the input voltage and sets the peak concentration point. Have. This indicates that the impurity concentration in the vicinity of the PN junction is an ideal impurity concentration. Further, since the impurity concentration in the vicinity of the PN junction is close to ideal, the depletion layer width (W) in the depletion region (A) at the lower limit of the input voltage is reduced to the depletion layer width in the conventional depletion region (A) at the lower limit of the input voltage. (W0) (see FIG. 4) can be made narrower (W <W0).

It is known that the resonance frequency f of the resonance circuit of the voltage controlled oscillator is proportional to the inverse of the square root of the capacitance C of the capacitor, as shown in the following equation. The capacitance C when the reverse bias voltage v is applied between the electrodes is expressed as a function C (v) of the reverse bias voltage v, and the resonance frequency f at that time is expressed as a function f (v) of the reverse bias voltage v. f is expressed by the following relational expression (4).
f (v) = K ′ / √ (C (v)) (K ′ is a constant) (4)
When the variable capacitance diode of this embodiment is used as a capacitor, the resonance frequency f also changes with a minute change in the input voltage v. Therefore, the resonance frequency is expressed as v + 0 as a function of the input voltage v (volt (V)). Taking the difference (f ′) between .05V and v−0.05V,
f ′ (v) = K / (f (v + 0.05) −f (v−0.05)) = 1 / ((1 / √ (C (v + 0.05)) − (1 / √ (C (v -0.05))) (K is a constant) (5)
It becomes.

In this embodiment, the variable capacitance diode satisfies the following relational expression (1) in the operating voltage range. In other words, the proportionality increases dramatically.
0.95 <f (v) / f (1) <1.05 (1)
f (1) is a resonance frequency when the input voltage is 1V.
When the input voltage v and the resonance frequency f are completely proportional (in the case of the ideal impurity concentration distribution of the variable capacitance diode shown in FIG. 3A), f ′ (v ) Is a constant value. However, the conventional variable capacitance diode as shown in FIG. 4 has a large error in the proportionality between the input voltage and the resonance frequency, which is far from the range shown in the equation (1).

Next, the width of the depletion layer depending on the effective impurity concentration of this embodiment will be described with reference to FIG. In FIG. 6, the vertical axis represents the effective impurity concentration Nd (cm ³ ) of the N-type impurity diffusion region, and the horizontal axis represents the depletion layer width W (μm). The characteristic curve A (-◆-) represents the depletion layer width when the input voltage of this embodiment is 0V (capacity at this time is represented by C0V), and the characteristic curve B (-◇-) is the embodiment. 4 represents the depletion layer width when the input voltage is 1V (capacitance at this time is represented by C1V), and the characteristic curve a (− ▲ −) indicates that when the conventional input voltage shown in FIG. The characteristic curve b (−Δ−) represents the depletion layer width when the conventional input voltage shown in FIG. 4 is 1 V (capacity is represented by C1V). To express.

The depletion layer width W generated by the reverse bias voltage applied between the electrodes (3 and 4 in FIG. 2) is such that the effective impurity concentration Nd of the N-type impurity diffusion region is 5.47E + 16-3. When it is 00E + 17 (cm ³ ), it is about 0.07 to 0.11 μm, and when the input voltage is 1 V, the effective impurity concentration Nd of the N-type impurity diffusion region is 2.94E + 16 to 2.06E + 17 (cm ³ ). Sometimes it is about 0.09-0.20V. On the other hand, the depletion layer width W generated by the reverse bias voltage applied between the electrodes of the conventional variable capacitance diode having the characteristics shown in FIG. 4 is effective for the N-type impurity diffusion region when the input voltage is 0V. When the impurity concentration Nd is 4.00E + 16 to 1.50E + 17 (cm ³ ), it is about 0.09 to 0.16 μm. When the input voltage is 1 V, the effective impurity concentration Nd of the N-type impurity diffusion region is 2. When it is 50E + 16 to 9.50E + 16 (cm ³ ), it is about 0.13 to 0.24 μm. Thus, when this embodiment is compared with the conventional example, the effective impurity concentration of this embodiment is high and the depletion layer width is narrow.

As described above, in the operating voltage range of the variable capacitance diode, for example, in the range of the input voltage 1 <v <3.5, the proportionality error between the input voltage v and the resonance frequency f is within ± 5% at 1V input. Smaller than technology variable capacitance diodes make it easier to design voltage controlled oscillators, and when used in resonant circuits of voltage controlled oscillators, reduce the time required to tune to the desired frequency .
In addition, since the impurity distribution near the PN junction in the concentration distribution obtained by subtracting the P-type impurity concentration from the N-type impurity concentration (hereinafter referred to as effective impurity concentration distribution) is steeper than that of the conventional variable capacitance diode, the input voltage is lower than that of the conventional product. Depletion can be achieved up to the vicinity of an ideal impurity concentration distribution. In the variable capacitance diode of this embodiment, the P-type impurity diffusion region (P layer) is sharply formed as compared with the conventional variable capacitance diode, so that an ideal impurity is obtained at an input voltage of 1.5 V or less. The concentration distribution region can be extended to the low voltage side. As a result, the fluctuation of the oscillation frequency with respect to the change of the input voltage can be suppressed to within ± 5% at the time of 1V input, so that the design of the voltage controlled oscillator becomes easy and the voltage controlled oscillator is tuned to a desired frequency. The time required for this is shortened.

  In addition, since the proportionality between the voltage and the resonance frequency is improved near the lower limit of the operating voltage range, which is a problem with the conventional product, particularly with respect to an input voltage of 1.5 V or less, as shown in FIG. Two voltage-controlled oscillators using variable capacitance diodes were necessary to compensate for the characteristics. However, when the variable capacitance diode of this embodiment is used, one voltage-controlled oscillator has the same effect (see FIG. 1A). Can be configured. Of course, the variable capacitance diode of this embodiment can be used in the circuit of FIG.

Next, Example 2 will be described with reference to FIG.
This embodiment is characterized by a super staircase junction variable capacitance diode in which the maximum concentration region of the effective impurity concentration distribution is depleted at an input voltage of 0.5V. FIG. 7A is a characteristic diagram showing an effective impurity concentration distribution of the variable capacitance diode of this embodiment and a region depleted in the operating voltage range, and FIG. 7B is an effective impurity concentration distribution shown in FIG. 7A. It is a characteristic view which shows the input voltage-frequency change characteristic of. In FIG. 7A, the vertical axis represents the effective impurity concentration, and the horizontal axis represents the width of the depletion layer. Further, a depletion layer is generated when an input voltage (VR) that is a reverse bias voltage is applied. This figure shows a depletion region (depletion layer) (C) having an input voltage lower limit of 0.5 V and a depletion region (depletion layer) (D) having an input voltage (VR) upper limit of 4 V in the operating voltage range. . As shown in the figure, the effective impurity concentration of the P-type impurity diffusion region (P layer) and the effective impurity concentration of the N-type impurity diffusion region (N layer) are compared with the conventional one shown in FIG. It is very close to the ideal impurity concentration distribution.

Also in this embodiment, the variable capacitance diode has an impurity concentration distribution that is close to ideal as shown in FIG. 7A. Therefore, as shown in FIG. The proportionality of the oscillation frequency is improved. In FIG. 7B, the vertical axis represents the resonance frequency (f), and the horizontal axis represents the input voltage (VR) (V). It can be seen that the linearity is almost linear between the upper limit (= 4V) and the lower limit (= 0.5V) of the input voltage VR, and the proportionality is improved. On the other hand, since the conventional variable capacitance diode has an impurity concentration distribution that is far from ideal, the proportionality between the input voltage and the oscillation frequency is poor in the operating voltage range, especially at the lower limit of the input voltage VR. The linearity (proportionality) is greatly broken.
Further, the effective impurity concentration of the N-type impurity diffusion region of the conventional variable capacitance diode has its peak concentration point (P) outside the depletion region (A) end of the lower limit of the input voltage. It shows that the impurity concentration in the vicinity of the PN junction is greatly reduced (see FIG. 4).

However, as shown in FIG. 7A, the effective impurity concentration of the N-type impurity diffusion region of the variable capacitance diode of this embodiment has a peak concentration at the end of the depletion region (C) at the lower limit of the input voltage (0.5 V). Although it has a point P, this indicates that the impurity concentration in the vicinity of the PN junction is close to the ideal impurity concentration. Further, since the impurity concentration in the vicinity of the PN junction is close to ideal, the depletion layer width in the depletion region (C) at the lower limit of the input voltage can be made narrower than the depletion layer width in the depletion region at the lower limit of the input voltage. .
In this way, in the variable capacitance diode of this embodiment, the concentration peak of the effective impurity concentration distribution is depleted at 0.5 V, which is the lower voltage limit of the working voltage region, so that the input voltage ranges from 0.5 V to 3.5 V. The ideal impurity distribution region shown in FIG. 3A can be used, and the proportionality of the resonance frequency to the input voltage is improved.

Next, Embodiment 3 will be described with reference to FIGS.
This embodiment is characterized by a variable capacitor diode having a super staircase junction having the impurity concentration distribution shown in FIG. 8 in the element region. FIG. 8 is a characteristic diagram showing the effective impurity concentration distribution of the variable capacitance diode of this embodiment, and FIG. 9A is a characteristic showing the effective impurity concentration distribution of the variable capacitance diode of this embodiment and the depletion region with respect to the input voltage. FIG. 9B is a characteristic diagram showing the voltage-resonance frequency characteristic of the variable capacitance diode of this example. In FIG. 8, the vertical axis represents the impurity concentration Nd (cm ³ ), and the horizontal axis represents the depth (μm) from the surface of the semiconductor substrate. As shown in the figure, this variable capacitance diode has an N-type impurity diffusion region formed on the surface of the semiconductor substrate, forms a PN junction with this region, and has a P-type impurity diffusion region formed deeper than this region. is doing. In FIG. 9A, the vertical axis represents the effective impurity concentration, and the horizontal axis represents the depth W (μm) from the surface of the semiconductor substrate. The characteristic curve shows a depletion region with respect to the input voltage. Point a of the curve is a depletion region at an input voltage of 0V (a point where a depletion layer extending from the PN junction ends), and point b of the curve is a depletion region at an input voltage of 4V. In FIG. 9B, the vertical axis represents the resonance frequency f (au), and the horizontal axis represents the input voltage VR (V).

  As shown in FIG. 9B, since the impurity distribution is such that the input voltage-resonance frequency is proportional in the range of the input voltage from 0.5 V to 3.5 V, the variable capacitance diode of this embodiment is The input voltage-resonance frequency characteristics are stable in the region.

Next, Example 4 will be described with reference to FIG.
FIG. 10A is a characteristic diagram showing the correlation between the element area (cm ² ) of the variable capacitance diode of this embodiment and the capacitance C1V (pF) when the input voltage is 1 V, and FIG. 10B is this embodiment. FIG. 6 is a characteristic diagram showing the correlation between the element area (cm ² ) of the variable capacitance diode and the capacitance C0V (pF) when the input voltage is 0V. The variable capacitance diode of this embodiment will be described with reference to FIG. The element area corresponds to the N-type impurity diffusion region (area is S) shown in FIG. 10A and 10B, y corresponds to C1V and C0V (capacitance), and x corresponds to S (N-type impurity diffusion region area = element area). 10A and 10B, the vertical axis represents capacitance (C1V, C0V) (pF), and the horizontal axis represents N-type impurity diffusion region area S (cm ² ).

The capacitance C (pF) / (cm ² ) per unit area of the PN junction is expressed by the depletion layer width W (μm) and the following relational expression (6).
C = Ks · ε0 / W (6)
(Ks is the dielectric constant of silicon, ε0 is the dielectric constant of vacuum)
The variable capacitance diode of this embodiment, in which the proportionality between the input voltage v and the resonance frequency f is improved by forming the P-type impurity diffusion region (P layer) sharply compared to the conventional VCD, Since the impurity concentration is high, the depletion layer width becomes thin when the same voltage as in the conventional example is input.
In the variable capacitance diode shown in FIG. 10A, the area (S (cm ² ) of the portion where the N-type impurity is diffused and the capacitance C1V (pF) when the reverse bias voltage is 1 V are expressed by the following relational expression (2). Satisfies.
S × 63998 + 0.3162 <C1V (2)

The region satisfying this relationship is bounded by the straight line of the equation y = 63998x + 0.3162 in FIG. 10A (y is the vertical axis (C1V), and x is the horizontal axis (element area S)). When the variable capacitance diode is formed so that the capacitance (C1V) and the area (S) are applied to the hatched portion and the portion satisfying this relationship, the one satisfying the proportionality between the input voltage and the resonance frequency can be obtained.
Further, in the device in which the proportionality between the input voltage v and the resonance frequency f in a region where the input voltage is lower is improved, the variable capacitance diode shown in FIG. 10B has an area S ( The capacity C0V (pF) in the case of cm ² ) and the reverse bias voltage of 0 V satisfies the following relational expression (3).
S × 114786 + 0.525 <C0V (3)

The region satisfying this relationship is bounded by the straight line of the equation y = 114786x + 0.525 in FIG. 10B (y is the vertical axis (C0V), and x is the horizontal axis (element area S)). When the variable capacitance diode is formed so that the capacitance (C1V) and the area (S) are applied to the hatched portion and the portion satisfying this relationship, the one satisfying the proportionality between the input voltage and the resonance frequency can be obtained.
In addition, as an application of the variable capacitance diode, there is an application (tuner application) that requires a large change in the resonance frequency with respect to a change in the input voltage. A diode having a ratio of C1V (depletion layer width a of VR = 1) to C25V (depletion layer width b of VR = 25) of about 7 has been used (FIG. 11A). However, by applying the diffusion profile of this embodiment having a thin depletion layer width at C0V and C1V, a capacitance ratio (for example, C7V (depletion layer width a of VR = 1) C1V (VR = 1 depletion layer width a)) is lower than that of the prior art. VR = 7 depletion layer width b) ratio of about 7) can be realized (FIG. 11 (b)), and can be used for lowering the voltage of variable capacitance diodes that require large capacitance changes.

1 is a voltage controlled oscillator using a super step junction variable capacitance diode according to a first embodiment which is an embodiment of the present invention. 2A and 2B are a cross-sectional view and a plan view of a variable capacitance diode formed on a semiconductor substrate for explaining Example 1; 3A is an impurity concentration distribution diagram of an ideal variable capacitance diode in which the oscillation frequency is proportional to the input voltage, and FIG. 3B is an ideal having the impurity concentration distribution shown in FIG. The characteristic view explaining the input voltage-resonance frequency change characteristic of a variable diode. The characteristic view explaining the area | region which is depleted in the effective impurity density distribution of a variable capacitance diode of a prior art, and a working voltage range. FIG. 5A is an effective impurity concentration distribution of the variable capacitance diode in Example 1 and a distribution diagram showing a region depleted in the operating voltage range, and FIG. 5B is an effective impurity concentration shown in FIG. The characteristic view which shows the input voltage-resonance frequency change characteristic of the variable capacity diode which has distribution. It is a characteristic view which shows the depletion layer width depending on the effective impurity density | concentration of the N type impurity diffusion area | region of the variable capacitance diode explaining Example 1 compared with the depletion layer width of the conventional variable capacitance diode. FIG. 7A is a characteristic diagram showing an effective impurity concentration distribution of the variable capacitance diode according to the second embodiment which is an embodiment of the present invention and a region depleted in the operating voltage range, and FIG. The characteristic view which shows the input voltage-frequency change characteristic of the effective impurity concentration distribution shown to (a). The characteristic view which shows the effective impurity density distribution of the variable capacity diode of Example 3 which is one Example of this invention. FIG. 9A is a characteristic diagram showing an effective impurity concentration distribution of the variable capacitance diode of Example 3 and a depletion region with respect to an input voltage. FIG. 10A is a characteristic diagram showing the correlation between the element area (cm ² ) of the variable capacitance diode of Example 4 which is an embodiment of the present invention and the capacitance C1V (pF) when the input voltage is 1V. (B) is a characteristic diagram showing the correlation between the element area (cm ² ) of the variable capacitance diode of this example and the capacitance C0V (pF) when the input voltage is 0V. FIG. 11A is a distribution diagram showing an effective impurity concentration distribution of a conventional variable capacitance diode and a region depleted in the operating voltage range, and FIG. 11B is an effective impurity concentration distribution of the variable capacitance diode in the fourth embodiment. And a distribution diagram showing a region that is depleted in the operating voltage range.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... N- area | region 3, 4 ... Electrode 5 ... P-type impurity diffusion area | region (P layer)
6 ... N-type impurity diffusion region (N layer)

Claims (5)

A semiconductor substrate;
A P-type impurity diffusion region formed in the semiconductor substrate;
An N-type impurity diffusion region formed on the semiconductor substrate and forming a PN junction with the P-type impurity diffusion region;
A first electrode formed on the semiconductor substrate and electrically connected to the P-type impurity diffusion region;
A second electrode formed on the semiconductor substrate and electrically connected to the N-type impurity diffusion region;
The capacitance C (pF) when a reverse bias voltage v volt (V) is applied between the first electrode and the second electrode is expressed as a function C (v) of the reverse bias voltage v, and the resonance frequency f at that time Is expressed by a function f (v) of the reverse bias voltage v, and the function f (v) is expressed by a proportional expression f (v) = K ′ / √C (K ′ is a constant). ) Between v + 0.05 and v−0.05, f ′ (v) = K / (1 / √ (C (v + 0.05)) − 1 / √ (C (v−0.05))) ( A variable capacitance diode characterized in that K is a constant) satisfies the following relational expression (1) in the operating voltage range.
0.95 <f (v) / f (1) <1.05 (1) The depletion layer width generated by the reverse bias voltage applied between the first and second electrodes has an effective impurity concentration in the N-type impurity diffusion region of 5.47E + 16 to 3.00E + 17 (when the input voltage is 0 V). cm ³ ) and 0.07 to 0.11 μm, and when the input voltage is 1 V, the effective impurity concentration at the end of the depletion layer in the N-type impurity diffusion region is 4.00E + 16 to 2.06E + 17 (cm ^3). The variable capacitance diode according to claim 1, wherein the voltage is 0.09 to 0.20V. In the case where the area is Scm ² of the N-type impurity diffusion region forming the PN junction with the P-type impurity diffusion region, the capacitance C1V (pF) when the reverse bias voltage is 1 V satisfies the relational expression (2). The variable capacitance diode according to claim 1.
S × 63998 + 0.3162 <C1V (2) In the case where the area is Scm ² of the N-type impurity diffusion region forming the PN junction with the P-type impurity diffusion region, the capacitance C0V (pF) when the reverse bias voltage is 0 V satisfies the relational expression (3). The variable capacitance diode according to claim 1.
S × 114786 + 0.525 <C0V (3) 2. The variable according to claim 1, wherein a peak point of the impurity concentration in the effective impurity concentration distribution of the N-type impurity diffusion region coincides with a lower limit depletion layer end or is included in the lower limit depletion layer. Capacitance diode.

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