JP2006108340A - Semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip which has a dummy pattern which can identify a position as to a specific portion in, for example, SRAM cells even after completion of a final wiring process for analysis. <P>SOLUTION: The semiconductor chip has an area which comprises only a dummy pattern for restricting a dishing caused when levelling by a chemical machining polishing method, in at least a portion of the conductor wiring layer of an uppermost layer, and the dummy pattern is laid out so as to present the specific position of a semiconductor element located in a lower layer than the conductor wiring layer of the uppermost layer. By observing the dummy pattern, the specific portion of SRAMs can be observed in the semiconductor chip. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  According to the present invention, a dummy pattern for chemical mechanical polishing is formed by providing information for identifying a specific region of a semiconductor element located in a lower layer on an uppermost conductor film of a semiconductor chip made of at least a part of a semiconductor chip. The present invention relates to a semiconductor chip.

  In the manufacturing process of a semiconductor chip, a process of planarizing the upper surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method is performed in order to eliminate the unevenness of the interlayer insulating film and planarize it. When planarization using the CMP method is performed, if the density of structures such as wirings in the lower structure is uniform, the upper surface of the interlayer insulating film can be further planarized.

  Therefore, in order to improve the flatness of the interlayer insulating film, a method has been adopted in which a dummy pattern is formed as a lower structure in a region where no wiring exists, and the density of structures such as wiring in the lower structure is made uniform. Yes.

  Conventionally, as a means for generating a dummy pattern, after inputting a wiring pattern to a dummy pattern generation program, an area necessary for automatically processing the density of the wiring pattern by the program and making the density of the structure uniform A method for generating a dummy pattern was used.

  For example, Patent Document 1 proposes a method of optimizing the layout of dummy patterns by determining the arrangement of dummy patterns based on circuit pattern position data.

  Further, in Patent Document 2, when there is a repeated pattern such as a RAM (Random Access Memory), a mark pattern for specifying the RAM position is formed in a part of the CMP dummy pattern with respect to the RAM pattern row. The method was known.

JP 2002-203905 A (paragraphs 0049 to 0066) JP-A-9-306910 (paragraphs 0014 to 0021)

  However, in the method of inserting a dummy pattern automatically generated by a program shown in Patent Document 1, it is difficult to detect the position of the semiconductor element on the lower layer side of the dummy pattern. However, there is a problem that it is difficult to identify the defective position of the lower layer wiring.

  In addition, in the dummy pattern obtained by the method disclosed in Patent Document 2, it is possible to identify the position of the periodic pattern, but the position of each periodic pattern is identified by changing a part of the shape of the dummy pattern. Therefore, there is a problem that it is difficult to know the position information of the semiconductor element in detail only with this dummy pattern. Furthermore, when observing at a high magnification using an electron microscope or the like, a pattern obtained by changing a part of the shape of the dummy pattern is out of the field of view of the electron microscope, making it difficult to investigate the layout of the semiconductor element. there were. Further, even if Patent Document 1 and Patent Document 2 are combined, as long as a dummy pattern is mechanically generated as described in Patent Document 1, a means for identifying a wiring defect position below the dummy pattern is found. It is difficult.

  Therefore, an object of the present invention is to form a dummy pattern that can identify and analyze the position of a specific portion in, for example, an SRAM cell even after the final wiring process is completed.

  In order to achieve the above object, the semiconductor chip of the present invention has an area consisting only of a dummy pattern for suppressing dishing that occurs when performing planarization by a chemical mechanical polishing method on at least a part of the uppermost conductor wiring layer. The dummy chip is laid out so as to present a specific position of a semiconductor element located below the uppermost conductor wiring layer.

  According to this configuration, by examining the dummy pattern formed in the uppermost conductor wiring layer of the semiconductor chip, a specific region of the semiconductor element located in the lower layer can be identified. Therefore, it is possible to efficiently perform defect analysis and the like. Further, since the distance between the feature point of the dummy pattern and the feature point of the semiconductor element located in the lower layer can be reduced, the feature point of the dummy pattern and the semiconductor element can be obtained even by using observation means having a high magnification such as an electron microscope. Therefore, it is possible to perform defect analysis more efficiently than in the case where only the reference position for search is formed on the semiconductor chip.

  The semiconductor chip of the present invention is characterized in that the semiconductor chip is repeatedly arranged in the same pattern in the semiconductor chip.

  According to this configuration, when the same pattern is repeatedly laid, the dummy pattern is also laid repeatedly in accordance with the underlying semiconductor element, so that the features of the repeatedly formed semiconductor element and the semiconductor element to be referred to can be referred to. The existence position in the semiconductor chip can be identified. Therefore, defect analysis can be performed more efficiently than when observing an object in which a random dummy pattern is formed on the uppermost conductor wiring layer.

  The semiconductor chip of the present invention is a cell constituting an SRAM.

  According to this configuration, the above-described effects can be obtained for the SRAM in which the same pattern is repeatedly laid. In addition, the SRAM has a very crowded structure in order to achieve a high degree of integration. When a semiconductor chip is observed using FIB (Focused Ion Beam), such as defect analysis, it is easy to understand by using a simple dummy pattern for the crowded structure. The location can be easily identified, and observation can be performed easily and accurately.

In the semiconductor chip of the present invention, the dummy pattern is formed in one shape per one cell, and each dummy pattern is formed in the same shape for the same semiconductor element pattern in the corresponding cell. It is characterized by being.
According to this configuration, the dummy pattern is formed in one shape per cell, and the semiconductor element pattern in the cell corresponding to each dummy pattern is formed in the same shape for the same cell. When analyzing each cell, those having the same semiconductor element pattern are laid out with the same dummy pattern. Therefore, the dummy pattern is formed so that the positional relationship between the dummy pattern and the semiconductor element pattern corresponds. Therefore, the semiconductor element pattern in the lower layer can be easily known by examining the dummy pattern.

  In the semiconductor chip of the present invention, the dummy pattern has a shape so that the direction of the cell can be recognized.

  According to this configuration, when performing defect analysis, when investigating a dummy pattern, it is possible to easily know the direction of the cells, and to grasp the positional relationship of the cells more efficiently.

  The present invention will be described below with reference to the drawings. In the present invention, since it is necessary to have a layer consisting only of a dummy pattern at the uppermost part of the wiring layer of the semiconductor chip, the system LSI in which SRAM (Static Random Access Memory) is embedded is used as a system LSI. Description will be made assuming a structure having a conductor wiring layer on the upper side and only a dummy pattern on the upper side of the SRAM pattern. FIG. 1 is an equivalent circuit diagram of an SRAM.

  Here, the configuration of the SRAM will be briefly described with reference to FIG. The SRAM cell 100 is composed of two inverters and two transfer NMOSs (N-type MOS transistors). Here, when the input of the inverter 101 is “high”, the output of the inverter 101 is “low”. The output of the inverter 101 is “low” because it is directly connected to the input of the inverter 102. Therefore, the output of the inverter 102 becomes “high” and is stabilized. This circuit functions as a memory in order to maintain this state until external writing is performed through the transfer NMOS 103 and the transfer NMOS 104 transistor.

  FIG. 2 is an equivalent circuit diagram of the inverter 101. The gate of the NMOS 201 and the gate of the PMOS (P-type MOS transistor) 202 are connected to form an input unit 203. The drain of the NMOS 201 and the drain of the PMOS 202 are connected to form an output unit 204.

  Further, the source of the NMOS 201 is connected to VSS which is the low potential side of the power supply, and the source of the PMOS 202 is connected to VDD which is the high potential side of the power supply.

  When a “high” potential is applied to the PMOS input unit 203, the potential of the gate of the NMOS 201 becomes “high” and the NMOS 201 becomes conductive. On the other hand, since the gate of the PMOS 202 is “high”, the PMOS 202 is turned off. Accordingly, the potential of the output unit 204 becomes “low”, and an output in which the inputted “high” potential is inverted can be obtained.

  Further, when a “low” potential is applied to the input portion 203, the gate potential of the NMOS 201 becomes “low”, and the NMOS 201 becomes non-conductive. On the other hand, since the gate of the PMOS 202 is “low”, the PMOS 202 becomes conductive. Therefore, the potential of the output unit 204 becomes “high”, and an output obtained by inverting the inputted “low” potential is obtained, so that this circuit becomes an inverter.

  FIG. 3 is an equivalent circuit diagram of the SRAM described with all MOS level semiconductor elements. An inverter formed by the NMOS 301 and the PMOS 302 corresponds to the inverter 101 in FIG. An inverter formed of NMOS 303 and PMOS 304 corresponds to the inverter 102 in FIG. In the SRAM used in this embodiment, one SRAM cell 100 is formed by using a total of six transistors in this way.

  FIG. 4 is a layout diagram for realizing the equivalent circuit shown in FIG. 3 on a semiconductor chip. When the hatching for distinguishing each region from the MOS equivalent circuit is overlapped, the drawing becomes difficult to see. In FIG. 4, the hatching indicating each region is omitted. In addition, contact regions 414, 415, 416, and 417, which will be described later, which are likely to cause problems, are hatched and overlapped in FIG.

  The SRAM cell 100 is formed on the semiconductor chip 400 on which the SRAM is mounted. The SRAM is arranged such that the unit cell pattern is repeated vertically and horizontally in the semiconductor chip.

  An NMOS 301 is formed by a polysilicon region 405 in an NMOS channel region 401 formed in a reverse Γ type. Similarly, a PMOS 302 is formed by the PMOS channel region 403 and the polysilicon region 405. Further, the gate of the NMOS 301 and the gate of the PMOS 302 are connected by a polysilicon region 405.

  Similarly, an NMOS channel region 402 and a polysilicon region 406 formed in a Γ shape form an NMOS 303, and a PMOS channel region 404 and a polysilicon region 406 form a PMOS 304.

  Further, the gate of the NMOS 303 and the gate of the PMOS 304 are connected by a polysilicon region 406. The NMOS channel region 401 and the polysilicon region 407 form an NMOS 305. The source portion of the NMOS 305 is connected to the drain portion of the NMOS 301 through the NMOS channel region 401.

  Similarly, the NMOS channel region 402 and the polysilicon region 407 form an NMOS 306. The source portion of the NMOS 306 is connected to the drain portion of the NMOS 303. The gate of the NMOS 305 and the gate of the NMOS 306 are connected by a polysilicon region 407.

  Note that portions that cannot be connected by the polysilicon wiring layer alone are connected using a metal wiring layer formed on the polysilicon wiring layer via the contact region. The drain 410 of the NMOS 301, the drain 408 of the PMOS 302, and the gate 409 of the NMOS 303 are electrically connected through a metal wiring layer formed on the polysilicon wiring layer through the contact region. Similarly, the drain 412 of the NMOS 303, the drain 411 of the PMOS 304, and the gate 413 of the NMOS 301 are electrically connected through the contact region via the metal wiring layer above the polysilicon wiring layer.

  Next, locations where problems are likely to occur in the SRAM will be described with reference to FIG. 4 again.

  (A) Since the dimension of the polysilicon region 405 that intersects the N channel region 401 is a factor that determines the gate length of the NMOS 301, if it is too thick, the operation speed will be slow, and if it is too thin, the current consumption will increase. .

  (B) The dimension of the polysilicon region 405 that intersects the P channel region 403 is a factor that determines the gate length of the PMOS 302. If it is too thick, the operation speed is slow, and if it is too thin, the current consumption increases.

In the following, as the dimensions of the parts that give rise to defects in processing dimensions that cause similar problems,
(C) The dimension of the portion where the N channel region 402 and the polysilicon region 406 intersect.

  (D) A dimension of a portion where the P channel region 404 and the polysilicon region 406 intersect.

  (E) Dimensions of the portion where the N channel region 401 and the polysilicon region 407 intersect.

  (F) Dimension of a portion where the N channel region 402 and the polysilicon region 407 intersect.

  The dimensions related to the gate lengths of the six transistors are an important factor in operating the SRAM.

In addition, when a problem occurs in the contact region, the operation of the SRAM is defective. Although there are many contact regions in the SRAM pattern, a contact region that is likely to cause a problem empirically is (G) a contact region 414 that transmits the power supply potential to the source of the PMOS 302.

  (H) A contact region 415 that applies a ground potential to the source of the NMOS 301.

  (I) A contact region 416 for extracting a signal from the NMOS 305.

  (J) A contact region 417 for extracting a signal from the NMOS 306 can be mentioned.

  Next, the correspondence between the shape of the dummy pattern and the SRAM pattern identified by the dummy pattern will be described. FIG. 5 is a diagram in which the dummy pattern formed on the uppermost metal layer in the SRAM region is overlaid with the SRAM pattern shown in FIG. In FIG. 5, the equivalent circuit diagram of the MOS that has been overwritten is omitted, and each region is hatched. The dummy pattern 501 is formed so as to be overlaid on the unit SRAM cell surrounded by the dotted line, and is a pattern for identifying the position of a semiconductor element that is likely to cause a problem empirically.

  The dummy pattern 501 is formed by forming a top conductive film, applying a photoresist, and exposing using an exposure mask formed on the exposure mask having a cross-shaped dummy pattern as a mask pattern, It is formed using a normal photolithography process. In addition, as a technique for measuring the pattern size of the SRAM, a method is used in which all of the following observations are performed by scraping the vicinity of a corresponding place by the FIB (Focused Ion Beam) method and digging out a lower layer pattern. ing. In FIG. 5, for the sake of explanation, the SRAM cell portion is depicted so as to be visible, but in an actual semiconductor chip, it is hidden by an insulating film or a wiring layer formed on the SRAM cell, You can see only the pattern of the cross shape.

  The shape of the dummy pattern 501 is formed in a cross shape with a lower side corresponding to the cell. Therefore, the vertical direction of the unit SRAM cell can be read from the dummy pattern 501.

  (A) The size of the polysilicon region 405 that intersects the N-channel region 401 is located below the left horizontal bar-like region of the cross-shaped dummy pattern 501, so that the dummy pattern 501 can be easily observed by observing the dummy pattern 501. The location can be identified.

  (B) Since the dimension of the polysilicon region 405 that intersects the P-channel region 403 is located above the horizontal bar-like region of the cross-shaped dummy pattern 501, the position can be easily identified by observing the dummy pattern 501. can do.

  (C) The size of the polysilicon region 406 that intersects the N channel region 402 is located below the right horizontal bar-shaped region of the cross-shaped dummy pattern 501, so that it can be easily observed by observing the dummy pattern 501. The location can be identified.

  (D) Since the dimension of the polysilicon region 406 that intersects with the P channel region 404 is positioned above the right horizontal bar-shaped region of the cross-shaped dummy pattern 501, it can be easily observed by observing the dummy pattern 501. Can be identified.

  (E) The dimension of the polysilicon region 407 that intersects the N channel region 401 is located on the lower left side of the vertical bar-shaped region of the cross-shaped dummy pattern 501, so that the position can be easily observed by observing the dummy pattern 501. Can be identified.

  (F) Since the size of the partial polysilicon region 407 intersecting with the N channel region 402 is located on the lower right side of the vertical bar-like region of the dummy pattern 501 having a cross shape, the position can be easily observed by observing the dummy pattern 501. Can be identified.

  (G) Since the contact region 414 for transmitting the power supply potential to the source of the PMOS 302 is located at the intersection of the left side of the left horizontal bar of the dummy pattern 501 having a cross shape and the upper side of the vertical bar, observe the dummy pattern 501. Can easily identify the position.

  (H) Since the contact region 415 for applying the ground potential to the source of the NMOS 301 is located at the lower part of the left side of the left horizontal bar of the cross-shaped dummy pattern 501, the position can be easily identified by observing the dummy pattern 501. be able to.

  (I) Since the contact region 416 for extracting a signal from the NMOS 305 is located on the lower left side of the vertical bar-shaped region of the cross-shaped dummy pattern 501, the position can be easily identified by observing the dummy pattern 501. .

  (J) Since the contact region 417 for extracting a signal from the NMOS 306 is located on the lower right side of the vertical bar-shaped region of the cross-shaped dummy pattern 501, its position can be easily identified by observing the dummy pattern 501. it can.

  As described above, when analyzing an SRAM having a complicated shape, it is possible to efficiently analyze by forming this dummy pattern.

  Next, the dishing suppression effect will be described with reference to FIG. FIG. 6 is a front view in which a dummy pattern of wiring formed on an SRAM cell via an insulating film or the like is developed on a semiconductor chip.

  When the dummy pattern 602 of the wiring layer formed on the SRAM cell 100 is developed on the semiconductor chip 400, the dummy pattern 602 is formed on the semiconductor chip 400 with a substantially uniform density. Therefore, planarization by the CMP method can be realized without causing dishing caused by pattern density.

  Next, the effect of this embodiment will be described.

  (1) Since the specific position of the semiconductor element located in the lower layer can be presented using the dummy pattern formed in the uppermost conductor wiring layer, it is possible to dig into the specific position using the FIB. It is possible to reduce the load for failure analysis.

  (2) Since the unit cell is repeatedly arranged in the semiconductor chip, the dummy pattern associated with the lower gate region is provided at the uppermost part of the conductor layer, so that the repeated dummy pattern is formed at the uppermost part of the conductor layer. It was. Therefore, the wiring density of the uppermost layer can be kept substantially constant, and the lower layer structure can be easily identified, and at the same time, excellent flatness can be obtained during CMP.

  (3) With respect to an SRAM that uses a complicated wiring pattern to reduce the cell area per unit cell, a simple dummy pattern can be used to indicate a part that greatly affects the characteristics of the SRAM. Therefore, the failure analysis can be performed even if the SRAM does not have much detailed knowledge.

  (4) Since the dummy pattern is formed in one shape per cell, and the semiconductor element pattern in the cell corresponding to each dummy pattern is formed in the same shape for the same cell, which cell Also, when analyzing the same location, failure analysis or the like can be performed by analyzing the corresponding position in each dummy pattern.

  (5) By forming the pattern so that the vertical and horizontal orientations of the dummy pattern can be understood, it becomes possible to easily determine where the pattern desired to be observed exists when the dummy pattern is observed with an electron microscope or the like.

  (Modification 1) Although the dummy pattern shown in the present embodiment has a cross shape, a dummy pattern having other shapes may be used, and a specific pattern of a semiconductor element laid out in a lower layer may be used. Any pattern that can identify the region may be used.

  (Modification 2) In the present embodiment, an example using a semiconductor substrate has been described. However, an SOI (silicon on insulator), a TFT (thin film transistor), or a compound semiconductor may be used.

  (Modification 3) In the present embodiment, the SRAM has been particularly described. However, this may be used for identifying a specific position of a semiconductor element used in various devices such as a DRAM and a gate array.

The equivalent circuit diagram of SRAM. The equivalent circuit diagram of an inverter. The equivalent circuit diagram of SRAM described with the semiconductor element of MOS level. The layout diagram for implement | achieving an equivalent circuit on a semiconductor chip. The figure which described the dummy pattern formed in the uppermost metal layer of SRAM area, and the pattern of SRAM in an overlapping manner. The front view which expanded the dummy pattern of wiring on the semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... SRAM cell 101 ... Inverter 102 ... Inverter 103 ... Transfer NMOS, 104 ... Transfer NMOS, 201 ... NMOS, 202 ... PMOS, 203 ... Input part, 204 ... Output part, 301 ... NMOS, 302 ... PMOS, 303 ... NMOS, 304 ... PMOS, 400 ... Semiconductor chip, 401 ... NMOS channel region, 402 ... NMOS channel region, 403 ... PMOS channel region, 404 ... PMOS channel region, 405 ... Polysilicon region, 406 ... polysilicon region, 407 ... polysilicon region, 408 ... drain, 409 ... gate, 410 ... drain, 411 ... drain, 412 ... drain, 413 ... gate, 414 ... contact region, 415 ... contact region, 416 ... contact region, 417 ... Tact area, 501 ... dummy pattern, 602 ... dummy pattern.

Claims (5)

  A semiconductor chip having a region consisting only of a dummy pattern for suppressing dishing that occurs when performing planarization by a chemical mechanical polishing method in at least a part of the uppermost conductor wiring layer, wherein the dummy pattern is A semiconductor chip laid out to present a specific position of a semiconductor element located below the uppermost conductor wiring layer.   The semiconductor chip according to claim 1, wherein the semiconductor elements are repeatedly arranged in the same pattern in the semiconductor chip.   The semiconductor chip according to claim 1, wherein the semiconductor element is a cell constituting an SRAM.   The dummy pattern is formed in one shape per one cell, and each dummy pattern is formed in the same shape with respect to the same cell in a corresponding semiconductor element pattern in the corresponding cell. Item 4. The semiconductor chip according to any one of Items 1 to 3. 5. The semiconductor chip according to claim 1, wherein the dummy pattern has a shape such that an orientation of the cell can be recognized.

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