JP2006106664A - Organic el light emitting device - Google Patents

Organic el light emitting device Download PDF

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JP2006106664A
JP2006106664A JP2005055459A JP2005055459A JP2006106664A JP 2006106664 A JP2006106664 A JP 2006106664A JP 2005055459 A JP2005055459 A JP 2005055459A JP 2005055459 A JP2005055459 A JP 2005055459A JP 2006106664 A JP2006106664 A JP 2006106664A
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circuit
organic el
current
data line
emitting device
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Haruhiko Nishio
Masahiro Sasaki
雅浩 佐々木
春彦 西尾
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Fuji Electric Holdings Co Ltd
富士電機ホールディングス株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a simple matrix type organic EL light emitting device capable of reducing current consumption when controlling light emission of an organic EL element with a predetermined luminance.
A unit output circuit 2 constituting a data line driving circuit of an organic EL light emitting device includes a pair of PMOS transistors CM0 and CM1, an NMOS transistor NM1 controlled by a reference signal Vref from a reference current generation circuit, An NMOS transistor NM2 for controlling the output current Iout, a capacitor Cs for storing and holding the gate-source voltage Vgs of the PMOS transistor CM0 in the ON state, and a PMOS transistor PM1 connected in parallel to the capacitor Cs are provided. Here, an NMOS transistor sw1 is disposed between the current mirror circuit and the NMOS transistor NM1, and a PMOS transistor sw2 is disposed between the gates of the PMOS transistors CM0 and CM1.
[Selection] Figure 1

Description

  The present invention selects a plurality of organic EL (Electro Luminescence) elements arranged in a matrix in a row direction and a plurality of scanning lines connecting the organic EL elements in a column direction, and a plurality of data lines connecting the organic EL elements in a column direction. The present invention relates to a simple matrix type organic EL light emitting device that controls light emission with luminance, and particularly relates to an organic EL light emitting device that can reduce an average current during operation.

  There are a simple matrix method and an active matrix method for driving a dot matrix organic EL display panel that performs display with dots (dots) arranged in a matrix. The simple matrix method is a method in which the organic EL elements of the respective pixels arranged in a matrix on the display panel are directly driven from the outside in synchronization with the scanning signal, and the display panel of the display device is configured only by the organic EL elements. The

  The organic EL element used in such an organic EL light emitting device has the advantages of high luminous efficiency and low driving voltage. In addition, various colors (green, red, blue, yellow, etc.) can be displayed by selecting the organic material of the light emitting element, and since it is a self-luminous type, the display is clear and no backlight is required. Because it is surface emitting, it has no viewing angle dependency, it is thin and lightweight, and the maximum temperature of the manufacturing process is low, so it has excellent features such as being able to use a soft material such as a plastic film as the substrate material I have.

FIG. 10 is a circuit diagram showing a configuration of a simple matrix type organic EL light emitting device.
The organic EL panel 10 is configured by arranging a plurality of organic EL elements EL11 to EL34 in a matrix. The plurality of data lines 11a to 11d are connected to a data line driving circuit (column driver) 20. The organic EL elements EL11 to EL31, EL12 to EL32, EL13 to EL33, EL14 to EL34 are connected to the data lines 11a to 11d, respectively. A driving current is supplied to the anode. The plurality of scanning lines 12a to 12c are connected to a scanning line driving circuit (low driver) 30. The scanning lines 12a to 12c are respectively cathodes of organic EL elements EL11 to EL14, EL21 to EL24, EL31 to EL34. Is connected.

  The data line driving circuit 20 is connected to a reference current generating circuit 21 and a control circuit 22, and the reference current generating circuit 21 supplies driving currents supplied from the voltage variable type constant voltage DC power source E to the data lines 11 a to 11 d respectively. The size is set. The data line driving circuit 20 includes the same number of constant current sources as the data lines 11a to 11d or more than the data lines 11a to 11d. These constant current sources are constituted by a current mirror circuit, for example.

  The scanning line driving circuit 30 includes a switch circuit that selectively connects each scanning line 12a to 12c to the ground potential, and a series of element groups EL11 to EL14, EL21 to EL24, and EL31 to EL34 arranged in the row direction. Sequentially scanned in the direction. A drive current is selectively supplied from the data line drive circuit 20 via the data lines 11a to 11d to the element group in the row selected by the scanning line drive circuit 30, for example, the organic EL elements EL11 to EL14. Thus, any one of these organic EL elements EL11 to EL14 can be selected and driven to emit light with a predetermined emission luminance.

  In such a conventional simple matrix type organic EL light emitting device, the drive current supplied from the scanning line drive circuit 30 to each of the organic EL elements EL11 to EL34 is temporarily stored as the charge of the capacitor, and the charge is applied to the capacitor. In some cases, a driving method for controlling light emission luminance is employed (see Patent Document 1).

  However, this type of drive system has the following problems. That is, in order to control charging / discharging of the capacitor, it is necessary to dispose a switch element or the like in each pixel, which causes a problem that a control circuit for the organic EL element becomes complicated.

  Patent Document 1 discloses that the period T of the selection period in which each pixel blinks is set to 2.3 times or more the time constant RC of the discharge circuit configured by the internal resistances of the organic EL elements EL11 to EL34. There is a description that multi-gradation display is possible. In that case, the relationship between the luminance L and the charge amount Q is as shown in the equation (4) described in Patent Document 1, but a few percent of the charge remains in the capacitor even when it is discharged. Since this is an error with respect to the luminance L of the organic EL elements EL11 to EL34, the gradation of each pixel cannot be precisely controlled.

  Third, since the pixel voltage is originally applied by the charging voltage of the capacitor, the relationship between the luminance of the organic EL elements EL11 to EL34 and the capacitor voltage is that the capacitor voltage is the threshold voltage of the organic EL elements EL11 to EL34. It becomes a first-order proportional relationship only when it exceeds. Therefore, when the charge of the capacitor is discharged to several percent, the applied pixel voltage also becomes several percent, which is below the threshold value necessary for light emission. It does not emit light correctly with the brightness as described.

  As a driving method of the organic EL light emitting device different from such a voltage modulation method, there is a pulse width modulation (PWM) method described below. This is because the control circuit 22 shown in FIG. 10 generates a pulse width modulation signal PWM, and outputs a drive current whose ON period is controlled from the data line drive circuit 20 using the pulse width modulation signal PWM. This is gradation display data for the organic EL elements EL11 to EL34 of the organic EL panel 10.

FIG. 11 is a circuit diagram showing an example of a unit output circuit constituting the conventional data line driving circuit 20.
The unit output circuit 2a is supplied with a DC power supply voltage Vdd, and includes PMOS transistors CM0 and CM1 constituting a current mirror circuit, an NMOS transistor NM1 controlled by a reference signal Vref from the reference current generation circuit 21, and an output current Iout. The reference current Iref generated by the NMOS transistor NM1 based on the reference signal Vref flows to the current mirror circuit based on the reference signal Vref and is multiplied by the mirror ratio in the current mirror circuit. The output current Iout is output from the transistor sw1.

  The output on period of the output current Iout in the unit output circuit 2a is set according to an image signal input from the outside of the organic EL light emitting device, and is based on, for example, 6 to 8 bit digital data in the control circuit 22. A pulse width modulation signal PWM is generated. The gates of the transistors sw1 and NM2 are controlled by the pulse width modulation signal PWM from the control circuit 22, and the output currents Iout of the data lines 11a to 11d are used as gradation display data for the plurality of organic EL elements EL11 to EL34. Is output. That is, the time width of the output current Iout is controlled from 100% to the minimum unit LSB output in accordance with the gray level for which a constant output is desired to be displayed every horizontal period in synchronization with the driving of the scanning lines 12a to 12c. Thus, gradation display is performed.

At this time, in the unit output circuit 2a, the NMOS transistor NM1 forms a current mirror circuit with the final stage transistor of the reference current generation circuit 21, and the reference current Iref generated by the reference current generation circuit 21 is folded back. The current flows through the NMOS transistor NM1. Accordingly, the gate-source voltage Vgs of the PMOS transistors CM0 and CM1 of the current mirror circuit is determined according to the current value of the reference current Iref flowing through the NMOS transistor NM1, and the output output from the transistor sw1 to the respective data lines 11a to 11d. The magnitude of the current Iout is controlled. Moreover, since the unit output circuit 2a is configured as a circuit that drives only one of the data lines 11a to 11d, the data line drive circuit 20 includes data lines 11a to 11a existing in the organic EL panel 10. The number of unit output circuits 2a corresponding to 11d is required.
JP 2000-276109 A

  However, in the data line driving circuit 20 of FIG. 11 described above, the reference current Iref continues to flow through the NMOS transistor NM1 regardless of whether the output current Iout is on or off. Since a large number of such unit output circuits 2a are included in the data line driving circuit 20, the sum of the currents flowing through the NMOS transistor NM1 becomes a very large value. Therefore, in the case of an organic EL light emitting device used for a small portable electronic device driven by a battery, there is a problem that the battery driving time is shortened (Problem 1).

  Further, the miniaturization of the wiring accompanying the increase in the resolution of the display device increases the wiring resistance of the data line driving circuit 20, so that when the current increases with the increase in the number of elements of the organic EL panel 10, The difference in wiring resistance due to the position of the pixel cannot be ignored. That is, the voltage drop increases because the current concentrates as the wiring resistance of the pixels at both ends, the voltage drop decreases as the wiring resistance in the center decreases, and the distribution of the source potential of the NMOS transistor NM1 with the source terminal grounded is “O”. It becomes an upward convex curve. Thus, since the wiring resistance generated in the ground line differs depending on the pixel position, the voltage distribution is distorted due to the difference in voltage drop. FIG. 6A, which will be described later, shows a voltage distribution between the unit output circuits 2a.

  Now, the gate voltage of the NMOS transistor NM1 that determines the magnitude of the output current Iout is all a common ground line, and the connection destination is only the gate, so that almost no current flows and there is almost no drop in the gate voltage. There is no such distribution. Therefore, since the gate-source voltage Vgs of each NMOS transistor NM1 changes according to the output terminal position, the reference current Iref is not accurately turned back, resulting in an error. In addition, since the current that is turned back is reduced as a whole, and the amount of current decrease is increased toward the center, the current distribution is a bowl-shaped current distribution in which the source potential distribution is inverted. FIG. 6B described later shows a current distribution between the unit output circuits 2a.

  In this way, since the output PMOS section outputs the reference current Iref after further amplification, the distortion of the bowl shape of the output current distribution becomes more conspicuous. As a result, the display panel has a variation in emission luminance. There was a problem of occurrence (Problem 2).

  The present invention has been made in view of the above points, and provides a simple matrix type organic EL light emitting device capable of reducing current consumption when controlling light emission of an organic EL element with a predetermined luminance. With the goal.

  Another object of the present invention is to provide an organic EL light-emitting device capable of obtaining a uniform output current distribution by reducing the voltage fluctuation due to wiring resistance by reducing the peak value of the reference current flowing into the ground line. It is to be.

  In the present invention, in order to solve the above problem, a plurality of scanning lines that connect a plurality of organic EL elements arranged in a matrix in the row direction and a plurality of data lines that connect the organic EL elements in the column direction are used. A simple matrix type organic EL light emitting device is provided that selects and controls light emission at a predetermined luminance.

  The organic EL light emitting device is connected to a reference current generating circuit that sets a driving current supplied to each of the data lines in a predetermined magnitude in synchronization with scanning of the scanning line, and the reference current generating circuit, and A data line driving circuit having a capacitor for holding data corresponding to the magnitude of the driving current, a charging time for writing the data into the capacitor of the data line driving circuit, and turning on the driving current supplied to the data line And a control circuit for controlling the period.

  According to the present invention, in a simple matrix type organic EL light emitting device that controls the light emission of an organic EL element with a predetermined luminance, the current consumption during driving can be reduced by reducing the average current value of the reference current.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a unit output circuit constituting the data line driving circuit of the organic EL light emitting device according to the first embodiment. The configuration of the entire organic EL light emitting device is the same as that shown in FIG. 10 described above, and will be described here with reference to FIG. 10 as necessary.

  The unit output circuit 2 in FIG. 1 includes a pair of PMOS transistors CM0 and CM1, an NMOS transistor NM1 controlled by a reference signal Vref from the reference current generation circuit 21 (see FIG. 10), and an NMOS that controls the output current Iout. It includes a transistor NM2, a capacitor Cs for storing and holding the gate-source voltage Vgs of the PMOS transistor CM0 in the on state, and a PMOS transistor PM1 connected in parallel to the capacitor Cs, and further between the current mirror circuit and the NMOS transistor NM1. The NMOS transistor sw1 that constitutes the switch circuit is arranged, and the PMOS transistor sw2 that constitutes the switch circuit is arranged between the gates of the PMOS transistors CM0 and CM1.

  The pair of PMOS transistors CM0 and CM1 constitute a current mirror circuit when the PMOS transistor sw2 is in an on state. If the PMOS transistor sw2 is in an off state, the gate potential of the PMOS transistor CM1 is applied to the capacitor Cs. It is determined only by the amount of charge held. Further, when the NMOS transistors sw1 and sw2 are on, the capacitor Cs holds data (Vgs) corresponding to the magnitude of the reference current Iref flowing through the NMOS transistor NM1. The gates of these transistors sw1 and sw2 are supplied with the charging period setting signal Wdata and the inverted signal Wdata0 obtained by inverting the charging period setting signal Wdata from the control circuit 22 (see FIG. 10), respectively, to the capacitor Cs. The data writing period is controlled.

  Further, the gate terminal of the PMOS transistor PM1 is supplied with a pulse width modulation signal PWMp for setting the ON period of the organic EL element according to the image signal. In the off period following the on period, the PMOS transistor PM1 functions as a discharge switch that discharges the charge held in the capacitor Cs and erases the data stored therein.

  As described above, in the organic EL light emitting device of the present invention, the reference current Iref is not always supplied to the NMOS transistor NM1, but is supplied to the capacitor Cs in the initial period of the ON period for a period during which the capacitance can be charged (a certain period). The constant current operation can be performed with the gate-source voltage Vgs stored (charged) in the capacitor Cs. Therefore, unlike the conventional organic EL light emitting device configured to flow the reference current Iref regardless of the output current Iout from the data line driving circuit, the data line driving circuit is configured not to consume more current than necessary. By doing so, the average current during the operation of the organic EL panel can be reduced.

FIG. 2 is a signal waveform diagram showing drive timing of the unit output circuit of FIG.
FIGS. 7A and 7B show signal waveform diagrams of the pulse width modulation signals PWMp and PWMn supplied to the unit output circuits 2 from the control circuit 22 shown in FIG. The pulse width modulation signals PWMp and PWMn are complementary signals that are switched to H (high level) and L (low level) signals according to the image signal, and PWMp = H in the on period Ton for lighting the corresponding pixel. A signal of PWMn = L is supplied to the unit output circuit 2. Accordingly, at this time, both the PMOS transistor PM1 and the NMOS transistor NM2 are turned off.

  2C and 2D also show signal waveform diagrams of the charging period setting signals Wdata and Wdata0 supplied from the control circuit 22 to each unit output circuit 2. FIG. Among these, the charging period setting signal Wdata becomes H when the ON period Ton for pixel lighting starts, and the NMOS transistor sw1 is turned on, so that the reference current Iref starts to flow through the NMOS transistor NM1. At the same time, the other charging period setting signal Wdata0 becomes L and the PMOS transistor sw2 is turned on, so that the capacitor Cs is charged according to the gate-source voltage Vgs of the PMOS transistor CM0. Since the gate potential of the pair of PMOS transistors CM0 and CM1 constituting the current mirror circuit is lowered from the DC power supply voltage Vdd by the gate-source voltage Vgs, the output current Iout having a predetermined magnitude is applied to the PMOS transistor CM1 that is turned on. Since the NMOS transistor NM2 is turned off, the output current Iout is output to the corresponding data lines 11a to 11d.

  The capacitor Cs is charged while the charging period setting signal Wdata is H and the other charging period setting signal Wdata0 is “L”, and the capacitor Cs is charged with the gate-source voltage Vgs. When the charging time T1 ends, the charging period setting signals Wdata and Wdata0 are inverted, the transistors sw1 and sw2 are turned off, and the reference current Iref flowing through the NMOS transistor NM1 is cut off (FIG. 2 (e)). When these transistors sw1 and sw2 are turned off, the escape path of the charge charged in the capacitor Cs is cut off, so that the gate potential Vc (FIG. 2 (f)) of the current mirror circuit is caused by the charge held in the capacitor Cs. It is held as (Vdd−Vgs), and the output current Iout can continue to be output at a predetermined magnitude thereafter.

  When the on-period Ton determined according to the image data from the outside ends, the pulse width modulation signal PWMp becomes L, PWMn becomes H, the PMOS transistor PM1 and the NMOS transistor NM2 are turned on, and FIG. As shown, the output current Iout that has flowed until then is eliminated. Further, when the PMOS transistor PM1 is turned on, all charges charged in the capacitor Cs are discharged, and the gate-source voltage Vgs stored therein is erased, so that the next on-period can be prepared.

  In the data line driving circuit described above, as shown in FIG. 2B, it is sufficient that the charging time T1 in which the reference current Iref flows through the NMOS transistor NM1 is only a period during which the capacitor Cs can be charged. As shown, it can be set shorter than the on period Ton determined according to the image data. Therefore, the average value of the consumption current in the NMOS transistor NM1 can be reduced as compared with the configuration in which the reference current Iref is always supplied as in the conventional circuit shown in FIG.

  Here, the capacitance value necessary for holding data in the capacitor Cs is determined by the maximum ON period Ton. For example, when the frame frequency in the organic EL light emitting device is 120 Hz and the number of scanning lines is 120, the maximum value of the on period Ton is about 70 μsec. If the capacitance value can hold data only during this period, Therefore, the charging time T1 that determines the magnitude of the consumption current in the NMOS transistor NM1 only needs to be a period during which the capacitance value of the capacitor Cs can be charged to Vgs with the minimum reference current Iref.

  In the unit output circuit 2 of FIG. 1, an example in which the MOS transistors constituting the switch circuit are the NMOS transistor sw1 and the PMOS transistor sw2, respectively, is shown. However, these switch circuits are both N-channel MOS transistors. Or both of them may be composed of P-channel MOS transistors. Further, the NMOS transistor sw1 and the PMOS transistor sw2 can be interchanged. In any case, the above-described charging period setting signals Wdata and Wdata0 are controlled so that the transistors sw1 and sw2 are turned on at the charging time T1 and are turned off at times other than the charging time T1.

(Embodiment 2)
In addition to the problem 1 related to the battery driving time solved in the first embodiment, the invention that solves the problem of the emission luminance variation (problem 2) in the organic EL light emitting device of the second embodiment will be described.

  FIG. 3 is a circuit diagram showing the overall configuration of the output unit in the conventional data line driving circuit 20. The data line driving circuit 20 shown here is of a type that performs gradation control by a pulse width modulation (PWM) method.

  In the figure, the NMOS transistors M1 to MN of the output circuit 24 constitute a current mirror circuit for the NMOS transistor M0 connected to the constant current source 23 and through which the reference current Iref flows, and inside each unit output circuit, The generated reference current IrefX (X = 1 to N) is folded back to the NMOS transistors M1 to MN constituting each output stage. The folded reference current IrefX is amplified by an output amplifying unit including a pair of PMOS transistors CM0 and CM1, and is output as an output current IoutX (X = 1 to N). Therefore, the magnitude of the output current IoutX can be set to an arbitrary current value by controlling the reference current IrefX.

  In order to reduce the variation between these output currents IoutX, the amplification factor of the output amplification unit is set to about four times. Further, the pulse width control here is performed by turning on / off the PWM control switches SW1 to SWN of each unit output circuit by PWM signals Ion1, Ion2,... IonN generated by the internal digital circuit of the control circuit 22 (FIG. 10). The organic EL element of each pixel is lit during the ON period of the switches SW1 to SWN.

Here, the problem (the problem 2) of the variation in the light emission luminance described above will be described in more detail.
For the PWM signals Ion1, Ion2,... IonN, image data read from the outside of the data line driving circuit 20 is compared with the count value of the PWM counter, and the “H” period is determined according to the comparison result. The image data is stored in a register for comparison with the count value of the PWM counter. Further, the PWM counter starts counting simultaneously with the output permission signal from the outside, and the PWM signals Ion1, Ion2,... IonN are simultaneously set to the “H” state. Thereafter, the image data and the count value of the PWM counter are constantly compared, and when the image data and the count value match, the PWM signals Ion1, Ion2,... IonN are in the “L” state.

  That is, when the PWM counter starts counting by an output permission signal from the outside, the switches SW1 to SWN of the unit output circuits are turned on all at once, and the folded reference current IrefX flows into the ground terminal. Now, assuming that the amplification factor of the output amplification unit is four times, in the data line driving circuit 20 of the organic EL light emitting device in which the output current IoutX is set to 200 μA, the reference currents IrefX each require 50 μA.

FIG. 4 is a chip layout diagram showing the pad layout of the data line driving circuit.
For example, when the number of output terminals is 240, the sum of the reference currents Iref1 to Iref240 is a relatively large current value of 12 mA. Further, in the data line driving circuit 20, since the pitch of the output terminals is narrowly formed, for example, 60 μm pitch, the pad layout of the chip layout is arranged on the left and right sides of the linear VDD wiring 25 as shown in FIG. Pads (VDDPAD) 251 and 252 are disposed, and ground pads (GNDDPAD) 261 and 262 are disposed on the left and right of the GND wiring 26 parallel to the VDD wiring 25. The output current IoutX of the data line driving circuit 20 is taken out from the output terminals (output PAD) 271 to 27N across the VDD wiring 25, respectively. In addition, output amplification regions 281 to 28N, switch regions 291 to 29N, and current mirror regions 2M1 to 2MN are formed between the VDD wiring 25 and the GND wiring 26. As a result, the multiple output terminals 271 to 27N are arranged on one straight line so that their pitches are uniform.

  However, even if the output terminals 271 to 27N are arranged at a narrow pitch, if the number of output terminals is very large, the distance between the ground pads 261 and 262 arranged on both sides of the GND wiring 26 is very large. Will become bigger. That is, in the case of the data line driving circuit 20 having 240 output terminals at a pitch of 60 μm, the pad spacing between the output terminals 271 and 27N requires a width of 13.36 mm. Between 262 is about 15 mm. Therefore, even if the GND wiring 26 connecting between them is a metal wiring, the influence of the wiring resistance generated there cannot be ignored. Further, when the wiring is miniaturized, the influence is further increased.

FIG. 5 is an equivalent circuit diagram specifically showing the wiring resistance of the GND wiring, and FIGS. 6A and 6B are diagrams showing the current distribution and the voltage distribution between the unit output circuits.
In FIG. 5, the output amplifying unit including the PMOS transistors CM0 and CM1 and the switches SW1 to SWN of each unit output circuit in the data line driving circuit 20 of FIG. 3 are omitted. As shown in FIG. 5, wiring resistors R0 to RN exist on the source side of the NMOS transistor M0 through which the reference current Iref flows and the NMOS transistors M1 to MN constituting the output stage. When counting by the PWM counter is started by an output permission signal from the outside, the reference currents Iref1 to IrefN flow into the GND wiring 26 through the wiring resistors R0 to RN all at once. As a result, a voltage drop occurs in each of the wiring resistors R0 to RN, which causes a variation in light emission luminance in the display panel (see FIG. 6).

  In the organic EL light emitting device of the second embodiment described below, the unit output circuit is divided into a plurality of groups instead of simultaneously turning on the PWM control switches SW1 to SWN and causing the reference current IrefX to flow simultaneously. The reference current Iref is supplied in a time-division manner in units of groups. By dividing and flowing the reference current Iref, the voltage drop in the wiring resistances R0 to RN is reduced, so that the distortion of the current distribution is also reduced. Here, the N unit output circuits are divided into m, but the whole may be divided into two groups (m = 2), or three groups (m = 3), four groups (m = 4). Alternatively, the timing of supplying the reference current IrefX may be varied for each unit output circuit (m = N).

FIG. 7 is a diagram showing a unit output circuit constituting the data line driving circuit of the second embodiment.
The unit output circuit 2b of FIG. 7 includes a pair of PMOS transistors CM0 and CM1, an NMOS transistor NM1 controlled by a reference signal Vref from the reference current generation circuit 21 (see FIG. 10), and an on-state PMOS transistor CM0. A capacitor Cs for storing and holding the gate-source voltage Vgs, a PMOS transistor PM1 connected in parallel to the capacitor Cs, an NMOS transistor NM2 and a PMOS transistor PM2 for controlling the output current Iout, and a current mirror circuit and NMOS An NMOS transistor sw1 constituting a switch circuit is arranged between the transistor NM1 and a PMOS transistor sw2 constituting a switch circuit is arranged between the gates of the PMOS transistors CM0 and CM1.

  The pair of PMOS transistors CM0 and CM1 constitute a current mirror circuit when the PMOS transistor sw2 is in an on state. If the PMOS transistor sw2 is in an off state, the gate potential of the PMOS transistor CM1 is applied to the capacitor Cs. It is determined only by the amount of charge held. Further, when the NMOS transistor sw1 and the PMOS transistor sw2 are in the on state, the capacitor Cs holds data (Vgs) corresponding to the magnitude of the reference current Iref flowing through the NMOS transistor NM1. The gates of these transistors sw1 and sw2 are supplied with a charging period setting signal Wdata and an inverted signal Wdata0 obtained by inverting the charging period setting signal Wdata from the control circuit 22 (see FIG. 10), respectively, to the capacitor Cs. The data writing period is controlled at different timing for each group as will be described later. Therefore, in the data line driving circuit 20 including a plurality or one unit output circuit 2b, the data writing period is set to a different timing for each group, and the PMOS transistor PM1 is held in the capacitor Cs in the off period following the on period. It functions as a discharge switch that discharges the stored charge and erases the data stored therein.

  Furthermore, the unit output circuit 2b of FIG. 7 differs from the unit output circuit 2 of the first embodiment in that the discharge for setting the ON period of the organic EL element in accordance with the image signal is applied to the gate terminal of the PMOS transistor PM1. A signal (pulse width modulation signal) Discha is supplied, and an ON / OFF control signal ON / OFF is supplied to the gate terminals of the NMOS transistor NM2 and the PMOS transistor PM2 to control the output current Iout.

FIG. 8 is a signal waveform diagram showing drive timing of the unit output circuit of FIG.
10A shows a signal waveform diagram of the discharge signal Discha supplied from the control circuit 22 shown in FIG. 10 to each unit output circuit 2b, and FIG. 10B shows a signal waveform of the on / off control signal ON / OFF. The figure is shown.

  When the discharge signal Discha from the control circuit 22 becomes “H”, the discharge switch PM1 is turned off, so that the capacitor Cs can be charged. At this time, as shown in FIG. 8C, when the charging period setting signal Wdata is “H” and the inverted signal Wdata0 is “L”, both the NMOS transistor sw1 and the PMOS transistor sw2 are turned on, and the NMOS transistor NM1 is turned on. The reference current Iref flows and charging of the capacitor Cs is started. As shown in FIG. 8E, when the reference current Iref flows through the NMOS transistor NM1, the gate potential Vc of the pair of PMOS transistors CM0 and CM1 constituting the current mirror circuit is changed from the DC power supply voltage Vdd to the gate-source voltage Vgs. Decrease by the minute (FIG. 8 (f)). The capacitor Cs is charged while the charging period setting signal Wdata is “H”, and the gate-source voltage Vgs is charged in the capacitor Cs.

  When the charging period in the unit output circuit 2b ends and the charging period setting signal Wdata becomes “L” (Wdata0 = “H”), the NMOS transistor sw1 and the PMOS transistor sw2 are turned off, and the reference current Iref is cut off. . When all of the NMOS transistor sw1, the PMOS transistor sw2, and the discharge switch PM1 are turned off, the charging / discharging current path of the capacitor Cs is all cut off, so that the gate-source voltage Vgs charged in the capacitor Cs is held. After that, when the charging period in all the groups is completed and the data holding state is established, the output on period is entered, so the on / off control signal ON / OFF becomes “L” and the output current Iout is output from the output terminal (FIG. 8). (G)). When the ON period determined by the frame frequency and image data from the outside ends in all the unit output circuits 2b, the ON / OFF control signal ON / OFF becomes “H” and the discharge signal Discha becomes “L”, so that the output current Iout Is cut off, and the capacitor Cs is discharged, and the gate-source voltage Vgs stored therein is erased. After that, it becomes an off period and prepares for the next on period.

FIG. 9 is a signal waveform diagram showing drive timing constituted by a plurality of output terminals.
The basic timing is the same as that described in the unit output circuit 2b of FIG. 8, but here, the charging period of the unit output circuit 2b is used in order to flow the reference current Iref to the ground terminal in a time-sharing manner between the groups. Each of the signal timings of the setting signal Wdata (FIGS. (C) to (f)) and the reference current Iref (FIGs. (G) to (j)) is shifted in groups.

  As described above, in the organic EL light emitting device of the present invention, the reference current Iref is not always supplied to the NMOS transistor NM1, but is supplied to the capacitor Cs in the initial period of the ON period for a period during which the capacitance can be charged (a certain period). The constant current operation can be performed with the gate-source voltage Vgs stored (charged) in the capacitor Cs. Further, the reference current Iref is caused to flow at different timings for each unit output circuit. Therefore, unlike the conventional organic EL light emitting device configured to flow the reference current Iref for each data line at the same time regardless of the output current Iout from the data line driving circuit, the data line driving circuit is more than necessary. By configuring so that no current is consumed, the average current during the operation of the organic EL panel can be reduced, the peak value of the reference current can be reduced, and a uniform current distribution can be realized in each data line. .

FIG. 3 is a circuit diagram showing a unit output circuit constituting the data line driving circuit of the organic EL light emitting device according to Embodiment 1. FIG. 2 is a signal waveform diagram showing drive timing of the unit output circuit of FIG. 1. It is a circuit diagram which shows the whole structure of an output part among the conventional data line drive circuits. It is a chip layout diagram showing the pad arrangement of the data line driving circuit. FIG. 4 is an equivalent circuit diagram specifically illustrating a wiring resistance of a GND wiring in the data line driving circuit of FIG. 3. It is a figure which shows the current distribution and voltage distribution between each unit output circuit. FIG. 6 is a diagram showing a unit output circuit constituting the data line driving circuit of the second embodiment. FIG. 8 is a signal waveform diagram showing drive timing of the unit output circuit of FIG. 7. It is a signal waveform diagram which shows the drive timing comprised by the several output terminal. It is a circuit diagram which shows the structure of the organic EL light emitting device of a simple matrix system. It is a circuit diagram which shows an example of the unit output circuit which comprises the conventional data line drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Organic EL panel 11a-11d Data line 12a-12c Scan line 20 Data line drive circuit 21 Reference current generation circuit 22 Control circuit 30 Scan line drive circuit CM0, CM1, PM1, sw2 PMOS transistor NM1, NM2, sw1 NMOS transistor Cs capacitor

Claims (6)

  1. A plurality of organic electroluminescence (EL) elements arranged in a matrix are selected by a plurality of scanning lines connecting in the row direction and a plurality of data lines connecting the organic EL elements in the column direction, and emit light with a predetermined luminance. In a simple matrix type organic EL light emitting device to be controlled,
    A reference current generating circuit for setting a driving current supplied to each of the data lines in synchronization with the scanning of the scanning lines to a predetermined magnitude;
    A data line driving circuit having a capacitor connected to the reference current generating circuit and holding data corresponding to the magnitude of the driving current;
    A control circuit for controlling a charging time for writing the data to the capacitor of the data line driving circuit and an on period of the driving current supplied to the data line;
    An organic EL light emitting device comprising:
  2.   2. The organic EL light emitting device according to claim 1, wherein in the control circuit, the current consumption in the data line driving circuit is reduced by controlling the charging time to be shorter than an ON period of the driving current. .
  3. The data line driving circuit includes:
    A current mirror circuit for connecting the gates of a pair of MOS transistors to each other and outputting the drive current at a predetermined magnification;
    A transistor circuit connected to the reference current generation circuit for supplying a reference current to the current mirror circuit;
    A switch circuit disposed between the gates of the pair of MOS transistors and between the current mirror circuit and the transistor circuit;
    A plurality of unit output circuits consisting of
    2. The organic EL light emitting device according to claim 1, wherein the switch circuit is controlled to be turned on for the charging time and data corresponding to the magnitude of the driving current is written to the capacitor.
  4.   4. The organic EL light emitting device according to claim 3, wherein in the data line driving circuit, the reference current flowing through the current mirror circuit flows at a different timing for each unit output circuit corresponding to the data line.
  5.   In the data line driving circuit, the reference current flowing through the current mirror circuit is divided into a plurality of groups of unit output circuits corresponding to the data lines, and flows at different timings for each group. The organic EL light-emitting device according to claim 3.
  6. The data line driving circuit includes a discharge switch for discharging the charge held by the capacitor,
    2. The organic EL light-emitting device according to claim 1, wherein the discharge switch is turned on after the on-period ends to erase data stored in the capacitor.

JP2005055459A 2004-09-08 2005-03-01 Organic el light emitting device Withdrawn JP2006106664A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007304122A (en) * 2006-05-08 2007-11-22 Fuji Electric Holdings Co Ltd Organic el display device
KR20110072293A (en) * 2009-12-22 2011-06-29 엘지디스플레이 주식회사 Backlight unit and liquid crystal display device using the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11311970A (en) * 1998-04-30 1999-11-09 Sony Corp Matrix driving method for current type display elements and matrix driving device for current type display elements
JP2002351400A (en) * 2001-05-30 2002-12-06 Sony Corp Active matrix type display device, active matrix type organic electroluminescence display device and their driving method
JP2003195815A (en) * 2000-11-07 2003-07-09 Sony Corp Active matrix type display device and active matrix type organic electroluminescence display device
JP2003195812A (en) * 2001-08-29 2003-07-09 Nec Corp Semiconductor device for driving current load device and current load device equipped with the same
JP2003308043A (en) * 2002-02-12 2003-10-31 Rohm Co Ltd Organic el driving circuit and organic el display device
JP2004045488A (en) * 2002-07-09 2004-02-12 Casio Comput Co Ltd Display driving device and driving control method therefor
WO2004061809A1 (en) * 2002-12-27 2004-07-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, light-emitting display apparatus, and method for driving them
JP2004206045A (en) * 2002-10-31 2004-07-22 Casio Comput Co Ltd Current generating and supplying circuit and control method therefor, and display device provided therewith

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11311970A (en) * 1998-04-30 1999-11-09 Sony Corp Matrix driving method for current type display elements and matrix driving device for current type display elements
JP2003195815A (en) * 2000-11-07 2003-07-09 Sony Corp Active matrix type display device and active matrix type organic electroluminescence display device
JP2002351400A (en) * 2001-05-30 2002-12-06 Sony Corp Active matrix type display device, active matrix type organic electroluminescence display device and their driving method
JP2003195812A (en) * 2001-08-29 2003-07-09 Nec Corp Semiconductor device for driving current load device and current load device equipped with the same
JP2003308043A (en) * 2002-02-12 2003-10-31 Rohm Co Ltd Organic el driving circuit and organic el display device
JP2004045488A (en) * 2002-07-09 2004-02-12 Casio Comput Co Ltd Display driving device and driving control method therefor
JP2004206045A (en) * 2002-10-31 2004-07-22 Casio Comput Co Ltd Current generating and supplying circuit and control method therefor, and display device provided therewith
WO2004061809A1 (en) * 2002-12-27 2004-07-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, light-emitting display apparatus, and method for driving them

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007304122A (en) * 2006-05-08 2007-11-22 Fuji Electric Holdings Co Ltd Organic el display device
KR20110072293A (en) * 2009-12-22 2011-06-29 엘지디스플레이 주식회사 Backlight unit and liquid crystal display device using the same
KR101633119B1 (en) 2009-12-22 2016-06-24 엘지디스플레이 주식회사 Backlight Unit and Liquid Crystal Display Device using the same

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