JP2006105891A - Integrated circuit, testing technique thereof, and integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase of an electric current flowing through a circuit when the scan path test is implemented. <P>SOLUTION: A multiphase clock supplying circuit 50 is installed, which generates a scan clock signal SCK (k) of (n+1) arising from the clock signal SCLK for test indicating implementation of scan path test, with no overlap mutually and in sequence, to supply the generated scan clock signal SCK (k) to scan flip-flop SFF of (n-1) and one scan flip-flop SFF*. When the scan clock signal SCK (k) is supplied, the scan clock signal SCK (k) is supplied sequentially from the scan flip-flop SFF*, and thus the scan flip-flop SFF and SFF* can be properly acted as an n-bit shift register implementing sequentially the shift action from the scan flip-flop SFF*. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit, a test method therefor, and an integrated circuit device. More specifically, the present invention can store a logic circuit and an operation result input from the logic circuit as data, and can output a plurality of data stored in the logic circuit. The present invention relates to an integrated circuit including the data storage circuit, a test method thereof, and an integrated circuit device.

Conventionally, as a method for performing a scan path test in an integrated circuit including this type of logic circuit, a method that operates using a normal clock signal and a scan clock signal generated from the normal clock signal and the scan clock signal has been proposed. (For example, refer nonpatent literature 1). In this integrated circuit device, since the data of the flip-flop that inputs / outputs data from the logic circuit is normally taken in at the rising edge of the clock signal and the data is outputted at the falling edge of the scan clock signal, it is stable regardless of the clock skew. And can work.
“Scan path test system (1) Scan path configuration”, Proceedings of the 1992 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers [Volume 1] Fundamentals / Boundaries, IEICE, September 27, 1992, p. 1-56

  In the test method described above, when flip-flops are serially connected and synchronized with a normal clock signal or a scan clock signal to operate the flip-flops all at once and function as a shift register, each time 1-bit data is shifted. In addition, a current flows through each flip-flop all at once, and a relatively large current flows in the entire circuit. When such a current flows, the power supply voltage applied to the circuit may decrease, or the temperature of the circuit may increase and the elements constituting each circuit may be thermally damaged.

  An object of the integrated circuit, the test method thereof, and the integrated circuit device of the present invention is to suppress a current flowing in the circuit. Another object of the integrated circuit, the test method thereof, and the integrated circuit device of the present invention is to suppress a drop in power supply voltage applied to the integrated circuit. Furthermore, an object of the integrated circuit, the test method thereof, and the integrated circuit device of the present invention is to suppress thermal damage to elements constituting the circuit.

  The integrated circuit, the test method thereof, and the integrated circuit device of the present invention employ the following means in order to achieve at least a part of the above object.

The integrated circuit of the present invention comprises
A logic circuit; and a plurality of data storage circuits capable of storing data from the logic circuit and outputting the stored data to the logic circuit, the plurality of data storage circuits being accompanied by a predetermined test signal input An integrated circuit that functions as a shift register without data input / output with the logic circuit,
A multi-phase clock supply circuit that generates a plurality of scan clock signals that sequentially rise without overlapping each other and supplies the generated plurality of scan clock signals to the plurality of data storage circuits;
A shift register operating circuit that causes the plurality of data storage circuits to function as a shift register without input / output of data to / from the logic circuit with the input of the scan clock signal;
It is a summary to provide.

  In the integrated circuit of the present invention, the multi-phase clock supply circuits supply a plurality of scan clock signals that sequentially rise without overlapping each other to the plurality of data storage circuits, and the shift register operating circuit receives the scan clock signals. Accordingly, a plurality of data storage circuits are caused to function as a shift register without data input / output with the logic circuit. The plurality of data storage circuits operate in order by receiving a plurality of scan clock signals that sequentially rise without overlapping each other and function as a shift register. Therefore, the plurality of data storage circuits are synchronized with one scan clock signal. Therefore, the current flowing through the integrated circuit can be suppressed more than those that operate all at once and function as a shift register. As described above, since the current flowing through the integrated circuit is suppressed, it is possible to suppress a drop in the power supply voltage applied to the integrated circuit, and it is possible to suppress thermal damage to elements constituting the integrated circuit.

  In such an integrated circuit of the present invention, the shift register operating circuit has two data storage elements having two data storage elements among the plurality of data storage circuits that do not serve as output terminals when functioning as shift registers. It may be a circuit that operates only one of the two data storage elements and causes the data storage circuit to function as one of the storage circuits of the shift register. In this way, for a data storage circuit having two data storage elements among a plurality of data storage circuits that do not serve as output terminals when functioning as a shift register, only one of the two data storage elements is operated. Therefore, the current flowing through the integrated circuit can be further suppressed. In this case, the data storage circuit having the two data storage elements receives the data input from the logic circuit to one data storage element with the input of an execution clock signal used when the logic circuit functions. The shift register operating circuit is a circuit that holds the two data storage elements. For the data storage circuit having the two data storage elements, the one of the data storage elements An input switching circuit that switches an input from an input from the logic circuit to an input when the plurality of data storage circuits function as a shift register, and an output of the one data storage element in accordance with the input of the predetermined test signal Output when the plurality of data storage circuits function as shift registers from the input of the other data storage element An output switching circuit for switching, and a clock switching circuit for switching a clock signal supplied to the one data storage element in response to the input of the predetermined test signal from the execution clock signal to the scan clock signal. The data storage circuit having two data storage elements may be a circuit that functions as one of the storage circuits of the shift register. The data storage circuit having the two data storage elements may include the logic circuit. A circuit for holding data input from the logic circuit to one data storage element with the input of an execution clock signal used for functioning, the shift register operating circuit, For a data storage circuit having two data storage elements, the scan clock signal An input switching circuit for switching an input of the one data storage element from an input from the logic circuit to an input when the plurality of data storage circuits function as a shift register in accordance with an input; and an output of the one data storage element A data storage circuit having the two data storage elements as one of the storage circuits of the shift register by a circuit having an output circuit that outputs when the plurality of data storage circuits function as a shift register It can also be a circuit.

  In the integrated circuit of the present invention, the shift register operating circuit is a data storage circuit having only one data storage element among the plurality of data storage circuits that does not become an output terminal when functioning as a shift register. It is also possible to operate the one data storage element so that the data storage circuit functions as one of the storage circuits of the shift register. In this way, a data storage circuit having only one data storage element among a plurality of data storage circuits that do not serve as output terminals can function as a shift register without adding a data storage element. Increase can be suppressed. In this case, the data storage circuit having only one data storage element holds the data input from the logic circuit with the input of an execution clock signal used when the logic circuit functions. The shift register operating circuit is configured so that, for a data storage circuit having only one data storage element, the input of the data storage element is input from the logic circuit in accordance with the input of the predetermined test signal. An input switching circuit for switching from an input to an input when functioning the plurality of data storage circuits as a shift register; and an output of the data storage element in response to an input of the predetermined test signal from the output to the logic circuit An output switching circuit for switching to an output when the data storage circuit of the data storage circuit functions as a shift register, and the predetermined test A data storage circuit having only one data storage element by a circuit having a clock switching circuit that switches the clock signal supplied to the data storage element from the execution clock signal to the scan clock signal in response to a signal input It can also be a circuit that functions as one of the storage circuits of the shift register, and the data storage circuit that has only one data storage element is an execution clock signal that is used when the logic circuit functions. A circuit that holds data input from the logic circuit with input in the data storage element, and the shift register operating circuit includes the scan clock for a data storage circuit having only one data storage element. The input of the data storage element is input from the logic circuit in accordance with the input of a signal. An input switching circuit that switches to an input when the plurality of data storage circuits function as a shift register, and an output circuit that outputs the data storage element as an output when the plurality of data storage circuits function as a shift register And a circuit that allows a data storage circuit having only the one data storage element to function as one of the storage circuits of the shift register.

  Further, in the integrated circuit of the present invention, the shift register operating circuit is configured such that when the data storage circuit serving as an output terminal when functioning as a shift register is a data storage circuit having two data storage elements, the two data storage circuits are provided. It may be a circuit that operates both of the elements to cause the plurality of data storage circuits to function as a shift register. In this case, the data storage circuit serving as the output terminal stores the data input from the logic circuit to one data storage element with the input of an execution clock signal used when the logic circuit functions. The shift register operating circuit is a circuit that holds the data storage element, and the data storage circuit having the data storage element serving as the output terminal, the input of the one data storage element with the input of the predetermined test signal An input switching circuit for switching from an input from the logic circuit to an input when the plurality of data storage circuits function as a shift register, and an output of the other data storage element in accordance with the input of the predetermined test signal Output switching for switching from output to the logic circuit to output when the plurality of data storage circuits function as shift registers A first clock switching circuit for switching a clock signal supplied to the one data storage element in response to the input of the predetermined test signal from the execution clock signal to the scan clock signal, and the predetermined test signal A second clock switching circuit that switches a clock signal supplied to the other data storage element upon input from the execution clock signal to a scan clock signal that does not overlap with the scan clock signal switched by the first clock switching circuit; The data storage circuit serving as the output terminal is a circuit that functions as a storage circuit at the end of the shift register by a circuit having a circuit, or the data storage circuit serving as the output terminal is used when the logic circuit functions. One data storage from the logic circuit with the input of an execution clock signal The data input to the child is held by the one data storage element, and the shift register operating circuit is configured to store the predetermined test signal for the data storage circuit having the data storage element serving as the output terminal. An input switching circuit for switching an input of the one data storage element from an input from the logic circuit to an input when the plurality of data storage circuits function as a shift register in accordance with the input; and an input of the predetermined test signal Accordingly, the output switching circuit for switching the output of the one data storage element from the output to the logic circuit to the input of the other data storage element, and the one data storage element according to the input of the predetermined test signal A clock switching circuit for switching a clock signal to be supplied from the execution clock signal to the scan clock signal; And a scan clock supply circuit that supplies a scan clock signal that does not overlap with the scan clock signal switched by the clock switching circuit to the other data storage element. It may be a circuit that functions as a storage circuit. In this case, the plurality of data storage circuits are composed of n data storage circuits having two data storage elements, and the shift register operating circuit includes the n data storage circuits in n bits. The multi-phase clock supply circuit generates (n + 1) scan clock signals that sequentially rise without overlapping each other, and functions as a shift register among the n data storage circuits. (N-1) scan clock signals are supplied to the (n-1) memory circuits that do not become output terminals when the data is output, and two scan clock signals are supplied to the data memory circuit serving as the output terminal. It can also be a circuit.

  In the integrated circuit of the present invention, when the shift register operating circuit is a data storage circuit having only one data storage element when the data storage circuit serving as the output end when functioning as a shift register is used as the output end, A circuit that operates the data storage element of the data storage circuit and the data storage element of the data storage circuit adjacent to the data storage circuit serving as the output terminal to cause the plurality of data storage circuits to function as a shift register. You can also In this case, the data storage circuit serving as the output terminal receives data input from the logic circuit to the data storage element with the input of an execution clock signal used when the logic circuit is functioned. The shift register operating circuit is a circuit that holds the data storage element having the data storage element serving as the output terminal, and the logic circuit receives the input of the data storage element in response to the input of the predetermined test signal. An input switching circuit for switching from the input to the input when the plurality of data storage circuits function as a shift register, and the output of the data storage element to the logic circuit when the predetermined test signal is input An output switching circuit for switching to an output when the plurality of data storage circuits function as a shift register; and A clock switching circuit for switching the clock signal supplied to the data storage element from the execution clock signal to the scan clock signal in response to the input of the strike signal, and the data storage circuit serving as the output terminal by the circuit having the shift register It may be a circuit that functions as a memory circuit at the end. Further, in this case, the plurality of data storage circuits are composed of n data storage circuits having only one data storage element, and the shift register operating circuit includes the n data storage circuits ( n-1) A circuit that functions as a bit shift register, wherein the multi-phase clock supply circuit generates n scan clock signals that sequentially rise without overlapping each other, and the n data storage circuits have n It may be a circuit that supplies the scan clock signal.

  In the integrated circuit of the present invention, the multi-phase clock supply circuit may be a circuit that sequentially supplies a scan clock signal from a data storage circuit serving as an output terminal when functioning as a shift register. In this way, the plurality of data storage circuits can function as shift registers by operating sequentially from the data storage circuit serving as the output terminal.

  An integrated circuit device of the present invention is an integrated circuit of the present invention according to any one of the above-described aspects, that is, basically an integrated circuit on which a logic circuit is mounted, and can store data from the logic circuit. A plurality of data storage circuits that can output data stored together to the logic circuit and a plurality of scan clock signals that sequentially rise without overlapping each other with the input of a predetermined test signal The multi-phase clock supply circuit for supplying a plurality of scan clock signals to the plurality of data storage circuits, and the plurality of data storage circuits together with the input of the predetermined test signal and the input of the scan clock signal. Provided with a plurality of integrated circuits including a shift register operating circuit that functions as a shift register without data input / output with a logic circuit The gist.

  Since the integrated circuit device of the present invention includes a plurality of the integrated circuits of the present invention according to any one of the above-described aspects, the effect of the integrated circuit of the present invention, for example, the effect of suppressing the current flowing in the integrated circuit or the integrated circuit The effect similar to the effect which can suppress that the power supply voltage applied to this falls, the effect which can suppress the thermal damage of the element which comprises an integrated circuit, etc. can be show | played.

The integrated circuit test method of the present invention comprises:
A test method for an integrated circuit for performing a scan path test on an integrated circuit having a logic circuit and a plurality of data storage circuits capable of storing data from the logic circuit and outputting the stored data to the logic circuit,
A predetermined test signal is input to the integrated circuit, and a plurality of scan clock signals that rise in order without overlapping each other are supplied to the plurality of data storage circuits, and the plurality of data storage circuits are connected to the logic circuit. The gist of the invention is to perform a scan path test of the integrated circuit by functioning as a shift register without any input / output.

  According to the integrated circuit test method of the present invention, a plurality of data storage circuits are provided by inputting a predetermined test signal to the integrated circuit and supplying a plurality of scan clock signals rising sequentially without overlapping each other to the plurality of data storage circuits. Functions as a shift register that does not involve input / output of data to / from the logic circuit, and performs a scan path test on the integrated circuit. The plurality of data storage circuits operate in order by receiving a plurality of scan clock signals that sequentially rise without overlapping each other and function as a shift register. Therefore, the plurality of data storage circuits are synchronized with one scan clock signal. Therefore, the current flowing through the integrated circuit can be suppressed more than those that operate all at once and function as a shift register. As described above, since the current flowing through the integrated circuit is suppressed, it is possible to suppress a drop in the power supply voltage applied to the integrated circuit, and it is possible to suppress thermal damage to elements constituting the integrated circuit.

  Next, the best mode for carrying out the present invention will be described using examples.

  FIG. 1 is a configuration diagram showing an outline of a configuration of a semiconductor integrated circuit device 20 on which a plurality of semiconductor integrated circuits 10 according to an embodiment of the present invention are mounted. The semiconductor integrated circuit device 20 normally performs normal operations on the execution clock signal CLK and the operation mode of the circuit under test 30 for causing each semiconductor integrated circuit 10 to function as the normal arithmetic unit from the outside of the device. Necessary signals such as a switch signal SW for switching from an operation mode to a test mode for performing a scan path test and a test clock signal SCLK for scan path test supplied to each multiphase clock supply circuit 50 are input, or the semiconductor integrated circuit 10 To output various data signals (not shown) that are output when the circuit under test 30 functions as a normal arithmetic unit. As will be described later, each circuit under test 30 includes a shift register that receives the scan input scin and outputs the scan output scout in the test mode. Each circuit under test 30 receives scan path test data SCIN serially input from the outside of the semiconductor integrated circuit device 20 via the shift register of each circuit under test 30, and the operation result in each circuit under test 30 is obtained. The scan output scout is appropriately connected to the input scin of another circuit under test 30 so as to be output serially as scan output data SCOUT to the outside of the integrated circuit device 20.

  FIG. 2 is a configuration diagram showing an outline of the configuration of the semiconductor integrated circuit 10. The semiconductor integrated circuit 10 is a circuit under test 30 to be subjected to a scan path test, and a multiphase clock supply circuit for supplying (n + 1) scan clock signals SCK (k) that sequentially rise without overlapping each other to the circuit under test 30. 50.

  As shown in FIG. 2, the circuit under test 30 can store data input from the combinational circuit 31 and outputs n stored data to the combinational circuit 31 as (n− 1) scan flip-flops SFF and scan flip-flops SFF * located at one end of the (n-1) scan flip-flops SFF. Each scan flip-flop SFF and scan flip-flop SFF * function as a shift register in the test mode and scan output scout so that the scan flip-flop SFF * becomes a data storage circuit at the output end when functioning as a shift register. Are connected to the scan input scin.

  FIG. 3 is a configuration diagram showing an outline of the circuit configuration of the scan flip-flop SFF. As shown in the figure, the scan flip-flop SFF changes the input of the latch L1 from the input d from the combinational circuit 31 to the scan input sin when the two latches L1 and L2 and the switch signal SW are set (becomes high level). The input switching circuit 32 for switching, the output switching circuit 34 for switching the output of the latch L1 from the input of the latch L2 to the scan output scout when the switch signal SW is set, and the latch L1 when the switch signal SW is set. And a clock switching circuit for switching the clock signal from an input clk to which the execution clock signal CLK is supplied to an input sck to which the scan clock signal SCK (k) is supplied. In the normal operation mode in which the switch signal SW is not set, the scan flip-flop SFF holds the data input from the input d to the latch L1 in synchronization with the execution clock signal CLK input from the input clk, and outputs the output q In the test mode in which the switch signal SW is set, the latch L2 is not operated, and the data input from the scan input sin is synchronized with the scan clock signal SCK (k) supplied from the input sck by the latch L1. Store and output from output scout. Thus, in the test flip-flop SFF, the latch L1 operates but the latch L2 does not operate in the test mode in which the switch signal SW is set.

  FIG. 4 is a configuration diagram showing an outline of the circuit configuration of the scan flip-flop SFF *. As shown in the figure, the scan flip-flop SFF * includes two latches L1 and L2, and an input switching circuit 42 that switches the input of the latch L1 from the input d from the combinational circuit 31 to the scan input sin when the switch signal SW is set. When the switch signal SW is set, the output switching circuit 44 switches the output of the latch L2 from the output q to the combinational circuit 31 to the scan output scout, and when the switch signal SW is set, the clock signal input to the latch L1. Is switched from the execution clock signal CLK supplied from the input clk to the scan clock signal SCK (k) supplied from the input sck2, and the clock signal input to the latch L2 when the switch signal SW is set. For the execution supplied from the input clk And a clock switching circuit 48 to switch to the scan clock signal SCK (k) supplied from the input sck1 from click signal CLK. In the normal operation mode in which the switch signal SW is not set, the scan flip-flop SFF * holds the data input from the input d to the latch L1 in synchronization with the execution clock signal CLK supplied from the input clk and outputs the data in the latch L2. In the test mode in which the switch signal SW is output from q, the data held in the latch L2 is output from the output scout in synchronization with the scan clock signal SCK (k) supplied from the input sck1, and the input sck2 In synchronization with the scan clock signal SCK (k) input from, data input from the scan input scin is stored in the latch L1. Thus, in the scan flip-flop SFF *, both the latch L1 and the latch L2 operate in the test mode in which the switch signal SW is set.

  FIG. 5 is a configuration diagram showing an outline of the circuit configuration of the multiphase clock supply circuit 50. As shown in the figure, the multiphase clock supply circuit 50 includes a plurality of delay circuits 52 having a delay time T1, a plurality of delay circuits 54 having a delay time T2, and a plurality of logic operation circuits for calculating a logical sum of two input signals. 56, and a test clock signal SCLK and a signal obtained by delaying and inverting the test clock signal SCLK by the delay circuit 52 are input to the logic operation circuit 56, and the scan clock of T1 time from the start of the rise to the start of the fall A signal SCK (1) is generated, a signal obtained by delaying the output signal of the delay circuit 52 used for generating the scan clock signal SCK (1) by the delay circuit 54, and a signal obtained by delaying and inverting this signal by the delay circuit 52 Are input to the logic operation circuit 56, and the rising of the scan clock signal SCK (1) is delayed by T2 time from the start of falling. Generating a scan clock signal SCK (2), and is configured to generate a scan clock signal SCK (n + 1) sequentially from the scan clock signal SCK in the same manner as (3). Here, the delay time T1 and the delay time T2 are set so that the scan clock signals SCK (k) do not overlap each other. FIG. 6 is a timing chart showing the correlation between each scan clock signal SCK (k) generated by the multiphase clock supply circuit 50 and the test clock signal SCLK. Thus, the multiphase clock supply circuit 50 generates (n + 1) scan clock signals SCK (k) that do not overlap with each other from the input test clock signal SCLK.

  Next, how the scan flip-flops SFF and SFF * function as an n-bit shift register will be described while explaining a method of performing a scan path test in the semiconductor integrated circuit 10 configured as described above. FIG. 7 is a flowchart showing an example of the scan path test method, and FIG. 8 is a timing chart showing the correlation between signals inputted to and outputted from the semiconductor integrated circuit 10 in the test mode. First, as shown in FIG. 8, the switch signal SW is set so that the scan flip-flops SFF and SFF * are operated in the test mode, and the execution clock signal CLK is fixed to low without pulse input and is used for testing. The clock signal SCLK is input to the multiphase clock supply circuit, and scan data SCIN composed of n-bit data is input (step S100).

  Here, consider a case where the test clock signal SCLK is pulsed once and one bit of the n-bit scan data SCIN is input. When the test clock signal SCLK is pulsed once, (n + 1) scan clock signals SCK (k) are sequentially supplied to the scan flip-flops SFF and SFF * by the multiphase clock supply circuit 50. FIG. 9 is an explanatory diagram for explaining the output signal O (k) of the scan flip-flops SFF and SFF *. As shown, the output signal O (K) is an output signal O (1) from the latch L2 of the scan flip-flop SFF *, and an output signal O (1) from the latch L1 of the scan flip-flop SFF *. 2) The output signal of the scan flip-flop SFF adjacent to the scan flip-flop SFF * is the output signal O (3), and the output signals of the scan flip-flop SFF are sequentially referred to as output signals O (4) to O (n + 1). . FIG. 10 is a timing chart showing the correlation between the scan clock signal SCK (k) and the output signal O (k). As shown in the figure, the latch L2 of the scan flip-flop SFF * does not determine data before the scan clock signal SCK (1) is input, and the scan clock signal SCK (1) is not converted to the scan flip-flop SFF *. Is input, the data S (1) held in the latch L1 of the scan flip-flop SFF * is fetched and output as an output signal O (1). When the scan clock signal SCK (2) is input to the scan flip-flop SFF * following the scan clock signal SCK (1), the latch L1 of the scan flip-flop SFF * is moved to the scan flip-flop SFF adjacent to the scan flip-flop SFF *. Captures the data signal S (2) held by the signal and outputs it as an output signal O (2). Thereafter, similarly, when the scan clock signal SCK (k) is sequentially input to the scan flip-flop SFF, the scan flip-flop SFF to which the scan clock signal SCK (k) is input captures and outputs data from the adjacent scan flip-flop SFF. Finally, the scan flip-flop SFF to which the scan clock signal SCK (n + 1) is input takes 1 bit of the scan data SCIN and ends the 1-bit shift operation.

  Subsequently, by inputting the scan clock signal SCK (n−1) times, the remaining (n−1) -bit scan data SCIN is captured and held in the scan flip-flops SFF and SFF *. In this way, the scan flip-flops SFF and SFF * are caused to function as a shift register that shifts data by 1 bit for each cycle of the test clock signal SCLK. At this time, since the scan flip-flop SFF operates only on the latch L1 of the latches L1 and L2, the current that flows when performing a 1-bit shift operation is smaller than that in which both the latches L1 and L2 operate. In addition, since all the scan flip-flops SFF and SFF * do not operate at a time and are sequentially shifted with the input of the scan clock signal SCK (k) that does not overlap each other, all the scan flip-flops perform the shift operation at a time. When compared with the one, the peak value of the operating current when accompanied by the 1-bit shift operation becomes smaller. Thus, since the current flowing through the semiconductor integrated circuit 10 is suppressed, a drop in the power supply voltage of the semiconductor integrated circuit 10 can be suppressed. In addition, since the generation of heat in the semiconductor integrated circuit 10 is also suppressed, thermal damage to elements constituting the semiconductor integrated circuit 10 can be suppressed. In the semiconductor integrated circuit 10 of the embodiment, the frequency of the test clock signal SCLK can be generated while the multiphase clock supply circuit 50 can generate (n + 1) scan clock signals SCK (k) from the test clock signal SCLK. Although the scan clock signal SCK (k) is limited to a frequency at which the scan flip-flops SFF and SFF * can operate, the current in the circuit is suppressed. It is also possible to make the scan flip-flop of the same size as that of the shift flip-flop.

  When the n-bit scan data SCIN is input in this way, as shown in FIG. 8, the switch signal SW is fixed to a low level and the supply of the test clock signal SCLK is stopped, and the execution clock signal CLK is pulsed once. Then, the circuit under test 30 of the semiconductor integrated circuit 10 is operated in the normal operation mode, and the operation result obtained by inputting the scan data SCIN to the combinational circuit 31 is held by the scan flip-flops SFF and SFF * (step S120). . Subsequently, the switch signal SW is set so that the circuit under test 30 of the semiconductor integrated circuit 10 operates in the test mode so that the execution clock signal CLK is fixed to a low level without pulse input, and the test clock signal SCLK is Input to the multiphase clock supply circuit and output the data held by the scan flip-flops SFF and SFF * as the operation result data SCOUT while the scan flip-flops SFF and SFF * function as a shift register as described above (step S140). ). The operation of the circuit under test 30 can be tested by comparing the output operation result data SCOUT with expected value data expected as the result of the operation in the circuit under test 30.

  According to the semiconductor integrated circuit 10 of the embodiment described above, when the scan flip-flops SFF and SFF * function as a shift resist, the scan flip-flops SFF and SFF * are accompanied by the input of the scan clock signals SCK (k) that do not overlap each other. Therefore, it is possible to suppress the operating current associated with the 1-bit shift operation as compared with the case where all the scan flip-flops operate at once. As described above, since the operating current is suppressed, it is possible to suppress the power supply voltage drop of the semiconductor integrated circuit 10 and the thermal damage of the elements constituting the semiconductor integrated circuit 10.

  In the semiconductor integrated circuit 10 of the embodiment, the circuit under test 30 includes a scan flip-flop SFF having (n−1) two latches L1 and L2 as n data storage circuits. The scan flip-flop SFF may be composed of one latch L1. FIG. 11 is a configuration diagram showing an outline of the configuration of the semiconductor integrated circuit 110 when the scan flip-flop SFF is a scan latch SL composed of one latch, and FIG. 12 shows an outline of the circuit configuration of the scan latch SL. FIG. 13 is a block diagram showing an outline of the circuit configuration of the scan latch SL * that becomes an output terminal when each scan latch SL functions as a shift register. As shown in FIG. 12, the scan latch SL includes a latch L1, an input switching circuit 132 that switches the input of the latch L1 from the input d from the combinational circuit 31 to the scan input sin when the switch signal SW is set, and a switch signal. When SW is set, the output switching circuit 134 switches the output of the latch L1 from the output q to the scan output scout, and when the switch signal SW is set, the clock signal input to the latch L1 is the execution clock signal CLK1 or execution And a clock switching circuit 136 for switching from an input clk to which an execution clock signal CLK2 not overlapping with the clock signal CLK1 is supplied to an input sck to which a scan clock signal SCK (k) is supplied. In the normal operation mode in which the switch signal SW is not set, the scan latch SL latches the data input from the input d to the latch L1 in synchronization with the execution clock signal CLK1 or the execution clock signal CLK2 input from the input clk. In the test mode in which the switch signal SW is set and output from the output q and the switch signal SW is set, the data input from the scan input sin is stored in the latch L1 in synchronization with the scan clock signal SCK (k) supplied from the input sck. Output from output scout. As shown in FIG. 13, the scan latch SL * includes latches L1 and L2, and when the switch signal SW is set, the input switch circuit 142 that switches the input of the latch L1 from the input d to the scan input sin, and the switch signal SW Is set, the output switching circuit 144 switches the output of the latch L1 from the output q to the input of the latch L2. In the normal operation mode in which the switch signal SW is not set, the scan latch SL * holds the data input from the input d to the latch L1 in synchronization with the execution clock signal CLK2 input from the input clk and outputs the output q In the test mode in which the switch signal SW is set, the data held in the latch L1 is captured by the latch L2 and output from the output scout in synchronization with the scan clock signal SCK (k) supplied from the input sck1. The data inputted from the scan input scin is fetched and held in the latch L1 in synchronization with the scan clock signal SCK (k) supplied from the input sck2. The scan latches SL and SL * configured in this manner function as a shift resist that performs a shift operation in order from the scan latch SL * when the scan clock signals SCK (k) that do not overlap each other are supplied in order from the scan latch SL *. . Even in this configuration, since the shift operation is sequentially performed in accordance with the input of the scan clock signal SCK (k), the operation current at the time of the 1-bit shift operation is suppressed as compared with the case where all the scan flip-flops perform the shift operation at a time. can do. In addition, in order for a circuit using a single latch as a data storage circuit to function as a shift register, it is necessary to separately add a test latch to each data storage circuit, increasing the circuit area. However, when the configuration shown in FIG. 11 is used, it is not necessary to add a test latch separately to the scan latch SL, and only the scan latch SL * serving as the output end is provided with two latches. Therefore, an increase in circuit area can be suppressed. Further, if another scan latch located next to the scan latch SL * at the output end is operated as a part of the shift register, the scan latch SL * can be configured as a circuit having only one latch. FIG. 14 is a configuration diagram showing an outline of the configuration of the semiconductor integrated circuit 210 when the scan latch SL * is a circuit composed of one latch. In the semiconductor integrated circuit 210, the scan latches SL and SL * all have the same circuit configuration as the scan latch SL shown in FIG. The semiconductor integrated circuit 210 includes (n−2) scan latches SL, one scan latch SL *, and a scan latch SL2 located next to the scan latch SL *. In the semiconductor integrated circuit 210, n scan clock signals SCK (k) are supplied from the multiphase clock supply circuit to the scan latches SL, SL *, SL2, and (n-2) scan latches SL and scan latch SL * are supplied. And function as an (n−1) -bit shift register. In this way, all the scan latches can be provided with only one latch. As described above, a scan flip-flop having two latches may be used for the data storage circuit, or a scan latch composed of one latch may be used, and the scan flip-flop and the scan latch are mixed. A scan flip-flop having two or more latches may be used.

  In the semiconductor integrated circuit 10 of the embodiment, the switch signal SW is input to the scan flip-flops SFF and SFF * to switch the semiconductor integrated circuit 10 from the normal operation mode to the test mode. The semiconductor integrated circuit is switched from the normal operation mode to the test mode by changing the execution clock signal CLK or the scan clock signal SCK (k) by supplying the CLK to a clock supply circuit (not shown) or the multiphase clock supply circuit 50 that supplies CLK. It may be a thing. FIG. 15 is a configuration diagram showing an outline of a circuit configuration of the scan flip-flop SFF3 used in such a semiconductor integrated circuit. The scan flip-flop SFF3 includes data storage elements 350 and 352 connected in cascade. The data storage elements 350 and 352 include cascaded inverters INV1 and INV2, and an inverter INV3 connected so that the output of the inverter INV1 is input. The inverter INV3 feeds back the output of the inverter INV1 to the input of the inverter INV1. Configured to hold data. A transistor Tr1 that is turned on / off by a clock signal from the input clk is provided between the input of the data storage element 350 and the input d, and an input is provided between the output of the data storage element 350 and the input of the data storage element 352. A transistor Tr2 that is turned on / off by a clock having a phase opposite to that of the clock signal from the clk is provided. Further, a transistor Tr3 that is turned on / off by a clock signal supplied from the input sck is provided between the input of the data storage element 350 and the scan input sin. FIG. 16 is a timing chart showing the correlation between the signals of the scan flip-flop SFF3. When the scan flip-flop SFF3 is in the normal operation mode, the scan clock signal SCK (k) supplied to the input sck is fixed to a low level, and when the execution clock signal CLK supplied to the input clk becomes a high level, The data D is taken in by the data storage element 350, and when the execution clock signal CLK becomes low level, the data in the data storage element 350 is taken in by the data storage element 352 and output as data Q from the output q. On the other hand, in the test mode, the execution clock signal CLK supplied to the input clk is fixed to a low level. The data is held at 350 and output from the scan output scout as data SCOUT. Similarly to the scan flip-flop SFF shown in FIG. 3, the scan flip-flop SFF3 operates only as the data storage element 350 in the test mode and functions as a shift register. Therefore, the scan flip-flop SFF3 is used as a semiconductor integrated circuit. Even if it is mounted on, the increase in operating current can be suppressed. The scan flip-flop SFF3 includes the two data storage elements 350 and 352. However, the scan flip-flop SFF3 may include only one data storage element as illustrated in the scan latch SL3 of the modification of FIG. The scan latch SL3 is configured such that the data storage element 352 and the transistor Tr2 of the scan flip-flop SFF3 shown in FIG. 15 are excluded, and the output of the data storage element 350 becomes an output q and a scan output scout. FIG. 18 is a timing chart showing the correlation between signals of the scan latch SL3. When the scan latch SLL3 is in the normal operation mode, the scan clock signal SCK (k) supplied to the input sck is fixed to a low level, and the execution clock signal CLK supplied to the input clk becomes a high level. Data D is held in the data storage element 350 and output as data Q from the output q. On the other hand, in the test mode, the execution clock signal CLK supplied to the input clk is fixed to low, and when the scan clock signal SCK (k) is supplied from the input sck, the data SCIN from the scan input scin is stored in the data storage element 350. And at the same time output from the scan output scout as data SCOUT. Similarly to the scan latch SL illustrated in FIG. 12, the scan latch SL3 does not require a separate test latch, and thus can suppress an increase in circuit area.

  In the semiconductor integrated circuit 10 of the embodiment, the scan flip-flops SFF and SFF * include the circuits having the configuration shown in FIGS. 3 and 4 as the peripheral circuits of the latch L1 and the latch L2. May be provided with circuits having various configurations as long as the same operation as that of the scan flip-flops SFF and SFF * is realized.

  In the semiconductor integrated circuit 10 of the embodiment, the multiphase clock supply circuit 50 having the circuit configuration shown in FIG. 5 is used, but a clock having another configuration capable of generating a plurality of clock signals that do not overlap each other from a predetermined clock signal. A supply circuit may be used.

  In the semiconductor integrated circuit 10 of the embodiment, each circuit such as the combinational circuit 31 and the scan flip-flops SFF and SFF * is operated at the rising edge of various signals, but may be operated at the falling edge.

  In the semiconductor integrated circuit device 20 according to the embodiment, the plurality of multiphase clock supply circuits 50 each supply the scan clock signal SCK (k) to the circuit under test 30. The scan clock signal SCK (k) may be supplied to the circuit under test.

  In the semiconductor integrated circuit device 20 of the embodiment, the scan clock signal SCK (k) is supplied from the mounted multiphase clock supply circuit 50 to the circuit under test 30, but the scan is performed from the outside of the semiconductor integrated circuit device 20. The clock signal SCK (k) may be supplied to the circuit under test 30.

  The best mode for carrying out the present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the gist of the present invention. Of course, it can be implemented in the form.

1 is a configuration diagram schematically showing a configuration of a semiconductor integrated circuit device 20 on which a plurality of semiconductor integrated circuits 10 according to an embodiment of the present invention are mounted. 1 is a configuration diagram showing an outline of a configuration of a semiconductor integrated circuit 10. It is a block diagram which shows the outline of a circuit structure of scan flip-flop SFF. It is a block diagram which shows the outline of a circuit structure of scan flip-flop SFF *. 2 is a configuration diagram showing an outline of a circuit configuration of a multiphase clock supply circuit 50. FIG. 4 is a timing chart showing a correlation between each scan clock signal SCK (k) generated by the multiphase clock supply circuit 50 and a test clock signal SCLK. It is a flowchart which shows an example of a scan path test method. 6 is a timing chart showing the correlation between signals input to and output from an integrated circuit device in a test mode. It is explanatory drawing explaining the output signal O (k) of scan flip-flop SFF, SFF *. 6 is a timing chart showing a correlation between a scan clock signal SCK (k) and an output signal O (k). FIG. 2 is a configuration diagram showing an outline of a configuration of a semiconductor integrated circuit 110 when a scan flip-flop SFF * is a scan latch SL composed of one latch. It is a block diagram which shows the outline of the circuit structure of scan latch SL. FIG. 3 is a configuration diagram showing an outline of a circuit configuration of a scan latch SL * that becomes an output terminal when each scan latch SL functions as a shift register. It is a block diagram which shows the outline of a structure of the semiconductor integrated circuit 210 when the scan latch SL * is a circuit comprising one latch. It is a block diagram which shows the outline of a circuit structure of scan flip flip SFF3. It is a timing chart which shows the correlation of each signal input / output to scan flip-flop SFF3. It is a block diagram which shows the outline of a circuit structure of scan latch SL3. It is a timing chart which shows the correlation of each signal input / output to scan flip-flop SL3.

Explanation of symbols

10, 110, 210 Semiconductor integrated circuit, 20 Semiconductor integrated circuit device, 30 Circuit under test, 31 Combinational circuit, 32, 42, 132, 134 Input switching circuit, 34, 44, 134, 144 Output switching circuit, 36, 46, 48, 136, 146 clock switching circuit, 50 multiphase clock supply circuit, 52, 54 delay circuit, 56 logic operation circuit, INV1, INV2, INV3 inverter, SFF, SFF *, SFF3 scan flip-flop, SL1, SL *, SL2 , SL3 scan latch, Tr1, Tr2, Tr3 transistors.

Claims (17)

A logic circuit; and a plurality of data storage circuits capable of storing data from the logic circuit and outputting the stored data to the logic circuit, the plurality of data storage circuits being accompanied by a predetermined test signal input An integrated circuit that functions as a shift register without data input / output with the logic circuit,
A multi-phase clock supply circuit that generates a plurality of scan clock signals that sequentially rise without overlapping each other and supplies the generated plurality of scan clock signals to the plurality of data storage circuits;
A shift register operating circuit that causes the plurality of data storage circuits to function as a shift register without input / output of data to / from the logic circuit with the input of the scan clock signal;
An integrated circuit comprising:   The shift register operating circuit is one of the two data storage elements for a data storage circuit having two data storage elements among the plurality of data storage circuits that do not serve as output terminals when functioning as a shift register. 2. The integrated circuit according to claim 1, wherein only one of the data storage circuits is operated so that the data storage circuit functions as one of the storage circuits of the shift register. An integrated circuit according to claim 2, wherein
The data storage circuit having the two data storage elements stores the data input from the logic circuit to one data storage element with the input of an execution clock signal used when the logic circuit functions. It is a circuit held by the element,
For the data storage circuit having the two data storage elements, the shift register operating circuit receives the input of the one data storage element from the input from the logic circuit in accordance with the input of the predetermined test signal. An input switching circuit for switching to an input when functioning the data storage circuit as a shift register, and an output of the one data storage element from the input of the other data storage element in accordance with the input of the predetermined test signal An output switching circuit for switching to an output when the data storage circuit is functioned as a shift register, and a clock signal supplied to the one data storage element in accordance with the input of the predetermined test signal from the execution clock signal A clock switching circuit for switching to a scan clock signal, and the two data Integrated circuit is a circuit to function data storage circuit having a 憶素Ko as one of the memory circuits of the shift register. An integrated circuit according to claim 2, wherein
The data storage circuit having the two data storage elements stores the data input from the logic circuit to one data storage element with the input of an execution clock signal used when the logic circuit functions. It is a circuit held by the element,
For the data storage circuit having the two data storage elements, the shift register operating circuit receives the input of the one data storage element from the input from the logic circuit in accordance with the input of the scan clock signal. An input switching circuit that switches to an input when the data storage circuit functions as a shift register; an output circuit that outputs the output of the one data storage element as an output when the plurality of data storage circuits function as a shift register; A circuit that causes a data storage circuit having the two data storage elements to function as one of the storage circuits of a shift register by a circuit having an integrated circuit.   The shift register operating circuit operates one data storage element for a data storage circuit having only one data storage element among the plurality of data storage circuits that do not serve as output terminals when functioning as a shift register. 5. The integrated circuit according to claim 1, wherein the data storage circuit functions as one of storage circuits of a shift register. An integrated circuit according to claim 5, wherein
The data storage circuit having only one data storage element is a circuit that holds data input from the logic circuit with the input of an execution clock signal used when the logic circuit is functioned. Yes,
For the data storage circuit having only one data storage element, the shift register operating circuit receives the input of the data storage element from the input from the logic circuit in accordance with the input of the predetermined test signal. An input switching circuit for switching to an input when the data storage circuit functions as a shift register, and an output of the data storage element in response to the input of the predetermined test signal from the output to the logic circuit to the plurality of data storage circuits An output switching circuit for switching to an output when functioning as a shift register, and a clock switching for switching a clock signal supplied to the data storage element in response to the input of the predetermined test signal from the execution clock signal to the scan clock signal A data storage device having only the one data storage element. Integrated circuit is a circuit to function circuit as one of the memory circuits of the shift register. An integrated circuit according to claim 5, wherein
The data storage circuit having only one data storage element is a circuit that holds data input from the logic circuit with the input of an execution clock signal used when the logic circuit is functioned. Yes,
For the data storage circuit having only one data storage element, the shift register operating circuit changes the input of the data storage element from the input from the logic circuit in accordance with the input of the scan clock signal. A circuit having an input switching circuit that switches to an input when the storage circuit functions as a shift register, and an output circuit that outputs the output of the data storage element when the plurality of data storage circuits function as a shift register An integrated circuit which is a circuit that causes a data storage circuit having only one data storage element to function as one of the storage circuits of a shift register.   When the shift register operating circuit is a data storage circuit having two data storage elements when the data storage circuit serving as an output terminal when functioning as a shift register is used, both the two data storage elements are operated to 8. An integrated circuit according to claim 1, wherein the data storage circuit functions as a shift register. An integrated circuit according to claim 8, wherein
The data storage circuit serving as the output terminal holds data input from the logic circuit to one data storage element with the input of an execution clock signal used when the logic circuit is functioned. Circuit to
For the data storage circuit having the data storage element serving as the output terminal, the shift register operating circuit receives the input of the one data storage element from the input from the logic circuit as the predetermined test signal is input. An input switching circuit for switching to an input when the plurality of data storage circuits function as a shift register, and an output of the other data storage element from the output to the logic circuit in accordance with the input of the predetermined test signal An output switching circuit for switching to an output when a plurality of data storage circuits function as a shift register, and a clock signal supplied to the one data storage element in response to the input of the predetermined test signal from the execution clock signal Along with the input of the first clock switching circuit for switching to the scan clock signal and the predetermined test signal And a second clock switching circuit that switches a clock signal supplied to the other data storage element from the execution clock signal to a scan clock signal that does not overlap with the scan clock signal switched by the first clock switching circuit. An integrated circuit which is a circuit that causes the data storage circuit serving as the output end to function as a storage circuit at the end of the shift register. An integrated circuit according to claim 8, wherein
The data storage circuit serving as the output terminal receives data input from the logic circuit to one of the data storage elements with the input of an execution clock signal used when the logic circuit functions. Holding circuit,
For the data storage circuit having the data storage element serving as the output terminal, the shift register operating circuit receives the input of the one data storage element from the input from the logic circuit as the predetermined test signal is input. An input switching circuit for switching to an input when the plurality of data storage circuits function as a shift register, and an output of the one data storage element from the output to the logic circuit in accordance with the input of the predetermined test signal An output switching circuit for switching to an input of the other data storage element, and a clock switching for switching a clock signal supplied to the one data storage element in response to the input of the predetermined test signal from the execution clock signal to the scan clock signal Circuit and a scan switched to the other data storage element by the clock switching circuit. Integrated circuit is a circuit to function and the scan clock supply circuit for supplying a scan clock signal do not overlap the clock signal and the data storage circuit to be output end by a circuit having a memory circuit of the end portion of the shift register. An integrated circuit according to any one of claims 8 to 10,
The plurality of data storage circuits are composed of n data storage circuits having two data storage elements,
The shift register operating circuit is a circuit that causes the n data storage circuits to function as an n-bit shift register,
The multi-phase clock supply circuit generates (n + 1) scan clock signals that sequentially rise without overlapping each other, and does not become an output terminal when functioning as a shift register among the n data storage circuits (n -1) A circuit that supplies (n-1) scan clock signals to one memory circuit and supplies two scan clock signals to the data memory circuit serving as the output terminal.   When the shift register operating circuit is a data storage circuit having only one data storage element when the data storage circuit serving as an output terminal when functioning as a shift register, the data storage element of the data storage circuit serving as the output terminal 8. The integrated circuit according to claim 1, wherein the integrated circuit is a circuit that operates a data storage element included in a data storage circuit adjacent to the data storage circuit serving as an output terminal to function the plurality of data storage circuits as a shift register. . An integrated circuit according to claim 12, comprising:
The data storage circuit serving as the output terminal is a circuit that holds data input from the logic circuit to the data storage element with the input of an execution clock signal used when the logic circuit is functioned. And
For the data storage circuit having the data storage element serving as the output terminal, the shift register operating circuit receives the input of the data storage element from the input from the logic circuit in accordance with the input of the predetermined test signal. An input switching circuit for switching to an input when the data storage circuit functions as a shift register, and the output of the data storage element from the output to the logic circuit in accordance with the input of the predetermined test signal An output switching circuit for switching to an output when the circuit functions as a shift register; and a clock signal supplied to the data storage element in response to the input of the predetermined test signal is switched from the execution clock signal to the scan clock signal The data storage circuit serving as the output terminal is shifted by a circuit having a clock switching circuit. Integrated circuit is a circuit to function as a memory circuit of the end of the register. An integrated circuit according to claim 12 or 13, comprising:
The plurality of data storage circuits are composed of n data storage circuits having only one data storage element,
The shift register operating circuit is a circuit that causes the n data storage circuits to function as an (n−1) -bit shift register,
The multiphase clock supply circuit is a circuit that generates n scan clock signals that sequentially rise without overlapping each other and supplies the n scan clock signals to the n data storage circuits.   15. The integrated circuit according to claim 1, wherein the multiphase clock supply circuit is a circuit that supplies a scan clock signal in order from a data storage circuit serving as an output terminal when functioning as a shift register.   An integrated circuit device comprising a plurality of integrated circuits according to claim 1. A test method for an integrated circuit for performing a scan path test on an integrated circuit having a logic circuit and a plurality of data storage circuits capable of storing data from the logic circuit and outputting the stored data to the logic circuit,
A predetermined test signal is input to the integrated circuit, and a plurality of scan clock signals that rise in order without overlapping each other are supplied to the plurality of data storage circuits, and the plurality of data storage circuits are connected to the logic circuit. A method for testing an integrated circuit, wherein the integrated circuit is caused to function as a shift register without input / output of the circuit and a scan path test is performed on the integrated circuit.

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