JP2006101498A - Image scanner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image scanner capable of correcting deviance of a clamp level and a black level by having a function of setting a reference voltage from outside, and a function to switch the reference voltage during reading operation. <P>SOLUTION: The image scanner corrects deviance of the clamp level, and shortens an adjusting time by being composed to have a function to adjust the clamp level and the reference voltage which is a reference of internal operation, using a D/A converter 303. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image reading apparatus, and more particularly to an image reading apparatus that reads image information using a line-shaped CCD image sensor.

  In the reading process with the conventional reduction optical system, the reflected light from the document is read as document information while the traveling body moves in the sub-scanning direction, and this reflected light is imaged on the CCD line sensor via the lens. In the CCD line sensor, an analog electronic signal is converted by photoelectric conversion. The obtained analog electrical signal is subjected to analog processing and digital processing, and image information is read as digital data.

Next, a conventional image reading apparatus will be described with reference to FIG.
FIG. 7 is a block diagram showing a configuration of a conventional image reading apparatus.
A conventional image reading apparatus includes a CCD 10, a line clamp circuit 11, an S / H (sample hold circuit) 12, a variable gain amplifier 13, an A / D converter 14, SW 15, VRT 16, VRB 17, a reference potential 18, and a CCD drive pulse driver 19. , A shading / background removal unit 20, a line memory 21, a gain setting value calculation unit 22, a clamp / S / H / gain control unit 23, and a drive signal generation unit 24.

  First, the line clamp circuit 11 in the analog processing circuit performs a line clamp operation on the output level of the light shield portion or the empty transfer portion in one line of the CCD 10 so as to keep the offset level in one line constant. The clamp level is the black level of the image data.

  Next, the image signal subjected to the line clamp is amplified with a certain gain by the variable gain amplifier 13. The gain is determined so that the target white level is obtained when the reference white original is read. By defining the gain in this way, the input dynamic range of the A / D converter 14 can be used effectively. The image number amplified by the set gain is sampled and held by the sample and hold circuit 12, and converted into a digital signal based on the reference level generated from the reference voltage by the A / D converter 14, and the digital data of the document information Get.

  In the line clamp circuit 11, the capacitor is charged at a preset clamp level during the clamp gate signal assertion period. The charge maintained as the clamp level in the capacitor is the assertion of the clamp level and the clamp gate signal. This is the integral amount of the signal for the period.

  Since a general CCD output includes a reset pulse component, the integration amount including this component is maintained as a clamp level, which is deviated from the CCD black level. In addition, the analog switch 15 inputs a clamp gate signal to perform ON / OFF control of the connection with the clamp level to charge the clamp level, but the capacitor for holding the ON resistance and charge in the analog switch 15 Due to the influence of the leakage current at the substrate, the leakage current on the substrate or the circuit, a deviation occurs between the reference potential and the clamp potential.

  In particular, when the analog processing circuit portion is made into an ASIC, a reference voltage is supplied from the outside, and the internal circuit operates based on the reference voltage, and the deviation between the clamp level and the black output level affects the image data. It will be.

Further, as the prior art of the image reading apparatus, there is the following.
Patent Document 1 describes an image reading apparatus that can shorten the rise time of the apparatus by shortening a substantial time until the clamp voltage is stabilized even in a situation such as returning from the energy saving mode.
Patent Document 2 describes an imaging apparatus that can clamp an output signal of an imaging element for each pixel.
JP 2000-69285 A JP 2000-106654 A

  However, in the clamp processing in the analog processing portion in the conventional image reading apparatus, when the clamp level is generated from the reference voltage and the clamp operation is performed, the operation is performed with the clamp potential integrated with the voltage during the assertion period of the clamp gate signal. . In this case, the reset pulse component of the CCD is also integrated, so that the black level of the CCD and the clamp potential shift. In addition, when the analog processing unit is made ASIC, the internal circuit operates using the reference voltage, and the black level is also caused by the deviation of the clamp level from the internal reference potential even with the ON resistance of the clamp switch and the internal leakage current. And the clamp level will be misaligned.

  The present invention has been made in view of such a problem, and an image capable of correcting a deviation between a clamp level and a black level by having a function of setting a reference voltage from the outside and a function of switching the reference voltage during a reading operation. An object is to provide a reader.

  In order to achieve the above object, an image reading apparatus according to claim 1, wherein a photoelectric conversion element that converts reflected light of a document image into an analog electronic signal by photoelectric conversion, and an analog electric signal output from the photoelectric conversion element are buffered. Analog buffer means for performing analog line clamping operation on analog electric signal, sample hold means for performing sample hold operation on analog electric signal from analog clamping means, and gain of analog electric signal from sample holding means In an image reading apparatus having an analog signal processing unit having a gain adjusting unit for adjusting the A / D conversion, an A / D conversion unit that converts an output from the analog signal processing unit into a digital signal based on a reference voltage, and an A / D conversion Data holding that can hold digital signal output from multiple means for multiple lines To the stage, a digital signal processing means for performing digital signal processing using the digital data held in the data holding means, characterized in that it has a switching means for ON / OFF the output from the analog buffer means.

  According to a second aspect of the present invention, in the image reading apparatus according to the first aspect, the analog buffer means includes an emitter follower circuit.

  The invention according to claim 3 is the image reading apparatus according to claim 1 or 2, further comprising a control signal generating means for generating a control signal for controlling switching supplied to the switching means, wherein the control signal generating means comprises: The control signal is divided into an arbitrary power source and supplied to the switching means.

  The invention according to claim 4 is the image reading apparatus according to claim 1, further comprising a generating unit that generates a reference voltage supplied from the digital data to the analog signal processing unit, and the generating unit is calculated from the digital data. A difference between the black level data and preset target black level data is calculated, and the reference voltage is generated by adjusting the black level data so that the difference falls within a certain range.

  A fifth aspect of the present invention is the image reading apparatus according to the first aspect, wherein the switching means is in a state in which the clamp signal supplied to the analog processing unit is ON when the power of the image reading apparatus is turned on or when energy saving is restored. The first reference voltage is switched to the second reference voltage when the clamp signal is OFF.

  A sixth aspect of the present invention is the image reading apparatus according to any one of the first to fifth aspects, wherein the switching unit includes a clamp period control unit that arbitrarily extends a clamp period of the clamp signal. And

  From the above description, the image reading apparatus according to the present invention is overloaded to the analog processing ASIC when the circuit operation is unstable by providing the function of controlling the output in the analog buffer means arranged in the preceding stage of the analog processing ASIC. It is possible to avoid the input of voltage.

Next, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the configuration of the image reading apparatus of the present invention.
As shown in FIG. 1, a CCD 100 and an emitter follower 101 that are photoelectric conversion elements, an AC coupling unit 102, an emitter follower ON / OFF SW 103, a line clamp 201 that constitutes an analog processing ASIC 200, a sample hold circuit (S & H) 202, SW 203, Variable gain amplifier 204, A / D converter 206, VRT 207, VRB 208, reference potential generation unit 205 for generating a reference potential, image processing unit 301 constituting timing control / image processing ASIC 300, gain setting value 302, DAC 303, clamp / S & H It comprises a control unit 304, a drive signal generation unit 305, and a CCD drive signal driver 400.

  In FIG. 1, an image signal is read as an analog signal by a photoelectric conversion element (CCD) 100, and the obtained analog signal is driven by an analog buffer and supplied to an analog processing ASIC 200 via an AC coupling circuit. In the analog processing ASIC 200, after performing clamp processing and sample hold processing, the variable gain amplifier 204 amplifies the gain by a gain corresponding to a predetermined amplification amount, and the A / D converter 206 performs timing control / image processing. It supplies to process ASIC300.

  In this embodiment, as shown in FIG. 2, the analog buffer unit (analog buffer 11 in FIG. 6) is realized by a two-stage emitter follower circuit 101 using transistors, and the operation of the transistors constituting the emitter follower circuit 101 is realized. An SW 103 for turning on / off the current is provided, and the SW 103 is also realized by a transistor. In the present embodiment, the transistor SW is configured in the first-stage emitter follower circuit portion. Further, a voltage obtained by dividing the base voltage of the transistor constituting the SW by the drive voltage of the emitter follower circuit by a certain resistance ratio is supplied.

Next, the operation of the emitter follower 101 will be described with reference to FIG.
First, when the power supply is turned on, the drive power supply Vcc_e of the emitter follower section rises. At the same time, the voltage (Vbase) obtained by dividing Vcc_e by R1 and R2 also rises. This Vbase is supplied to the base of Tr_SW. Tr_SW does not work until Vbase is 0.7V. For this reason, the operating current is not supplied to the first-stage emitter follower section, and the output of the first-stage emitter follower circuit remains at 0V.

  For this reason, the base current is not supplied to the transistor Tr2 of the second-stage emitter follower circuit, so that the second-stage emitter follower circuit does not operate, and therefore no signal is supplied to the subsequent AC coupling portion.

  Next, when the base-emitter voltage necessary for Vbase to perform the Tr_SW operation becomes 0.7 V, the transistor SW is turned on, and the analog signal output from the first-stage emitter follower circuit is buffered. Output to AC coupling unit. Further, after Tr_SW is turned ON, not only an analog signal component but also a change component until the emitter follower circuit becomes the operating potential is supplied to the AC coupling unit at the same time.

  At this time, the resistors R1 and R2 are set in advance in accordance with the rise times of the analog ASIC drive power source and the emitter follower circuit drive power source in the subsequent stage. R1 and R2 are set so that Vbase reaches 0.7 V after the power supply of the analog processing ASIC in the subsequent stage is turned on (see FIG. 3A).

  By setting in this way, after the analog ASIC in the subsequent stage becomes a normal operation and the input protection circuit or the like is in an operating state, a large power-on at the time of power-on until the respective operating potentials in the emitter follower circuit unit and the CCD are reached. A voltage change is supplied, and it is possible to avoid an excessive voltage being input to the analog processing ASIC and circuit breakdown. As described above, in this embodiment, it is possible to suppress a risk of circuit destruction by adding a circuit composed of Tr_SW and R1 and R2.

As shown in FIG. 3B, when the power is turned off, the sequence operation is reverse to that when the power is turned on.
First, Vbase falls at the same time as Vcc_e falls. When Vbase becomes 0.7 V or less, Tr_SW is turned off, and the operating current is not supplied to the first-stage emitter follower, and the first-stage emitter follower circuit does not operate. For this reason, the supply of the base current to the second-stage emitter follower is also stopped, the second-stage emitter follower does not operate, and no analog signal is supplied to the subsequent AC coupling.

  At this time, the operation battery also changes when the operation of the emitter follower circuit is stopped, and this change is input to the analog processing unit via AC coupling, but at this timing, the driving power of the analog processing ASIC is not turned off. Therefore, it is a normal operation, and it is possible to avoid circuit destruction even if an excessive voltage is input.

  Further, as shown in FIG. 4, the drive power supply in the emitter follower circuit 101 is divided by R1 and R2, and the voltage is supplied as the base potential of Tr_SW, which is used for ON / OFF control of Tr_SW. In such a case, the output from the emitter follower circuit 101 can be controlled at an arbitrary timing by supplying the base potential of Tr_SW from the timing control signal generator.

  In the present embodiment, the clamp level and the internal operation reference voltage are adjusted using a DAC (D / A converter) 203 to correct the clamp level deviation, and Adjustment time can be shortened.

  In addition, by setting the assertion period of the clamp gate signal to be arbitrarily controllable, it is possible to shorten the charge time of the clamp level to the capacitor at the time of starting the system (see FIG. 5).

Next, clamp level adjustment will be described.
The correction of the deviation in the clamp operation is performed by adjusting the reference voltage setting value during the period when the clamp gate signal is negated and calculating the reference setting value 2 for absorbing the deviation, and in the normal reading operation During the time when the clamp gate signal is asserted, the capacitor is charged with the reference voltage 1 based on the reference setting value 1 to perform the clamping operation. In the clamp gate negation period, the analog processing circuit portion is switched to the reference voltage 2 based on the reference setting value 2. By operating at the reference voltage 2, the difference between the clamp level and the black output level generated by the clamp operation is absorbed.

  At the stage of starting up the system such as when the power is turned on or when energy saving is restored, a capacitor in the clamp circuit portion is first charged with a clamp potential set at a reference set value 1. In the present invention, the AC coupling capacitor is charged with the reference potential. At this time, when the lamp is turned off, the output level is the same as that of the light shield part even during the effective output period of the CCD. As a result, it is possible to shorten the time until the battery is charged to a certain level.

  As the reference set value 1, the center set value of the adjustment range is set. After charging the capacitor to the reference voltage 1 set with the reference set value 1, processing for obtaining the reference set value 2 for absorbing the correction for the deviation in the clamping operation is performed.

  The reference set value 2 is obtained by updating several times so that the difference between the digital data read as the black level and the target black level is within a certain range. The potential of the period during which the clamp signal is negated is set while updating the reference set value 2. However, while the clamp signal is negated, the line clamps 201 and SW 203 shown in FIG. Since the capacitor having a capacity for holding the clamp level is not connected, the charging time until the reference voltage 2 is refined by the DAC during the update process of the reference setting value 2 can be ignored. It is possible to significantly reduce the time for updating the value 2. Further, the switching operation during normal reading can be realized without considering the charging time.

  Before the update process of the reference set value 2, first, the assertion period of the clamp gate is returned to the assertion period in the normal reading operation (see FIG. 5). In this state, the value of the light shield part of the CCD output is read as a black level, and update processing is performed so that the read value becomes the target black level.

Clamp level setting value 2 [n + 1]
= Clamp level setting value 2 [n] + α × (black target level−reading level)
α: Clamp level set value 2 Update coefficient Clamp level set value 2 [n]: Generates reference voltage 2 for the clamp gate negate period
Setting value for D / A converter

  Further, the black level at the time of processing by the above formula is calculated from the data held in the line memory in the ASIC shown in FIG. In order to reduce the influence of noise, the black level is calculated by performing averaging processing from the black level read data of a plurality of pixels. For the target pixel, pixels corresponding to the light shield portion in one line are averaged for several lines (the portion indicated by the black level acquisition period in FIGS. 5 and 6).

By using the reference set value 2 calculated in this way and setting it during the negation period of the clamp gate signal during normal reading, it is possible to correct the deviation in the clamp operation.
Further, in the present invention, the time for calculating the reference set value 2 can be shortened, and a faster system start-up time can be realized.

Furthermore, the updating process of the reference voltage setting value 2 is not performed only at the time of starting the system, but the black reading level of the CCD light shield part is monitored even during normal reading operation, and the reference voltage setting value 2 is constantly updated. In addition, by setting the D / A converter, it is possible to absorb not only the displacement of the clamping operation but also the temperature variation and the temporal variation.
From the above description, the analog buffer 11 is realized by a two-stage emitter follower circuit without using a circuit such as a high-speed operational amplifier having a complicated configuration, so that it can be realized at a low cost and with a simple circuit configuration. Make it possible.

  Further, by realizing the means for controlling the output of the analog buffer 11 from a transistor and two resistors without preparing a dedicated control IC outside, it can be realized at a low cost and with a simple circuit configuration. Become.

  In addition, the signal for controlling the output of the analog buffer 11 is divided and supplied to the drive power of the analog buffer 11 without adding a dedicated control IC to the outside, so that the low cost and simple circuit configuration can be realized. It is possible to do.

  Further, in a system having a more complicated power-up sequence, a signal for controlling the output of the analog buffer 11 is supplied from the timing control signal generator 305, and the output from the analog buffer 11 is turned ON / OFF at an arbitrary timing. By controlling, it is possible to avoid an excessive voltage being input to the analog processing ASIC when the circuit operation of the analog processing ASIC 200 is unstable.

1 is a block diagram illustrating a configuration of an image reading apparatus according to an embodiment. It is the circuit diagram which showed the structure of the emitter follower shown in FIG. It is a graph which shows the operation state of the emitter follower shown in FIG. It is the block diagram which showed the structure of the image reading apparatus which showed the structure which can control the output from an emitter follower at arbitrary timings. It is a time chart which shows the clamp operation | movement in this embodiment. It is a time chart which shows the clamp operation | movement in this embodiment. It is a block diagram showing a configuration of a conventional image reading apparatus.

Explanation of symbols

100 CCD
101 Emitter follower 102 AC coupling unit 103 Emitter follower ON / OFF SW
200 Analog processing ASIC
201 Line clamp 202 S & H (sample hold circuit)
203 SW
204 Variable gain amplifier 205 Reference potential generator 206 A / D converter 207 VRT
208 VRB
300 Timing Control / Image Processing ASIC
301 Image Processing Unit 302 Gain Setting Value 303 DAC
304 Clamp / S & H Control Unit 305 Drive Signal Generation Unit 400 CCD Drive Signal Drive

Claims (6)

A photoelectric conversion element that converts reflected light of a document image into an analog electronic signal by photoelectric conversion;
Analog buffer means for buffering an analog electrical signal output from the photoelectric conversion element;
Analog clamp means for performing line clamp operation on analog electrical signals;
Sample hold means for performing a sample hold operation on the analog electrical signal from the analog clamp means;
In an image reading apparatus comprising an analog signal processing unit having a gain adjusting means for adjusting a gain of the analog electric signal from the sample hold means,
A / D conversion means for converting the output from the analog signal processing unit into a digital signal based on a reference voltage;
Data holding means capable of holding a digital signal output from the A / D conversion means for a plurality of lines;
Digital signal processing means for performing digital signal processing using digital data held in the data holding means;
An image reading apparatus comprising switching means for turning ON / OFF the output from the analog buffer means.   2. The image reading apparatus according to claim 1, wherein the analog buffer means is composed of an emitter follower circuit. Control signal generating means for generating a control signal for controlling the switching supplied to the switching means,
The image reading apparatus according to claim 1, wherein the control signal generation unit divides an arbitrary power source and supplies the control signal to the switching unit. Generating means for generating a reference voltage supplied from the digital data to the analog signal processing unit;
The generating means calculates a difference between black level data calculated from the digital data and preset target black level data, and adjusts the black level data so that the difference falls within a certain range. The image reading apparatus according to claim 1, wherein a voltage is generated.   The switching means uses a first reference voltage when the clamp signal supplied to the analog processing unit is ON when the image reading apparatus is turned on or when energy saving is restored, and a second reference voltage when the clamp signal is OFF. The image reading apparatus according to claim 1, wherein the image reading apparatus is switched to the reference voltage.   The image reading apparatus according to claim 1, wherein the switching unit includes a clamp period control unit that arbitrarily extends a clamp period of the clamp signal.

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