JP2006101429A - In-byte plural spotty byte error correction/detection method and its device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an in-byte plural spotty byte error correction/detection device equipped with a function for controlling a multiple in-byte plural spotty byte error. <P>SOLUTION: There is provided the in-byte plural spotty byte error correction/detection device equipped with an encoding means for producing transmission words based on input information data and a decoding means for entering, as reception words, the transmission words in which an error has been generated in an information transmission channel to correct or detect the error. In the in-byte plural spotty byte error correction/detection device, the encoding means produces the transmission words by adding check information produced based on a parity check matrix for expressing spotty byte error control signs and the input information data to the input data. The decoding means is equipped with a syndrome producing means for producing the syndrome of the reception words based on the parity check matrix and an error correcting means for correcting or detecting the error of the reception words based on the syndrome produced by the syndrome producing means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  More particularly, the present invention relates to a spotty byte error correction / detection method and apparatus, and more specifically, a plurality of bits in a byte as a plurality of bits. The present invention relates to an intra-byte multiple spotty byte error correction / detection method and apparatus suitable for use in detecting or correcting an error when a spotty byte error occurs.

  In recent years, improvement in the reliability of digital data has become increasingly important due to the progress of the information society and the progress of semiconductor technology. When attempting to transmit or record digital data accurately, transmission data is erroneously transmitted in the transmission path due to the influence of noise, etc., or errors caused by element failures or recording medium defects are detected. Need to detect and correct. In order to realize this error detection / correction, various error correction / detection codes based on code theory have been developed.

As a conventional error correction code, for example, a block of b bits (b is an integer of 2 or more) is referred to as a byte, and it is excellent as a code that corrects an arbitrary error in one byte (referred to as an S _b EC code). -Patel code is disclosed (for example, see Non-Patent Document 1).

  Further, in a high-speed semiconductor memory system, an odd weight sequence byte error correction code having characteristics including a 1-bit error correction code and a 2-bit error detection code most frequently used in the past has been disclosed (for example, Non-Patent Document 2). reference).

Furthermore, a code for correcting a 1-byte error and detecting a 2-byte error (referred to as an S _b EC-D _b ED code) is a Reed-Solomon code (Reed-Solomon code) and its improved efficient code It has been proposed and already adopted in main storage devices such as many computer systems (for example, see Non-Patent Document 3 and Non-Patent Document 4).

As a code for detecting a byte error, a code that corrects a 1-bit error and detects a 2-bit error and also detects a 1-byte error (referred to as a SEC-DED-S _b ED code) has been announced. Currently, it is widely applied to a main storage device of a computer system (for example, see Non-Patent Document 5).

  In addition, specific contents regarding many code researches and developments related to each other up to the latter half of the 1980s are described comprehensively in Non-Patent Document 6.

Subsequently, as a newly developed code for high-speed semiconductor memory, a code for correcting a 1-byte error and detecting a 2-bit error (referred to as S _b EC-DED code) is described in Non-Patent Document 7 below, Non-Patent Document 8 proposes a code that corrects a 1-byte error and detects a simultaneous error of a 1-bit error and a 1-byte error (referred to as S _b EC− (S + S _b ) EC code). Further, Non-Patent Document 9 discloses a code (referred to as S _b EC-DEC code) that corrects a 1-byte error and corrects a 2-bit error if there is a 2-bit error.

In particular, as a code most relevant to the present invention, specifically, an error up to t bits (t ≦ b) in a byte consisting of b bits is referred to as a t / b error or a spotty byte error. An invention relating to a St _{/ b} EC code for correcting a byte error and a St _{/ b} EC- _Sb ED code for correcting a spotty byte error and detecting a one-byte error exceeding t bits in a byte has already been disclosed (See Patent Document 1). In particular, the _{St / b} EC code is disclosed in Non-Patent Document 10.

Further, 1 spotty-byte error and correct the and _{S t / b EC-D t} / b ED code is detected two spotty byte error, and correcting single spotty byte error, and a 2 spotty-byte error An invention has already been filed for an S _{t / b} EC-D _{t / b} ED-S _b ED code for detecting and detecting a one-byte error exceeding t bits in a byte (see Patent Document 2).

Furthermore, an invention regarding a method for constructing a general spotty byte error control code for the distance d has already been filed (see Patent Document 3).
JP 2004-7217 A Japanese Patent Application No. 2003-416978 Japanese Patent Application No. 2004-239392 JP 2002-374175 A SJHong / AMPatel, “A general Class of Maximal Codes for Computer Applications”, IEEE Transactions on Computers Computers), C-21, No. 12, p.1322-1331, 1972 E. Fujiwara, “Odd-Weight-Columnb-Adjacent Error Correcting Codes”, Transactions of the IECE Japan, No. Volume E61, No. 10, p. 781-787, 1978 S. Kaneda and E. Fujiwara, “Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems” IEEE Transactions on Computers, Vol. C-31, No. 7, p. 596-602, July 1982 CLC and LEGrosbach, “Fault-Tolerant Memory Design in the IBM Application System / 400TM”, Proceedings Off Annual International Symposium on Proceedings of Annual International Symposium on Fault-Tolerant Computing, p.393-400, June 1991 S. Kaneda, “A class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications”, IEEE IEEE Transactions on Computers, Vol. C-33, No. 8, p. 737-739, August 1984 Co-authored by TRNRao and Eiji Fujiwara, “Error Control Coding for Computer Systems”, Prentice-Hall, 1989 Co-authored by E. Fujiwara and M. Hamada, “Single b-Bit ByteError Correcting and Double Bit Error Detecting Codes for Memory Systems ”, IEICE Transactions on Fundamentals, Volume E76-A, No. 9, pp. 1442-1448, September 1993 "A Class of Error Control Codes for Byte Organized Memory" Co-authored by M. Hamada and E. Fujiwara, "A Class of Error Control Codes for Byte Organized Memory Systems Systems-SbEC- (Sb + S) ED Codes- "", IEEE Transactions on Computers, Vol. 46, No. 1, p.105-109, January 1997 Co-authored by G. Umanesan and E. Fujiwara, “Random Double Bit Error Correcting – Single Byte Error Correcting – Single Byte Error Correcting (DEC-SbEC) Codes for MemorySystems ””, IEICE Transactions on Fundamentals, Vol. E85-A, No. 1, p.273-276, January 2002 Co-authored by G. Umanesan and E. Fujiwara, “A Class of Codes for Correcting Single Spotty Byte Errors”, IEICE Transactions on Fundamentals (IEICE Transactions on Fundamentals), Volume E86-A, No. 3, p.704-714, March 2003 SBWicker and VKBhargava, “Reed-Solomon Codes and Their Applications”, IEEE Press, 1994 SJPiestrak, “The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks”, IEEE Transactions on Computer (IEEE Transactions on Computers), Vol. 42, No. 6, p. 700-712, June 1993

Until the middle of the 1980s, semiconductor memory devices mainly used devices having 1-bit input / output of data, so 1-bit error correction for correcting errors of up to 2 devices and detecting errors up to 2 devices. Many bit error detection codes (referred to as SEC-DED codes) have been used. However, since the middle of the 1980s, in response to the need for high integration of memory devices, devices having 4-bit data input / output have become mainstream, and the aforementioned S ₄ EC-D ₄ ED code having a byte width b = 4 bits. And SEC-DED-S ₄ ED codes are mainly used. Furthermore, since the mid-1990s, semiconductor memory devices having 8-bit and 16-bit input / output data have become mainstream.

However, when b = 8 or b = 16 is applied to the byte width b of the conventional S _b EC-D _b ED code, the ratio of the number of check bits to the total code length is as large as about 30% to 40%. As a result, the coding rate is lowered, which is a very large problem practically.

  By the way, in a memory device using these semiconductor memory elements (DRAM elements), a temporary failure may occur due to noise, alpha particles, or the like, or a fixed failure may occur in which the DRAM element itself deteriorates and does not operate. More than 80% of recent devices using DRAM devices are said to have a temporary failure. Especially in DRAM devices having multi-bit data input / output of 8 bits or more, about 1, 2, 3 bits in a byte. A relatively small number of bit errors are assumed to be the majority.

  Among them, there are the most frequent one-bit errors caused by electromagnetic noise and alpha particles having relatively low energy levels, and fixed failure of the memory cell, and recently, mobile devices equipped with the DRAM element are frequently used. Therefore, it is necessary to consider use in a poor electromagnetic environment. In addition, in DRAM devices in electronic equipment used in aircraft and military aircraft flying at high altitudes, temporary failures that have errors of about 2 bits or 3 bits due to collisions of neutron particles with high energy levels caused by cosmic rays Is likely to occur. Furthermore, it is necessary to consider that a DRAM element mounted on a space device used in satellite communication or space communication is greatly damaged by collision with particles having a high energy level. In this case, an error of 2 bits or more is required. It is known that must be considered.

Considering the fact that bit error occurrence conditions as described above are diverse, the St _{/ b} EC- _Sb ED code, which can be configured by giving arbitrary values to the parameters t and b, is a DRAM device having 8 bits or more. This is a very practical encoding method when used in a memory device using the. In other words, the _{St / b} EC- _Sb ED code is t bits smaller than the byte width b (the value of t can be arbitrarily determined by the designer by investigating the tendency of errors). By providing a function capable of correcting an error (spotty byte error) of one element and a function capable of detecting a one-byte error exceeding t bits although the probability of occurrence is small, a conventional byte unit The error can be corrected and detected with a significantly smaller number of check bits than the error control code such as the Reed-Solomon code performed in FIG.

In addition, for an error over any two elements (not limited to two adjacent elements), the St _{/ b} EC-D _{t / b} ED- _Sb ED code uses a DRAM element of 8 bits or more. This is a very practical encoding method when used in a memory device. In other words, the _{St / b} EC-D _{t / b} ED- _Sb ED code is capable of correcting one element error up to t bits smaller than the byte width b (one spotty byte error correction, S _{t / b} EC) A function capable of detecting a spotty byte error across two elements (two spotty byte error detection, D _{t / b} ED), and a probability of occurrence which is small but exceeding t bits This is a code with a function that can detect byte errors (1-byte error detection, S _b ED). Bit errors can be reduced with a significantly smaller number of check bits compared to the conventional coding method in byte units. It can be corrected and detected.

Furthermore, for errors extending over two or more elements, in theory, it is possible to correct and detect errors by constructing a spotty byte error control code having a distance d on GF (2 ^b ). It has become.

However, the spotty byte error control code having a distance d on GF (2 ^b ) has a problem that an error exceeding t bits in one byte cannot be corrected / detected (S _b ED function or the like). Was. Therefore, development of a code having a function of correcting and detecting even when an error exceeding t bits in one byte, that is, a plurality of spotty byte errors, has been demanded.

In addition, the _{St / b} EC-D _{t / b} ED code has the problem that the t value is the same for both correction and detection, and a different t value cannot be given to the correction and detection.

Here, as in the spotty byte error control code having a distance d on GF (2 ^b ), an error in which only one spotty byte error occurs in one byte is referred to as “single spotty byte error in byte”. In contrast, an error in which a plurality of spotty byte errors (that is, two or more spotty byte errors) occur in one byte is referred to as “a plurality of spotty byte errors in a byte”.

  The present invention has been made in view of the circumstances as described above, and an object of the present invention is to provide a multiple spotty byte error within a byte having a function capable of controlling multiple spotty byte errors within multiple bytes. It is to provide a correction / detection method and apparatus.

  Another object of the present invention is to provide an intra-byte multiple spotty byte error correction / detection method having a function capable of controlling two types of spotty byte errors of different sizes generated in one byte, and To provide an apparatus.

を有することにより、或いは、前記ｔ値、ｂ値、ｄ値を任意に設定することにより、或いは、前記情報伝送路は、情報通信システムであることにより、或いは、前記情報伝送路は、メモリシステムであることにより、或いは、前記情報伝送路は、バス線回路であることによって効果的に達成される。 The present invention comprises: encoding means for generating a transmission word based on input information data; and decoding means for correcting or detecting the error by inputting the transmission word in which an error has occurred in an information transmission path as a reception word. The above-mentioned object of the present invention relates to an intra-byte multiple spotty byte error correction / detection device, wherein the encoding means is generated based on a parity check matrix representing a spotty byte error control code and the input information data The check information is added to the input information data to generate the transmission word, and the decoding means generates a syndrome of the received word based on the parity check matrix, and the syndrome generation means Error correction means for correcting or detecting an error in the received word based on the syndrome generated by When the report data is composed of a plurality of bytes, where b (b is an integer of 2 or more) bits is one byte, errors up to t bits (1 ≦ t ≦ b) in the bytes are spotted. The spotty byte error control code expressed by the parity check matrix is called a byte error, assuming that an error in which a plurality of spotty byte errors occur in one byte is referred to as an intra-byte multiple spotty byte error. , For distance d

Or by arbitrarily setting the t value, b value, and d value, or the information transmission path is an information communication system, or the information transmission path is a memory system. Alternatively, the information transmission path is effectively achieved by a bus line circuit.

ただし、Ｒ＝ｑ＋（ｄ−２）ｒ、Ｎ＝ｂｎ、０≦ｉ≦ｎ−１、ｎ＝２^ｒ−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、（ｄ−１）ｔまたはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（（ｄ−１）ｔ、ｂ）を満足し、前記行列Ｈ’のランクがｂに等しいとき、前記行列Ｈ’はランクｂのｂ×ｂ行列であり、前記行列Ｈ’のランクが（ｄ−１）ｔ＜ｂのとき、前記行列Ｈ’は最小ハミング距離（ｄ−１）ｔ＋１を有する符号の検査行列、すなわち、（ｄ−１）ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しくなり、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、

またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、

を満足し、ここで、

はｘを超えない最小の整数を表し、また、前記行列Ｈ”のランクがｂに等しいとき、前記行列Ｈ”はランクｂのｂ×ｂ行列であり、前記行列Ｈ”のランクが

のとき、前記行列Ｈ”は最小ハミング距離

を有する符号の検査行列、すなわち、

ビット誤り検出機能を有する（ｂ、ｂ−ｒ）符号のパリティ検査行列に等しくなり、γは２を底とするｒ次の拡大体ＧＦ（２^ｒ）の原始元であって、γ^ｉＨ”＝［γ^ｉｈ_０”、γ^ｉｈ_１”、…、γ^ｉｈ_ｂ−１”］が成立するように構成されることによって効果的に達成される。 Also, the above-mentioned object of the present invention is that the parity check matrix is a next matrix H having R rows and N columns used for an intra-byte multiple spotty byte error control code having the distance d.

However, R = q + (d−2) r, N = bn, 0 ≦ i ≦ n−1, n = 2 ^r −1, and the matrix H ′ has H ′ = [h ₀ ′, h ₁ ′, .., H _b-1 ′], a q-th column vector h _j ′ (0 ≦ j ≦ b−1) and a q × b binary matrix (q ≦ b), d-1) has a rank equal to or larger than either t or b, i.e. Rank (H ′) ≧ Min ((d−1) t, b), and the matrix When the rank of H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and when the rank of the matrix H ′ is (d−1) t <b, the matrix H ′ is the minimum Hamming A parity check matrix of a code having a distance (d-1) t + 1, that is, a parity check matrix of a (d-1, b) code having a (d-1) t-bit error detection function, and Matrix H _"is, H" = consists _{[h 0 ", h 1"} , ···, h b-1 "] are shown r next column vector _{h j" (0 ≦ j ≦} b-1) a binary matrix of r rows and b columns (r ≦ b),

Or has a rank equal to or greater than the smaller value of b, ie,

Satisfied here,

Represents the smallest integer not exceeding x, and when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

Is equal to a parity check matrix of a (b, b−r) code having a bit error detection function, and γ is a primitive element of an r-order extension field GF (2 ^r ) with 2 as a base, and γ ⁱ H ″ = [Γ ⁱ h ₀ ″, γ ⁱ h ₁ ″,..., Γ ⁱ h _b−1 ″] is effectively achieved.

ただし、Ｒ≧ｑ＋（ｄ−２）ｒ、かつ（Ｒ−ｑ）は（ｄ−２）の倍数であり、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／（ｄ−２）、０≦ｉ≦ｎ−１、（Ｒ−ｑ）は（ｄ−２）の倍数とし、ｎ＝２^{（Ｒ−ｑ）／（ｄ−２）}−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、（ｄ−１）ｔまたはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（（ｄ−１）ｔ、ｂ）を満足し、前記行列Ｈ’のランクがｂに等しいとき、前記行列Ｈ’はランクｂのｂ×ｂ行列であり、前記行列Ｈ’のランクが（ｄ−１）ｔ＜ｂのとき、前記行列Ｈ’は最小ハミング距離（ｄ−１）ｔ＋１を有する符号の検査行列、すなわち、（ｄ−１）ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しくなり、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、

またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、

を満足し、前記行列Ｈ”のランクがｂに等しいとき、前記行列Ｈ”はランクｂのｂ×ｂ行列であり、前記行列Ｈ”のランクが

のとき、前記行列Ｈ”は最小ハミング距離

を有する符号の検査行列、すなわち、

ビット誤り検出機能を有する（ｂ、ｂ−ｒ）符号のパリティ検査行列に等しくなり、Ｒ≧ｑ＋（ｄ−２）ｒ、かつＲ−ｑはｄ−２の倍数とし、γは２を底とする（Ｒ−ｑ）／（ｄ−２）次の拡大体ＧＦ（２^{（Ｒ−ｑ）／（ｄ−２）}）の原始元であって、γ^ｉＨ”＝［γ^ｉΦ（ｈ_０”
）、γ^ｉΦ（ｈ_１” ）、・・・、γ^ｉΦ（ｈ_ｂ−１”
）］が成立するように構成され、ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／（ｄ−２）}）への準同型写像（homomorphism）であり、すなわち、Φ：ＧＦ（２^ｑ）→ＧＦ（２^{（Ｒ−ｑ）／（ｄ−２）}）であることによって効果的に達成される。 Also, the above-mentioned object of the present invention is that the parity check matrix is a next matrix H having R rows and N columns, which is used for an extended byte multiple spotty byte error control code having the distance d.

However, R ≧ q + (d−2) r and (R−q) is a multiple of (d−2), N = b (n + 1) + (R−q) / (d−2), 0 ≦ i ≦ n−1, (Rq) is a multiple of (d−2), n = 2 ^{(Rq) / (d−2)} −1, and the matrix H ′ is H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′] of q-th column vector h _j ′ (0 ≦ j ≦ b−1) of q rows and b columns (q ≦ b) It is a binary matrix and has a rank (Rank) that is equal to or greater than (d-1) t or b, i.e., Rank, that is, Rank (H ′) ≧ Min ((d−1) t, b ) And the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and the rank of the matrix H ′ is (d−1) t <b. The matrix H ′ is the minimum Hamming distance (d−1) t + 1. Check matrix of a code having, i.e., (d-1) is equal to t bits having an error detection function (b, b-q) code of the parity check matrix, also the matrix H "is, H" = _[h 0 " , H ₁ ″,..., H _b−1 ″], r-row b column (r ≦ b) binary composed of r-th column vector h _j ″ (0 ≦ j ≦ b−1) Matrix

Or has a rank equal to or greater than the smaller value of b, ie,

And the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

It is equal to the parity check matrix of a (b, b−r) code having a bit error detection function, R ≧ q + (d−2) r, Rq is a multiple of d−2, and γ is 2 ( ^{Rq) / (d-2} ) is a primitive element of the next extension field GF (2 ^{(Rq) / (d-2)} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ”
), Γ ⁱ Φ (h ₁ ″),..., Γ ⁱ Φ (h _b-1 ″)
)], Where Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(Rq) / (d-2)} ) under addition Yes, that is, effectively achieved by Φ: GF (2 ^q ) → GF (2 ^{(R−q) / (d−2)} ).

ただし、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、また、Ｎ＝ｂ（ｎ＋１）＋Ｒ−ｑ、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／２}−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、２ｔ＋ｔ’またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（２ｔ＋ｔ’、ｂ）を満足し、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、ｔまたはｔ’のうちいずれか大きい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ”）≧Ｍａｘ（ｔ、ｔ’）を満足し、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、γは２を底とする（Ｒ−ｑ）／２次の拡大体ＧＦ（２^{（Ｒ−ｑ）／２}）の原始元であって、γ^ｉＨ”＝［γ^ｉΦ（ｈ_０”）、γ^ｉΦ（ｈ_１”）、・・・、γ^ｉΦ（ｈ_ｂ−１”）］が成立するように構成され、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）であることにより、或いは、前記スポッティバイト誤り制御符号は、１個のｔ／ｂ誤りを訂正し、且つ、２個のｔ’／ｂ誤りを検出する機能を有するＳ_ｔ／ｂＥＣ−Ｄ_ｔ’／ｂＥＤ符号であり、前記Ｓ_ｔ／ｂＥＣ−Ｄ_ｔ’／ｂＥＤ符号に用いる前記パリティ検査行列は、Ｒ行Ｎ列を有する次の行列Ｈであり、

ただし、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、また、Ｎ＝ｂ（ｎ＋１）＋Ｒ−ｑ、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／２}−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、２ｔまたはｔ＋２ｔ’のうちいずれか大きい値、及びｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（Ｍａｘ（２ｔ、ｔ＋２ｔ’）、ｂ）を満足し、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、ｔまたはｔ’のうちいずれか大きい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ”）≧Ｍａｘ（ｔ、ｔ’）を満足し、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、γは２を底とする（Ｒ−ｑ）／２次の拡大体ＧＦ（２^{（Ｒ−ｑ）／２}）の原始元であって、γ^ｉＨ”＝［γ^ｉΦ（ｈ_０”）、γ^ｉΦ（ｈ_１”）、・・・、γ^ｉΦ（ｈ_ｂ−１”）］が成立するように構成され、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）であることにより、或いは、前記スポッティバイト誤り制御符号は、（ｔ／ｂ＋ｔ’／ｂ）誤りを訂正する機能を有する（Ｓ_ｔ／ｂ＋Ｓ_ｔ’／ｂ）ＥＣ符号であり、前記（Ｓ_ｔ／ｂ＋Ｓ_ｔ’／ｂ）ＥＣ符号に用いる前記パリティ検査行列は、Ｒ行Ｎ列を有する次の行列Ｈであり、

ただし、Ｒ≧ｑ＋３ｒ、且つ、（Ｒ−ｑ）は３の倍数であり、また、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／３、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／３}−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、２ｔ＋２ｔ’またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（２ｔ＋２ｔ’、ｂ）を満足し、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、ｔ＋ｔ’またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ”）≧Ｍｉｎ（ｔ＋ｔ’、ｂ）を満足し、Ｒ≧ｑ＋３ｒ、かつ（Ｒ−ｑ）は３の倍数であり、γは２を底とする（Ｒ−ｑ）／３次の拡大体ＧＦ（２^{（Ｒ−ｑ）／３}）の原始元であって、γ^ｉＨ”＝［γ^ｉΦ（ｈ_０”）、γ^ｉΦ（ｈ_１”）、・・・、γ^ｉΦ（ｈ_ｂ−１”）］が成立するように構成され、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）であることにより、或いは、前記スポッティバイト誤り制御符号は、２個のｔ／ｂ誤りを訂正し、且つ、１個のｔ’／ｂ誤り（ｔ＜ｔ’）を訂正する機能を有するＤ_ｔ／ｂＥＣ−Ｓ_ｔ’／ｂＥＣ符号であり、前記Ｄ_ｔ／ｂＥＣ−Ｓ_ｔ’／ｂＥＣ符号に用いる前記パリティ検査行列は、Ｒ行Ｎ列を有する次の行列Ｈであり、

ただし、Ｒ≧ｑ＋３ｒ、且つ、（Ｒ−ｑ）は３の倍数であり、また、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／３、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／３}−１であり、行列Ｈ’は、Ｈ’＝［ｈ_０’、ｈ_１’、・・・、ｈ_ｂ−１’］に示すｑ次の列ベクトルｈ_ｊ’（０≦ｊ≦ｂ−１）から構成されるｑ行ｂ列（ｑ≦ｂ）の２元行列であり、４ｔまたは２ｔ’のうちいずれか大きい値、及びｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ’）≧Ｍｉｎ（Ｍａｘ（４ｔ、２ｔ’）、ｂ）を満足し、また、行列Ｈ”は、Ｈ”＝［ｈ_０”、ｈ_１”、・・・、ｈ_ｂ−１”］に示すｒ次の列ベクトルｈ_ｊ”（０≦ｊ≦ｂ−１）から構成されるｒ行ｂ列（ｒ≦ｂ）の２元行列であり、２ｔまたはｔ’のうちいずれか大きい値、及びｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有し、すなわち、Ｒａｎｋ（Ｈ”）≧Ｍｉｎ（Ｍａｘ（２ｔ、ｔ’）、ｂ）を満足し、Ｒ≧ｑ＋３ｒ、かつ（Ｒ−ｑ）は３の倍数であり、γは２を底とする（Ｒ−ｑ）／３次の拡大体ＧＦ（２^{（Ｒ−ｑ）／３}）の原始元であって、γ^ｉＨ”＝［γ^ｉΦ（ｈ_０”）、γ^ｉΦ（ｈ_１”）、・・・、γ^ｉΦ（ｈ_ｂ−１”）］が成立するように構成され、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）であることによって効果的に達成される。 The above-mentioned object of the present invention is such that, when the input information data is composed of a plurality of bytes, where b (b is an integer of 2 or more) bits, and up to t bits in the bytes. It is assumed that an error is called a t / b error and an error up to t ′ bits in a byte is called a t ′ / b error, provided that 1 ≦ t, t ′ ≦ b, and t ≠ t ′. The spotty byte error control code represented by the parity check matrix includes two types of spotty byte errors having different sizes generated in one byte (that is, the t / b error and the t ′ / b error). ) Or the spotty byte error control code corrects one t / b error and (t / b + t ′ / b) error (ie, t / b error). And S 'having a function of detecting a composite error of t' / b errors) _{t / b} EC− (S _{t / b} + S _{t ′ / b} ) ED code, and the parity check matrix used for the St _{/ b} EC− (S _{t / b} + S _{t ′ / b} ) ED code is R The following matrix H with rows and N columns,

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b) and has a rank equal to or smaller than 2t + t ′ or b, ie, Rank (H ′) ≧ Min (2t + t ′, b) is satisfied, and the matrix H ″ has an r-th column vector h _j ″ represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. It is a binary matrix of r rows and b columns (r ≦ b) composed of (0 ≦ j ≦ b−1), and has a rank equal to or greater than t or t ′, whichever is greater ,sand That is, Rank (H ″) ≧ Max (t, t ′) is satisfied, R ≧ q + 2r, (Rq) is a multiple of 2, and γ is 2 (Rq) / Primordial element of the secondary extension GF (2 ^{(Rq) / 2} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),... , Γ ⁱ Φ (h _b-1 ″)] holds, and Φ is a homomorphic mapping from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) under addition ( by a homomorphism), or the spotty byte error control code, correct one t / b error, and, S _{t / b} EC having a function of detecting two t '/ b error -D _{t '/ b} ED code, and the parity check matrix used for the _{St / b} EC-D _{t' / b} ED code is the following matrix H having R rows and N columns;

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b), and has a rank that is equal to or greater than the larger value of 2t or t + 2t ′ and the smaller value of b That is, Rank (H ′) ≧ Min (Max (2t, t + 2t ′), b) is satisfied, and the matrix H ″ is H ″ = [h ₀ ″, h ₁ ″,..., H _{b −1} ″] is a binary matrix of r rows and b columns (r ≦ b) composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1), and either t or t ′ Or big Has a rank (Rank) that is equal to or greater than the value, ie, satisfies Rank (H ″) ≧ Max (t, t ′), R ≧ q + 2r, and (R−q) is a multiple of 2, and γ Is the primitive element of the base 2 (Rq) / 2 quadratic extension GF (2 ^{(Rq) / 2} ), where γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b-1 ″)] is established, and Φ is additively converted from GF (2 ^q ) to GF (2 ^(R by a ^{-q) / 2)} homomorphism to (homomorphism), or the spotty byte error control code has a function of correcting (t / b + t '/ b) error _{(S t / b} in + S _{t '/} b) is EC code, the _{(S t / b + S t} ' / b) the parity check matrix used in the EC code, the following matrix with R rows and N columns H Ri,

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1), a q × b binary matrix having a rank equal to or greater than 2t + 2t ′ or b, i.e., Rank, Rank (H ′) ≧ Min (2t + 2t ′, b) is satisfied, and the matrix H ″ is an r-th order represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. Is a binary matrix of r rows and b columns (r ≦ b) made up of column vectors h _j ″ (0 ≦ j ≦ b−1), and rank equal to or greater than t + t ′ or b. (Ra nk), that is, Rank (H ″) ≧ Min (t + t ′, b) is satisfied, R ≧ q + 3r, and (R−q) is a multiple of 3, and γ is based on 2 ( Rq) / 3 primitive field GF (2 ^{(Rq) / 3} ) primitive element, and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″ _{^{), ···, γ i Φ (}} h b-1 ")] it is configured to establish, [Phi from under additive ^{GF (2 q) GF (2} (R-q) / 2) to Or the spotty byte error control code corrects two t / b errors and one t ′ / b error (t <t ′). D _{t / b} EC-S _{t ′ / b} EC code having a function of correcting the error, and the parity check matrix used for the D _{t / b} EC-S _{t ′ / b} EC code has R rows and N columns. Next It is a matrix H,

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1) is a binary matrix of q rows and b columns (q ≦ b), and rank equal to or greater than the larger value of 4t or 2t ′ and the smaller value of b (Rank), that is, Rank (H ′) ≧ Min (Max (4t, 2t ′), b) is satisfied, and the matrix H ″ has H ″ = [h ₀ ″, h ₁ ″, .., H _b-1 ″] is an r-th column vector h _j ″ (0 ≦ j ≦ b−1) and is a binary matrix of r rows and b columns (r ≦ b), 2t Or t ', whichever is greater It has a rank (Rank) that is equal to or greater than the threshold value and whichever is smaller of b, that is, Rank (H ″) ≧ Min (Max (2t, t ′), b) is satisfied, and R ≧ q + 3r And (Rq) is a multiple of 3, and γ is the primitive element of (Rq) / 3-order extension GF (2 ^{(Rq) / 3} ) with 2 as the base, γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b−1 ″)] is established, and Φ is additive Is effectively achieved by being a homomorphism from GF (2 ^q ) to GF (2 ^{(Rq) / 2} ).

Further, the above-described object of the present invention is to generate a bit error pointer for detecting which bit of the received word is incorrect based on the syndrome, and based on the generated bit error pointer. When the error of the received word is corrected by inverting the bit value of the received word corresponding to the error bit, and when it is detected that the bit error of the received word cannot be corrected, an uncorrectable error is detected. By outputting a detection signal, or the error correction means includes H ′ decoding means, H ″ multiplying means, parallel decoding means on GF (2 ^r ), and error generation means on GF (2 ^b ). Or the inverting means, or the H ′ decoding means, based on the upper q bits of the syndrome generated by the syndrome generating means, (E _A) generates said H "multiplication means, the H 'based on the sum (e _A) of errors for each of the bytes generated by the decoding means, the upper q bits and H of the syndrome" of The parallel decoding means on the GF (2 ^r ) generates a transposed matrix product, and the product of the upper q bits of the syndrome generated by the H ″ multiplying means and the transposed matrix of H ″, and the syndrome generating means in based on the remaining lower bits except for the most q bits of the generated the syndrome, GF (2 ^r) on the bit-error pointer, and GF (2 ^r) on the parallel decoding all impossible error correction in The first uncorrectable error detection signal output when the error is generated, and the error generation means on the GF (2 ^b ) is a sum of errors for each byte generated by the H ′ decoding means ( e _A), and said GF ( based on the bit error pointer on said generated by parallel decoding means GF ^{(2 r)} on ^r), by converting the error on GF ⁽² r) the error on GF ^{(2 b),} GF A bit error pointer on (2 ^b ) and a second uncorrectable error detection signal that is output when error correction is deemed impossible, and the inverting means is on GF (2 ^b ) By inverting the bit value of the received word corresponding to the bit error pointer on GF (2 ^b ) based on the bit error pointer on GF (2 ^b ) generated by the error generation means of By correcting an error in the received word, or in the error correction means, the first uncorrectable error detection signal generated by the parallel decoding means on the GF (2 ^r ), and the GF (2 ^b ) generated by the error generation means above By calculating the logical sum of the second uncorrectable error detection signal, outputting a third uncorrectable error detection signal indicating that an error exceeding the correction capability has been detected, or the GF ( The error generation means on 2 ^b ) includes an error byte detection means for detecting that the syndrome is non-zero, and a bit on the GF (2 ^b ) from 1 byte of the bit error pointer on the GF (2 ^r ). T-bit error correction decoding means for outputting 1 byte of an error pointer; bit-by-bit selection means for selecting an input signal according to a control signal; and Hamming weight detection means for detecting a Hamming weight 1 of the input signal. by providing, or error vector generating means on the GF (2 ^b) is an error byte detection means, and t-bit error correction decoding means, and a bit for each selection means, Hamming And a look detecting means, the error byte detection means inputs the 1-byte bit-error pointer on the GF (2 ^r), and outputs a syndrome detection signal of 1 bit, the t-bit error correction decoding The means inputs a predetermined 1 byte of the bit error pointer on the GF (2 ^r ), outputs a 1 byte corresponding to the predetermined 1 byte of the bit error pointer on the GF (2 ^b ), and A detection signal for detecting an error exceeding the correction capability is also output, the bit-by-bit selection unit selects each bit of two input signals according to a control signal, and the Hamming weight detection unit is the error byte detection unit When the syndrome detection signal output from is input, the Hamming weight of the input syndrome detection signal is calculated, and the Hamming weight is 1 1 is output, otherwise 0 is output, or in the t-bit error correction decoding means, the error exceeding the correction capability is an error on the GF (2 ^r ). An error e _I on GF (2 ^b ) that is not mapped from e ′ _I , or the error generation unit on GF (2 ^b ) outputs from the t-bit error correction decoding unit The detected signal is input to a multi-input OR gate circuit, and the multi-input OR gate circuit outputs the second uncorrectable error detection signal based on the input detection signal. In the error generation means on GF (2 ^b ), the signal output from the Hamming weight detection means and the syndrome detection signal output from the error byte detection means are respectively input to the 2-input AND gate circuit. The signal output from the two-input AND gate circuit is used as the control signal of the bit-by-bit selection unit, and the bit-by-bit selection unit is configured to output the signal output from the t-bit error correction decoding unit and the byte. The error sum (e _A ) is selected according to the control signal, the selected signals are collected, and a bit error pointer on the GF (2 ^b ) is output.

Furthermore, the present invention provides an encoding processing step for generating a transmission word based on input information data, and a decoding for correcting or detecting the error by inputting the transmission word in which an error has occurred in an information transmission path as a reception word. The present invention relates to a method for correcting and detecting a plurality of spotty byte errors within a byte, wherein the encoding processing step includes a parity check matrix representing a spotty byte error control code, and the input information data. The transmission word is generated by adding the check information generated based on the input information data, and the decoding processing step generates a syndrome of the received word based on the parity check matrix And correcting or detecting an error in the received word based on the syndrome generated by the syndrome generation processing step. An error correction processing step, or the error correction processing step generates a bit error pointer for detecting which bit of the received word is incorrect based on the syndrome, and the generated bit Based on the error pointer, by inverting the bit value of the received word corresponding to the error bit, the error of the received word is corrected, and when it is detected that the bit error of the received word cannot be corrected, By outputting an uncorrectable error detection signal, or the error correction processing step includes an H ′ decoding processing step, an H ″ multiplication processing step, a parallel decoding processing step on GF (2 ^r ), and GF ( by having 2 ^b) and the error generation processing step on, and inversion processing step, or the H 'decoding processing step, the Shindoro And the upper q bits of the syndrome generated by the beam generation process step based on, generates a sum (e _A) of an error in each byte, the H "multiplication processing step is generated by the H 'decoding processing step Further, based on the error sum (e _A ) for each byte, a product of the upper q bits of the syndrome and a transposed matrix of H ″ is generated, and the parallel decoding processing step on the GF (2 ^r ) Based on the product of the upper q bits of the syndrome generated in the H "multiplication step and the transpose matrix of H" and the remaining lower bits excluding the upper q bits of the syndrome generated in the syndrome generation step first uncorrectable error detection output when deemed impossible error correction in a parallel decoding on GF (2 ^r) on the bit-error pointer, and GF (2 ^r) It generates a signal, error generation processing step on the GF (2 ^b), the H 'sum of errors for each of the bytes generated by the decoding process step (e _A), and, the GF (2 ^r) above On the basis of the bit error pointer on GF (2 ^r ) generated in the parallel decoding processing step, an error on GF (2 ^r ) is converted into an error on GF (2 ^b ), and GF (2 ^b ) generating a bit error pointer on the above and a second uncorrectable error detection signal that is output when error correction is deemed impossible, and the inversion processing step is on the GF (2 ^b ) Based on the bit error pointer on GF (2 ^b ) generated in the error generation processing step, by inverting the bit value of the received word corresponding to the bit error pointer on GF (2 ^b ), Correct the received word error The Rukoto, or the error correction processing step, the first uncorrectable error detection signal generated by the parallel decoding processing steps on the GF (2 ^r) and an error on the GF (2 ^b) A third uncorrectable error detection signal indicating that an error exceeding the correction capability is detected is obtained by performing a logical sum of the second uncorrectable error detection signal generated in the generation processing step. Effectively achieved by

The above-described object of the present invention is to provide an error generation processing step on the GF (2 ^b ), an error byte detection processing step for detecting that the syndrome is non-zero, and a bit error on the GF (2 ^r ). A t-bit error correction decoding process step for outputting 1 byte of a bit error pointer on the GF (2 ^b ) from 1 byte of the pointer, a bit-by-bit selection process step for selecting an input signal according to a control signal, and an input A Hamming weight detection processing step for detecting a Hamming weight 1 of the signal, or an error generation processing step on the GF (2 ^b ) includes an error byte detection processing step and a t-bit error correction decoding processing. A bit-by-bit selection processing step and a Hamming weight detection processing step, and the error byte detection processing step. , The GF as input (2 ^r) 1-byte bit-error pointer on, and outputs a syndrome detection signal of 1 bit, the t-bit error correction decoding processing step, bit error on the GF (2 ^r) A predetermined 1 byte of the pointer is input, 1 byte corresponding to the predetermined 1 byte of the bit error pointer on the GF (2 ^b ) is output, and a detection signal for detecting an error exceeding the correction capability is also provided. The bit-by-bit selection processing step selects each bit of the two input signals according to a control signal, and the Hamming weight detection processing step inputs the syndrome detection signal output from the error byte detection processing step. And calculates the Hamming weight of the input syndrome detection signal, and outputs 1 when the Hamming weight is 1. Otherwise, by outputting 0, or in the t-bit error correction decoding processing step, the error exceeding the correction capability is not mapped from the error e ′ _I on the GF (2 ^r ). Due to the error e _I on the GF (2 ^b ), or in the error generation processing step on the GF (2 ^b ), the detection signal output from the t-bit error correction decoding processing step is multi-input. The multi-input OR gate circuit outputs the second uncorrectable error detection signal based on the input detection signal, and an error on the GF (2 ^b ) is input to the OR gate circuit. In the generation processing step, the signal output from the Hamming weight detection processing step and the syndrome detection signal output from the error byte detection processing step are each input into two inputs The signal input to the gate circuit and output from the 2-input AND gate circuit is used as the control signal used in the bit-by-bit selection processing step, and the bit-by-bit selection processing step is output from the t-bit error correction decoding processing step. And the error sum for each byte (e _A ) is selected according to the control signal, the selected signals are collected, and a bit error pointer on the GF (2 ^b ) is output. To be achieved.

  According to the intra-byte multiple spotty byte error correction / detection method and apparatus according to the present invention, a transmission word in which check information generated based on a parity check matrix representing a code and input information data is added to the input information data Generates a syndrome based on the parity check matrix for a received word that may have an error that has occurred in the information transmission path, and corrects or detects an error in the received word based on the syndrome. Therefore, for spotty byte errors that are errors up to t bits such as 2 bits and 3 bits in 1 byte, multiple spotty byte errors in any number of bytes (designed by investigating error tendency) It is possible to implement an intra-byte multiple spotty byte error control code having a function of correcting and detecting (which can be arbitrarily determined by the user).

  This makes it possible to handle the configuration of the parity check matrix, which is a code for detecting or correcting an error, and the decoding processing procedure in a unified manner without having to correspond to each error occurrence situation, and in the coding function of the present invention. By simply setting the t value, b value, and d value, the parity check matrix H and the decoding procedure can be handled uniformly, and a coding function that can flexibly cope with the error occurrence state can be provided. . In addition, a code function that can more flexibly cope with an error occurrence state can be provided by the code for controlling two types of spotty byte errors having different sizes according to the present invention.

  Furthermore, by selecting an integer bit length t smaller than the byte length which is b bits, the number of check bits can be greatly reduced as compared with a conventional byte error control code (corresponding to t = b). Become. As a result, the ratio of the number of check bits to the code length can be reduced, and the coding rate can be remarkably improved, so that highly efficient and highly reliable data transfer can be realized.

  In short, according to the intra-byte multiple spotty byte error correction / detection method and apparatus of the present invention having an excellent function such as `` can control multiple spotty byte errors in multiple bytes '', which does not exist in the conventional coding technology, Compared with conventional multi-byte error control codes using Reed-Solomon codes, the number of check bits can be reduced and the coding rate can be improved, and the bit error occurrence status can be flexibly handled. It is possible to provide a remarkable effect that a code function that can be provided can be provided.

  In addition, according to the multiple spotty byte error correction / detection method and apparatus in a byte of the present invention having a function such as “it is possible to control two types of spotty byte errors having different sizes generated in one byte”. Compared with conventional spotty byte error control codes and Reed-Solomon codes (Reed-Solomon codes), the number of check bits is reduced and the coding rate is improved. There is a remarkable effect that it is possible to provide a code function that can flexibly cope with the occurrence state.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  Terms used to describe the present invention are defined as follows. First, in the embodiment of the present invention, the target digital data is a signal (binary code) of a combination of 0 and 1, and the occurrence of a bit error is that any bit in a code word is 0. → 1 or 1 → 0. Further, the occurrence of a spotty byte error means that 0 to 1 or 1 to 0 until t bits (t ≦ b) in a byte consisting of b bits. In the present embodiment, when there is an “error”, all of the above “bit error” and “spotty byte error” are included unless otherwise specified. An error in which a plurality of spotty byte errors (that is, two or more spotty byte errors) occur in one byte is referred to as “a plurality of spotty byte errors in a byte”.

  First, the overall configuration of the intra-byte multiple spotty byte error correction / detection apparatus 100 according to the present invention will be described. FIG. 1 is a block diagram showing a schematic configuration of an intra-byte multiple spotty byte error correction / detection apparatus 100 (hereinafter abbreviated as spotty byte apparatus 100) according to the present invention. As shown in FIG. 1, the spotty byte device 100 has a configuration including an encoding circuit 2, a circuit 3, a decoding circuit 4, and the like.

  The encoding circuit 2 is a circuit that generates inspection information for correcting and detecting an error with respect to target digital data (hereinafter referred to as input information data 30). The inspection information is composed of an arbitrary number of inspection bits.

  The circuit 3 corresponds to a communication path such as a memory, and in the present embodiment, the data that has passed through the circuit 3 may have an error. That is, the data output from the encoding circuit 2 and input to the circuit 3 has no error, whereas the data output from the circuit 3 includes a case where an error has occurred. .

  The decoding circuit 4 includes a syndrome generation circuit 1 and an error correction circuit 5. The decoding circuit 4 is a circuit for detecting whether or not an error is included in the received word 32, and specifying and correcting the error part. The detailed configuration of the decoding circuit 4 will be described in the decoding process described later.

  In the encoding process and decoding process described later, since matrix operation based on Galois field theory is performed, each data in the encoding circuit 2, the decoding circuit 4, or the communication path is a matrix with alphabetic characters, or Expressed as a vector. Specifically, for example, input information data D, code (parity check matrix) H, check information C, transmission word V, reception word V ′, and syndrome S are represented.

  Next, the overall operation of the spotty byte device 100 of the present invention will be described. FIG. 2 is a flowchart showing a processing procedure of the overall operation of the spotty byte device 100 of the present invention shown in FIG.

  As shown in FIG. 2, first, in the encoding circuit 2, when input information data (D) 30 is input, check information (C) is generated using a parity check matrix (H) described later in detail. (Step S200). Next, the encoding circuit 2 adds this inspection information (C) to the input information data (D) 30 and sends it as a transmission word (V) 31 to the circuit 3 which is a communication path such as a memory (step S201). ). A received word (V ′) 32 that may contain an error is input to the decoding circuit 4 via the circuit 3 (step S202).

Next, the decoding circuit 4 first checks whether an error has occurred in the input received word (V ′) 32 using the parity check matrix (H) used in the encoding circuit 2. Specifically, the syndrome generation circuit 1 of the decoding circuit 4 multiplies the received word (V ′) 32 by the transposed matrix (H ^T ) obtained by transposing the parity check matrix (H) representing the code. As a result, a syndrome (S) is generated (step S203). Since the value of the syndrome (S) 33 changes according to the received word (V ′) 32, it is possible to determine whether the received word (V ′) 32 includes an error.

Therefore, the error correction circuit 5 of the decoding circuit 4 first determines whether or not an error has been detected based on the value of the syndrome (S) 33 (step S204), and whether or not error correction is possible. Judgment is made (step S205), and if correction is possible as a result of the judgment, an error is corrected (step S206). Then, when the spotty byte error correction process is performed on the received word V ′, the error correction circuit 5 outputs the corrected V ′ as received word output information data (V ^* ) 34 (step S207). . On the other hand, if an uncorrectable spotty byte error or the like is detected as a result of the determination in step S205, the error correction circuit 5 uses a UCE (Uncorrectable Error) signal as an uncorrectable error detection signal. 35 is output (step S208).

  Next, the configuration of the parity check matrix (H) used in the encoding circuit 2 and the decoding circuit 4 described above will be described in detail. The parity check matrix H (also referred to as H matrix, code matrix, or simply check matrix) of the present invention is a code having a function of correcting and detecting a plurality of spotty byte errors.

  In the present embodiment, a general code configuration method that can be configured for any d (d is an integer of 3 or more), t (t is an integer of 1 or more and b or less), and b (an integer of 2 or more). In addition to presenting the method, a method that can actually correct and detect an error by the code is shown, and an encoding circuit and a decoding circuit for the method are presented, and the error can be specifically corrected and detected by the encoding circuit and the decoding circuit. Indicates.

を有していることを具体的に示す。例えば、距離ｄ＝５の２重バイト内複数スポッティバイト誤り訂正符号の場合、

となる。 For the distance d,

It shows concretely that it has. For example, in the case of a multiple spotty byte error correction code in a double byte with a distance d = 5,

It becomes.

のとき、従来のバイト誤り制御符号であるリード・ソロモン符号（ＲＳ符号）に一致する。 In the present code construction method, when t = b, as will be described later,

At this time, it matches the Reed-Solomon code (RS code) which is a conventional byte error control code.

Now, R-bit check information (C) is added to K-bit input information data (D) 30, and a transmission word V (N-bit row vector having a length of N = K + R bits satisfying a certain function) ) Can be constructed, a relationship of V · H ^T = 0 between the transmission word (V) and the R-row N-column binary parity check matrix (H) defining the code Is established. Here, H ^T is a permutation matrix generated by rearranging the rows and columns of the parity check matrix (H), also 0 on the right side shows the zero line vector of R bits.

  In the present embodiment, the parity check matrix (H) having R rows and N columns used for the intra-byte multiple spotty byte error control code having the distance d is configured as shown in the following equation (1).

ただし、Ｒ＝ｑ＋（ｄ−２）ｒ、Ｎ＝ｂｎ、０≦ｉ≦ｎ−１、ｎ＝２^ｒ−１である。

However, R = q + (d−2) r, N = bn, 0 ≦ i ≦ n−1, and n = 2 ^r −1.

The matrix H ′ constituting the above equation 1 is a binary matrix of q rows and b columns (q ≦ b) composed of q-th order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following equation 2. (D-1) has a rank equal to or greater than the smaller value of either t or b. That is, Rank (H ′) ≧ Min ((d−1) t, b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが（ｄ−１）ｔ＜ｂのとき、行列Ｈ’は最小ハミング距離（ｄ−１）ｔ＋１を有する符号の検査行列、すなわち、（ｄ−１）ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a unit matrix of b × b), and the rank of the matrix H ′ is (d−1) t. When <b, the matrix H ′ is a parity check matrix of a code having a minimum Hamming distance (d−1) t + 1, that is, a parity check of a (b, bq) code having a (d−1) t-bit error detection function. Equivalent to a matrix.

またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有する。すなわち、

を満足する。ここで、

はｘを超えない最小の整数を表す。 In addition, the matrix H ″ that constitutes the above Equation 1 is 2 in r rows and b columns (r ≦ b) composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in Equation 3 below. Is an original matrix,

Or, it has a rank equal to or larger than the smaller value of b. That is,

Satisfied. here,

Represents the smallest integer not exceeding x.

ここで、行列Ｈ”のランクがｂに等しいとき、行列Ｈ”はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ”のランクが

のとき、行列Ｈ”は最小ハミング距離

を有する符号の検査行列、すなわち、

ビット誤り検出機能を有する（ｂ、ｂ−ｒ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b (for example, a unit matrix of b × b), and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

It is equal to a parity check matrix of a (b, br) code having a bit error detection function.

Next, when γ is a primitive element of an r-th order extension field GF (2 ^r ) with 2 as a base, γ ⁱ H ″ can be defined by the following equation (4).

このとき、最大符号長Ｎは、Ｎ＝ｂ（２^ｒ―１）である。

At this time, the maximum code length N is N = b (2 ^r −1).

とした場合に、Ｈ’及びＨ”はランクｂを有することから、従来のＲＳ符号のパリティ検査行列と一致する。 The parity check matrix (H) shown in Equation 1 is a parameter.

In this case, since H ′ and H ″ have rank b, they match the parity check matrix of the conventional RS code.

  In the present embodiment, a decompression code can be defined. The parity check matrix (H) having R rows and N columns used for the multi-spotty byte error control code in the extended byte having the distance d can be configured as shown in the following equation (5).

ただし、Ｒ≧ｑ＋（ｄ−２）ｒ、かつ（Ｒ−ｑ）は（ｄ−２）の倍数であり、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／（ｄ−２）、０≦ｉ≦ｎ−１、（Ｒ−ｑ）は（ｄ−２）の倍数とし、ｎ＝２^{（Ｒ−ｑ）／（ｄ−２）}−１である。

However, R ≧ q + (d−2) r and (R−q) is a multiple of (d−2), N = b (n + 1) + (R−q) / (d−2), 0 ≦ i ≦ n−1 and (R−q) are multiples of (d−2), and n = 2 ^{(R−q) / (d−2)} −1.

The matrix H ′ constituting the equation 5 is a binary matrix of q rows and b columns (q ≦ b) composed of q-order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following equation 6. (D-1) has a rank equal to or greater than the smaller value of either t or b. That is, Rank (H ′) ≧ Min ((d−1) t, b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが（ｄ−１）ｔ＜ｂのとき、行列Ｈ’は最小ハミング距離（ｄ−１）ｔ＋１を有する符号の検査行列、すなわち、（ｄ−１）ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a unit matrix of b × b), and the rank of the matrix H ′ is (d−1) t. When <b, the matrix H ′ is a parity check matrix of a code having a minimum Hamming distance (d−1) t + 1, that is, a parity check of a (b, bq) code having a (d−1) t-bit error detection function. Equivalent to a matrix.

またはｂのうちいずれか小さい値に等しいか大きいランク（Ｒａｎｋ）を有する。すなわち、

を満足する。 In addition, the matrix H ″ that constitutes the above Equation 1 is 2 in r rows and b columns (r ≦ b) composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in Equation 7 below. Is an original matrix,

Or, it has a rank equal to or larger than the smaller value of b. That is,

Satisfied.

ここで、行列Ｈ”のランクがｂに等しいとき、行列Ｈ”はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ”のランクが

のとき、行列Ｈ”は最小ハミング距離

を有する符号の検査行列、すなわち、

ビット誤り検出機能を有する（ｂ、ｂ−ｒ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b (for example, a unit matrix of b × b), and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

It is equal to a parity check matrix of a (b, br) code having a bit error detection function.

Next, R ≧ q + (d−2) r and R−q is a multiple of d−2, and γ is 2 as the base (R−q) / (d−2) -order extension field GF (2 ⁽ Γ ⁱ H ″ can be defined by the following equation (8) when ^{R−q) / (d−2)} ).

ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／（ｄ−２）}）への準同型写像（homomorphism）である。すなわち、Φ：ＧＦ（２^ｑ）→ＧＦ（２^{（Ｒ−ｑ）／（ｄ−２）}）である。このとき、最大符号長Ｎは、Ｎ＝ｂ・２^{（Ｒ−ｑ）／（ｄ−２）}＋（Ｒ−ｑ）／（ｄ−２）である。また、Ｒ≧ｑ＋（ｄ−２）ｒであることから、数５のＨの２行目から下の行に用いるＨ”の行数ｒ’はｒより大きい値をとることができ、数５で表される符号は、（ｄ−２）ビットずつ検査ビット数を増大させることにより、任意の符号長に対して構成できる符号であることに注意する必要がある。

Here, Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / (d−2)} ) under addition. That is, Φ: GF (2 ^q ) → GF (2 ^{(R−q) / (d−2)} ). At this time, the maximum code length N is N = b · 2 ^{(R−q) / (d−2)} + (R−q) / (d−2). Further, since R ≧ q + (d−2) r, the number r ′ of H ″ used for the second row from the second row of H in Formula 5 can take a value larger than r. It should be noted that the code represented by is a code that can be configured for an arbitrary code length by increasing the number of check bits by (d-2) bits.

とした場合に、Ｈ’及びＨ”はランクｂを有することから、従来の２次伸長ＲＳ符号のパリティ検査行列と一致する。 The parity check matrix (H) shown in Equation 5 is a parameter.

Since H ′ and H ″ have rank b, they match the parity check matrix of the conventional secondary extended RS code.

を有していることを具体的に示す。一般に、

において、パリティ検査行列Ｈ＝［Ｈ_０、Ｈ_１、・・・、Ｈ_ｎ−１］が、以下に示す必要十分条件を満たしていることを示せばよい。ただし、Ｈ_ｉはＲ×ｂの小行列である。 Next, the code represented by the parity check matrix (H) shown in Equation 1 above has a distance d,

It shows concretely that it has. In general,

, It can be shown that the parity check matrix H = [H ₀ , H ₁ ,..., H _n−1 ] satisfies the necessary and sufficient conditions shown below. Here, H _i is a small matrix of R × b.

ここで、１バイト中のｔビットまでの誤りの集合をＥ_ｔ／ｂとし、ｅ_ｉは誤りの集合Ｅ_ｔ／ｂに含まれる任意の誤りとする。また、ｉ_１、ｉ_２、・・・、ｉ_ｋ・・・、ｉ_ｄ−１（０≦ｉ_１、ｉ_２、・・・、ｉ_ｋ、・・・、ｉ_ｄ−１≦ｎ−１）はすべて異なるものとする。

Here, a set of errors up to t bits in one byte is E _{t / b,} and e _i is an arbitrary error included in the error set E _{t / b} . _{Also, i 1, i 2, ···} , i k ···, i d-1 (0 ≦ i 1, i 2, ···, i k, ···, i d-1 ≦ n-1 ) Are all different.

Spotty byte error correction is executed by using the syndrome (S) 33 generated by the syndrome generation circuit 1 described above. Here, the relationship between the syndrome (S) 33 and the parity check matrix (H) is expressed as S = V ′ · H ^T. Now, when the received word (V ′) 32 includes an error (E) with respect to the original transmitted word (V) 31 and is expressed by V ′ = V + E, the syndrome (S) 33 is S = V ′ · H ^T = (V + E) · H ^T = V · H ^T + E · H ^T

As described above, since the relationship of V · H ^T = 0 is established, the syndrome S = E · H ^T is finally satisfied. That is, since the syndrome (S) 33 is determined only by the error (E) without being influenced by the transmission word (V) 31, it is possible to perform spotty byte error correction based on the syndrome (S) 33. This can be determined by the result of the value of E · H ^T calculated from the parity check matrix (H) and the error (E).

個以下のバイト内複数スポッティバイト誤りのシンドロームが異なればよい。よって、

個のバイト内複数スポッティバイト誤りのシンドローム和が０とならなければよい。 The necessary and sufficient conditions shown in the above equations 9, 10, and 11 are as follows. For the distance d, all of the multiple spotty byte error syndromes that can be corrected / detected and all other intra-byte multiple spot errors that can be corrected. It shows that the syndrome of tibito error is different. That is, the syndrome of multiple spotty byte errors within m bytes or less and other

It is sufficient that the syndromes of multiple spotty byte errors in less than or equal to bytes are different. Therefore,

It is only necessary that the syndrome sum of multiple spotty byte errors within one byte is not zero.

個のバイト内複数スポッティバイト誤りが、すべて同じバイトに生じた場合であり、それぞれのシンドロームが異なることを示している。 Equation (9) indicates that multiple spotty byte errors in m bytes

This is a case where multiple spotty byte errors within one byte are all generated in the same byte, indicating that each syndrome is different.

個のバイト内複数スポッティバイト誤りが生じ、うち２からｄ−２バイトにおいて、バイト内複数スポッティバイト誤りが同じバイトに生じている場合であり、これらのシンドロームが異なることを示している。 In addition, Equation (10) indicates that there are multiple spotty byte errors in m bytes.

This is a case where a plurality of spotty byte errors in one byte occur, and from 2 to d-2 bytes, a plurality of spotty byte errors in a byte occur in the same byte, indicating that these syndromes are different.

個のバイト内複数スポッティバイト誤りが、すべて異なるバイトに生じている場合であり、それぞれのシンドロームが異なることを示している。 Further, Equation 11 shows that multiple spotty byte errors in m bytes

This is a case where multiple spotty byte errors in one byte are all generated in different bytes, indicating that the respective syndromes are different.

Here, since (e _i +... + E _{i + j} ) includes multiple spotty byte errors in j bytes or less, the syndrome sum of (d−1) multiple spotty byte errors in bytes is 0. It can be shown that the syndromes of multiple spotty byte errors in less than (d-1) bytes are different by indicating that this is not true.

を有していることを以下に示す。

＜１＞必要十分条件（数９）を満たしていることの証明
シンドロームＳとして、下記数１２の関係が成立していると仮定する。 Therefore, by indicating that the code represented by the parity check matrix shown in Equation 1 satisfies the necessary and sufficient conditions shown in Equation 9, Equation 10, and Equation 11, the distance d

The following is shown.

<1> Proof that the Necessary and Sufficient Condition (Equation 9) is Satisfied As the syndrome S, it is assumed that the relationship of the following equation 12 holds.

数１２において、Ｈ’はランクがＭｉｎ（（ｄ−１）ｔ、ｂ）、かつｅ_１＋ｅ_２＋・・・＋ｅ_ｄ−１≠０より（ｅ_１＋ｅ_２＋・・・＋ｅ_ｄ−１）・Ｈ’^Ｔ≠０。よって、数１で表される符号は、必要十分条件（数９）を満たしている。

＜２＞必要十分条件（数１０）を満たしていることの証明
シンドロームＳとして、下記数１３の関係が成立したと仮定する。

In Expression 12, H ′ has a rank of Min ((d−1) t, b) and e ₁ + e ₂ +... + _Ed-1 ≠ 0 (e ₁ + e ₂ +... + _Ed-1). ) · H ′ ^T ≠ 0. Therefore, the code represented by Equation 1 satisfies the necessary and sufficient condition (Equation 9).

<2.

数１３の（ｅ_１＋ｅ_２＋・・・＋ｅ_ｄ−１）・Ｈ’^Ｔ＝０において、Ｈ’はランクがＭｉｎ（（ｄ−１）ｔ、ｂ）より、下記数１４が得られる。

In (e ₁ + e ₂ +... + E _d−1 ) · H ′ ^T = 0 in the equation 13, the following equation 14 is obtained from the rank of H ′ as Min ((d−1) t, b).

数１４において、右からＨ”^Ｔをかけると、下記数１５が得られる。

In Expression 14, when H ″ ^T is applied from the right, the following Expression 15 is obtained.

数１３、数１５において、

をそれぞれｘ_１、ｘ_２、・・・、ｘ_ρ、ρ＞１、とおくと、下記数１６が得られる。ここで、

より、

となるｉは、高々１個のみ存在する。Ｈ”はランク

より、ｘ_２≠０、ｘ_３≠０、・・・、ｘ_ρ≠０（ｘ_１は０となることもある）、ρ＞１、となる。

In Equations 13 and 15,

Where x ₁ , x ₂ ,..., X _ρ , ρ> 1, respectively, the following equation 16 is obtained. here,

Than,

There is at most one i. H ”is rank

Therefore, x ₂ ≠ 0, x ₃ ≠ 0,..., X _ρ ≠ 0 (x ₁ may be 0), ρ> 1.

数１６において、上からρ（＜ｄ−１）個の式を行列の形で表すと、下記数１７が得られる。

In Expression 16, when ρ (<d−1) equations from the top are expressed in the form of a matrix, the following Expression 17 is obtained.

数１７中のρ行ρ列の行列は、ヴァンデルモンドの行列の形をしているため、正則行列である。よって、数１７の両辺に左からこの行列の逆行列を乗算すると、下記数１８が得られる。

The matrix of ρ rows and ρ columns in Equation 17 is a regular matrix because it is in the form of a Vandermonde matrix. Therefore, when both sides of Equation 17 are multiplied by the inverse matrix of this matrix from the left, the following Equation 18 is obtained.

数１８は、ｘ_１＝０、ｘ_２＝０、・・・、ｘ_ρ＝０、ρ＞１、となり、前提であるｘ_２≠０、ｘ_３≠０、・・・、ｘ_ρ≠０に矛盾する。よって、数１で表される符号は、必要十分条件（数１０）を満たしている。

＜３＞必要十分条件（数１１）を満たしていることの証明
シンドロームＳとして、下記数１９の関係が成立したと仮定する。

Number _{18, x 1 = 0, x 2} = 0, ···, x ρ = 0, ρ> 1, next, _{x 2} ≠ 0 is a _{prerequisite, x 3 ≠ 0, ···,} x ρ ≠ 0 Contradict. Therefore, the code represented by Equation 1 satisfies the necessary and sufficient condition (Equation 10).

<3> Proof that the Necessary and Sufficient Condition (Equation 11) is satisfied As a syndrome S, it is assumed that the relationship of the following equation 19 is established.

数１９の（ｅ_１＋ｅ_２＋・・・＋ｅ_ｄ−１）・Ｈ’^Ｔ＝０において、Ｈ’はランクがＭｉｎ（（ｄ−１）ｔ、ｂ）より、下記数２０が得られる。

In (e ₁ + e ₂ +... + E _d−1 ) · H ′ ^T = 0 in the equation 19, the following equation 20 is obtained from the rank of H ′ as Min ((d−1) t, b).

数２０において、右からＨ”^Ｔをかけると、下記数２１が得られる。

In Formula 20, when H ″ ^T is applied from the right, the following Formula 21 is obtained.

数１９、数２１において、ｅ_１・Ｈ”^Ｔ、ｅ_２・Ｈ”^Ｔ、・・・、ｅ_ｄ−１・Ｈ”^Ｔをそれぞれｘ_１、ｘ_２、・・・、ｘ_ｄ−１

より、ｘ_１≠０、ｘ_２≠０、・・・、ｘ_ｄ−１≠０）と表すと、下記数２２が得られる。

The number 19, in number ^{_{21, e 1 · H "T}} , e 2 · H" T, ···, e d-1 · H "T each _{x 1, x 2, ···,} x d-1

Thus, when expressed as x ₁ ≠ 0, x ₂ ≠ 0,..., X _d−1 ≠ 0, the following equation 22 is obtained.

数２２を行列の形で表すと、下記数２３が得られる。

When Expression 22 is expressed in the form of a matrix, the following Expression 23 is obtained.

数２３中の（ｄ−１）行（ｄ−１）列の行列は、ヴァンデルモンドの行列の形をしているため、正則行列である。よって、上記数２３の両辺に左から逆行列をかけると、下記数２４が得られる。

The matrix of (d-1) rows (d-1) columns in Equation 23 is a regular matrix because it is in the form of a Vandermonde matrix. Therefore, when the inverse matrix is applied to both sides of the equation 23 from the left, the following equation 24 is obtained.

数２４は、ｘ_１＝０、ｘ_２＝０、・・・、ｘ_ｄ−１＝０となり、前提であるｘ_１≠０、ｘ_２≠０、・・・、ｘ_ｄ−１≠０に矛盾する。よって、数１で表される符号は、必要十分条件（数１１）を満たしている。

Number _{24, x 1 = 0, x 2} = 0, ···, x d-1 = 0 _{becomes, x 1 ≠ 0, x 2} ≠ 0 is premised, _..., the _{x d-1} ≠ 0 Contradict. Therefore, the code represented by Equation 1 satisfies the necessary and sufficient condition (Equation 11).

個以下のバイト内複数スポッティバイト誤りを訂正し、ｍ個以下のバイト内複数スポッティバイト誤りを検出する機能を有していることを証明することができた。 Therefore, from the proof results in <1> to <3> described above, the parity check matrix (H) shown in the above equation 1 is included in the received word (V ′) 32 with respect to the distance d.

It was proved that it has a function of correcting multiple spotty byte errors in less than m bytes and detecting multiple spotty byte errors in m bytes or less.

を有していることを示すことができる。 Similarly, the expansion code represented by the parity check matrix (H) shown in the above equation 5 also satisfies the necessary and sufficient conditions shown in the above equations 9, 10, and 11 to thereby reduce the distance d. In contrast,

Can be shown.

  Here, it is shown that the parity check matrix (H) shown in Equation 1 can be configured by giving specific code parameters. Note that this parity check matrix (H) is merely an example, and it is needless to say that the present invention is not limited to this.

Now, for a memory system using a memory element having 8 bits as read / write data width, parameters of d = 5, t = 2, b = 8 are given, and an error of 2 bits or less in a byte is a spotty byte error. Assuming that a parity check matrix (H) of a D _2/8 EC code that corrects multiple spotty byte errors in two bytes is configured. At this time, from Min ((d−1) t, b) = Min (8, 8) = 8, a matrix having rank 8 may be configured as the matrix H ′. As an example of this, an 8 × 8 (meaning 8 rows and 8 columns) unit matrix shown in the following equation 25 may be configured.

また、

より、行列Ｈ”として、ランク４を有する４ビット誤り検出符号の検査行列を構成すればよい。この一例として、下記数２６に示す６×８行列を示す。

Also,

Thus, a check matrix of a 4-bit error detection code having rank 4 may be configured as the matrix H ″. As an example of this, a 6 × 8 matrix represented by the following Expression 26 is shown.

次に、γをＧＦ（２）上の６次の原始多項式ｇ（ｘ）＝ｘ^６＋ｘ＋１の根とすると、γは、６次の列ベクトルγ＝（０１００００）^Ｔと表現することができる。

Next, if γ is a root of a sixth-order primitive polynomial g (x) = x ⁶ + x + 1 on GF (2), γ can be expressed as a sixth-order column vector γ = (010000) ^T.

That is, the correspondence between the display γ ⁱ of γ and the vector display is as follows.
γ ⁰ = (100,000) ^T , γ ¹ = (010000) ^T , γ ² = (001000) ^T ,
γ ³ = (000100) ^T , γ ⁴ = (0000010) ^T , γ ⁵ = (000001) ^T ,
γ ⁶ = (110000) ^T , γ ⁷ = (011000) ^T , γ ⁸ = (001100) ^T ,
γ ⁹ = (000110) ^T , γ ¹⁰ = (0000011) ^T , γ ¹¹ = (110001) ^T ,
γ ¹² = (101000) ^T , γ ¹³ = (010100) ^T , γ ¹⁴ = (001010) ^T ,
γ ¹⁵ = (000101) ^T , γ ¹⁶ = (110010) ^T , γ ¹⁷ = (011001) ^T ,
γ ¹⁸ = (111100) ^T , γ ¹⁹ = (011110) ^T , γ ²⁰ = (001111) ^T ,
γ ²¹ = (110111) ^T , γ ²² = (101011) ^T , γ ²³ = (100101) ^T ,
γ ²⁴ = (100010) ^T , γ ²⁵ = (010001) ^T , γ ²⁶ = (111000) ^T ,
γ ²⁷ = (011100) ^T , γ ²⁸ = (001110) ^T , γ ²⁹ = (000111) ^T ,
γ ³⁰ = (110011) ^T , γ ³¹ = (101001) ^T , γ ³² = (100100) ^T ,
γ ³³ = (010010) ^T , γ ³⁴ = (001001) ^T , γ ³⁵ = (110100) ^T ,
γ ³⁶ = (011010) ^T , γ ³⁷ = (001101) ^T , γ ³⁸ = (110110) ^T ,
γ ³⁹ = (011011) ^T , γ ⁴⁰ = (111101) ^T , γ ⁴¹ = (101110) ^T ,
γ ⁴² = (010111) ^T , γ ⁴³ = (1111011) ^T , γ ⁴⁴ = (101101) ^T ,
γ ⁴⁵ = (100110) ^T , γ ⁴⁶ = (010011) ^T , γ ⁴⁷ = (111001) ^T ,
γ ⁴⁸ = (101100) ^T , γ ⁴⁹ = (010110) ^T , γ ⁵⁰ = (001011) ^T ,
γ ⁵¹ = (110101) ^T , γ ⁵² = (101010) ^T , γ ⁵³ = (010101) ^T ,
γ ⁵⁴ = (1111010) ^T , γ ⁵⁵ = (011101) ^T , γ ⁵⁶ = (111110) ^T ,
γ ⁵⁷ = (011111) ^T , γ ⁵⁸ = (111111) ^T , γ ⁵⁹ = (101111) ^T ,
γ ⁶⁰ = (100111) ^T , γ ⁶¹ = (1000011) ^T , γ ⁶² = (100001) ^T

From this, the matrix H ″ shown in Equation 26 can be expressed as H ″ = [γ ⁰ γ ¹ γ ² γ ³ γ ⁴ γ ⁵ γ ¹⁸ γ ²⁰ ]. Therefore, the parity check matrix (H) shown in Equation 1 can be used to construct a specific (504, 478) D _2/8 EC code using H ′ and H ″. FIG. 3 shows a parity check matrix of the (90, 64) D _2/8 EC code obtained by deleting 414 columns from.

  In addition, as shown in FIG. 3, in order to clarify the location of the row unit corresponding to H ′ and H ″ of the parity check matrix (H), a solid line is drawn at the boundary.

Now, it is specifically confirmed whether γ ³ H ″ that is a component of the parity check matrix (H) corresponds to the actual bit value shown in FIG. 3. As described above, H ″ = [γ ⁰ From γ ¹ γ ² γ ³ γ ⁴ γ ⁵ γ ¹⁸ γ ²⁰ ], γ ³ H ″ = γ ³ [γ ⁰ γ ¹ γ ² γ ³ γ ⁴ γ ⁵ γ ¹⁸ γ ²⁰ ] = [γ ³ γ ⁴ γ ⁵ γ ⁶ γ ⁷ γ ⁸ γ ²¹ γ ²³ ] If this power display is converted into a vector display (for example, γ ⁰ = (100,000) ^T, etc.), it corresponds to a part shown in FIG. Is clearly the γ ³ H ″ portion of the parity check matrix (H). Similarly, if the other components in the parity check matrix (H) are also converted to vector representation, the overall configuration is 26 rows by 90 columns in the bit representation shown in FIG.

より、行列Ｈ”として、ランク６を有し、また、符号長８ビットを有する６ビット誤り検出符号の検査行列を構成すればよい。この一例として、下記数２７に示す７×８行列を構成することができる。 Here, for t = 3, from Min ((d−1) t, b) = 8, as matrix H ′, 8 × 8 (8 rows × 8 columns) having rank 8 shown in Equation 25 above. Meaning) A unit matrix may be constructed. Also,

Thus, a check matrix of a 6-bit error detection code having rank 6 and a code length of 8 bits may be configured as the matrix H ″. As an example of this, a 7 × 8 matrix represented by the following Equation 27 is configured. can do.

一方、ｔ＝４、５、６、７については、Ｈ’及びＨ”は８×８の単位行列に等しくなり、パリティ検査行列（Ｈ）は、ＲＳ符号のパリティ検査行列と一致する。

On the other hand, for t = 4, 5, 6, and 7, H ′ and H ″ are equal to an 8 × 8 unit matrix, and the parity check matrix (H) matches the parity check matrix of the RS code.

In the above description, an example of a parity check matrix H (code) has been described for the semiconductor memory device having the most recently used byte width b = 8 bits input / output. A D _{t / b} EC code can be configured for a multi-bit input / output element, for example, an element having b = 16 bit input / output, and for b having an arbitrary integer value of 2 or more. Is clear.

  In the above description, an example of the parity check matrix H is configured with the distance d = 5. However, it is also clear that a code, that is, a parity check matrix can be configured for an arbitrary distance d.

  Thus, in the above description, an example of the configuration method of the parity check matrix (H) of the intra-byte multiple spotty byte error control codes has been described. The ranks of H ′ and H ″ in the parity check matrix (H) are expressed as follows. By changing it, it is possible to configure a code for controlling a plurality of spotty byte errors in two types of bytes having different sizes.

  Here, four types of in-byte multiple spotty byte error control codes taking into account two types of spotty byte errors (t / b error and t ′ / b error, 1 ≦ t, t ′ ≦ b) having different sizes. Will be described.

Specifically, the four types of intra-byte multiple spotty byte error control codes are as follows.
<I> S _{t / b} EC− (S _{t / b} + S _{t ′ / b} ) ED code That is, one t / b error is corrected, and (t / b + t ′ / b) error (t / b This is a code for detecting a combined error of an error and a t ′ / b error.
<II> _{St / b} EC-D _{t ′ / b} ED code In other words, this is a code that corrects one t / b error and detects two t ′ / b errors.
<III> (S _{t / b} + S _{t ′ / b} ) EC code That is, (t / b + t ′ / b) is a code for correcting an error.
<IV> D _{t / b} EC-S _{t ′ / b} EC code That is, a code that corrects two t / b errors and corrects one t ′ / b error (t <t ′). is there.

Here, the above four types of intra-byte multiple spotty byte error control taking into account two types of spotty byte errors of different sizes (t / b error and t ′ / b error, 1 ≦ t, t ′ ≦ b) The symbols are described in detail as follows.
<I> S _{t / b} EC- (S _{t / b} + S _{t '/ b} ) ED code St _{t / b} EC- (S _{t / b} + S _{t' / b} ) Parity having R rows and N columns used for the ED code The check matrix (H) is configured as shown in the following equation (28).

ただし、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、Ｎ＝ｂ（ｎ＋１）＋Ｒ−ｑ、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／２}−１である。

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) /} 2−1. is there.

The matrix H ′ constituting the equation 28 is a q-row b-column (q ≦ b) binary matrix composed of q-order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following equation 29. And has a rank equal to or larger than 2t + t ′ or b, whichever is smaller. That is, Rank (H ′) ≧ Min (2t + t ′, b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが２ｔ＋ｔ’＜ｂのとき、行列Ｈ’は最小ハミング距離２ｔ＋ｔ’＋１を有する符号の検査行列、すなわち、２ｔ＋ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a b × b unit matrix), and the rank of the matrix H ′ is 2t + t ′ <b. , Matrix H ′ is equal to a parity check matrix of a code having a minimum Hamming distance 2t + t ′ + 1, ie, a (b, b−q) code having a 2t + t ′ bit error detection function.

In addition, the matrix H ″ constituting the equation 28 is 2 in r rows and b columns (r ≦ b) composed of r-order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in the following equation 30. It is an original matrix and has a rank equal to or larger than t or t ′, whichever is larger. That is, Rank (H ″) ≧ Max (t, t ′) is satisfied.

ここで、行列Ｈ”のランクがｔ＞ｔ’のとき、行列Ｈ”は最小ハミング距離ｔ＋１を有する符号の検査行列、すなわち、ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。また、行列Ｈ”のランクがｔ＜ｔ’のとき、行列Ｈ”は最小ハミング距離ｔ’＋１を有する符号の検査行列、すなわち、ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is t> t ′, the matrix H ″ is a parity check matrix of a code having a minimum Hamming distance t + 1, that is, a parity of a (b, bq) code having a t-bit error detection function. Equal to the check matrix. When the rank of the matrix H ″ is t <t ′, the matrix H ″ is a check matrix of a code having the minimum Hamming distance t ′ + 1, that is, a (b, bq) code having a t′-bit error detection function. Equal to the parity check matrix.

Next, R ≧ q + 2r, and (Rq) is a multiple of 2, and γ is 2 as the base of (Rq) / 2-order extension GF (2 ^{(Rq) / 2} ) When the primitive element is used, γ ⁱ H ″ can be defined by the following Equation 31.

ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）である。

Here, Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) under addition.

Next, the code represented by the parity check matrix (H) shown in Equation 28 corrects one t / b error and (t / b + t ′ / b) error (that is, t / b). It shows concretely that it has a function of detecting a combined error of an error and a t ′ / b error. It suffices to show that the parity check matrix H = [H ₀ , H ₁ ,..., H _n−1 ] satisfies the necessary and sufficient conditions shown below. Here, H _i is a small matrix of R × b.

ここで、Ｅ_ｔ／ｂを１バイト中のｔビットまでの誤りの集合とし、Ｅ_ｔ’／ｂを１バイト中のｔ’ビットまでの誤りの集合とする。また、ｉ、ｊ、ｋ（０≦ｉ、ｊ、ｋ≦ｎ−１）は、すべて異なるものとする。

Here, E _{t / b} is a set of errors up to t bits in one byte, and E _{t ′ / b} is a set of errors up to t ′ bits in one byte. Also, i, j, k (0 ≦ i, j, k ≦ n−1) are all different.

Similar to the necessary and sufficient conditions shown in the above formulas 9, 10, and 11, it can be shown that the conditions shown in the formulas 32 to 35 are satisfied.

<II> S _{t / b} EC-D _{t ′ / b} ED code The parity check matrix (H) having R rows and N columns used for the _{St / b} EC-D _{t ′ / b} ED code is shown in the following Expression 36. The structure is as follows.

ただし、Ｒ≧ｑ＋２ｒ、かつ（Ｒ−ｑ）は２の倍数であり、Ｎ＝ｂ（ｎ＋１）＋Ｒ−ｑ、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／２}−１である。

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) /} 2−1. is there.

The matrix H ′ constituting the above Expression 36 is a q-by-b column (q ≦ b) binary matrix composed of q-order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following Expression 37. And has a rank equal to or larger than 2t or t + 2t ′, whichever is greater, and b, whichever is smaller. That is, Rank (H ′) ≧ Min (Max (2t, t + 2t ′), b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが２ｔのとき、行列Ｈ’は最小ハミング距離２ｔ＋１を有する符号の検査行列、すなわち、２ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。また、行列Ｈ’のランクがｔ＋２ｔ’のとき、行列Ｈ’は最小ハミング距離ｔ＋２ｔ’＋１を有する符号の検査行列、すなわち、ｔ＋２ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a unit matrix of b × b), and when the rank of the matrix H ′ is 2t, the matrix H 'Is equal to a parity check matrix of a code having a minimum Hamming distance 2t + 1, that is, a (b, bq) code having a 2t bit error detection function. When the rank of the matrix H ′ is t + 2t ′, the matrix H ′ is a parity check matrix of a code having a minimum Hamming distance t + 2t ′ + 1, that is, a parity of a (b, bq) code having a t + 2t ′ bit error detection function. Equal to the check matrix.

In addition, the matrix H ″ constituting the equation 36 is an r-by-b column (r ≦ b) 2 composed of r-order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in the following equation 38. It is an original matrix and has a rank equal to or larger than t or t ′, whichever is larger. That is, Rank (H ″) ≧ Max (t, t ′) is satisfied.

ここで、行列Ｈ”のランクがｔ＞ｔ’のとき、行列Ｈ”は最小ハミング距離ｔ＋１を有する符号の検査行列、すなわち、ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。また、行列Ｈ”のランクがｔ＜ｔ’のとき、行列Ｈ”は最小ハミング距離ｔ’＋１を有する符号の検査行列、すなわち、ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is t> t ′, the matrix H ″ is a parity check matrix of a code having a minimum Hamming distance t + 1, that is, a parity of a (b, bq) code having a t-bit error detection function. Equal to the check matrix. When the rank of the matrix H ″ is t <t ′, the matrix H ″ is a check matrix of a code having the minimum Hamming distance t ′ + 1, that is, a (b, bq) code having a t′-bit error detection function. Equal to the parity check matrix.

Next, R ≧ q + 2r, and (Rq) is a multiple of 2, and γ is 2 as the base of (Rq) / 2-order extension GF (2 ^{(Rq) / 2} ) When the primitive element is used, γ ⁱ H ″ can be defined by the following equation (39).

ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／２}）への準同型写像（homomorphism）である。

Here, Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) under addition.

Next, the code represented by the parity check matrix (H) shown in Equation 36 has a function of correcting one t / b error and detecting two t ′ / b errors. It shows concretely. It suffices to show that the parity check matrix H = [H ₀ , H ₁ ,..., H _n−1 ] satisfies the necessary and sufficient conditions shown below. Here, H _i is a small matrix of R × b.

ここで、Ｅ_ｔ／ｂを１バイト中のｔビットまでの誤りの集合とし、Ｅ_ｔ’／ｂを１バイト中のｔ’ビットまでの誤りの集合とする。また、ｉ、ｊ、ｋ（０≦ｉ、ｊ、ｋ≦ｎ−１）は、すべて異なるものとする。

Here, E _{t / b} is a set of errors up to t bits in one byte, and E _{t ′ / b} is a set of errors up to t ′ bits in one byte. Also, i, j, k (0 ≦ i, j, k ≦ n−1) are all different.

Similar to the necessary and sufficient conditions shown in the above formulas 9, 10, and 11, it can be shown that the conditions shown in the formulas 40 to 45 are satisfied.

<III> (S _{t / b} + S _{t ′ / b} ) EC code (S _{t / b} + S _{t ′ / b} ) The parity check matrix (H) having R rows and N columns used for the EC code is shown in the following Expression 46. The structure is as follows. Here, it is assumed that t> t ′ without losing generality.

ただし、Ｒ≧ｑ＋３ｒ、かつ（Ｒ−ｑ）は３の倍数であり、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／３、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／３}−１である。

However, R ≧ q + 3r and (Rq) is a multiple of 3, N = b (n + 1) + (Rq) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) /} 3-1.

The matrix H ′ constituting the above equation 46 is a binary matrix of q rows and b columns (q ≦ b) composed of q-order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following equation 47. And has a rank equal to or larger than 2t + 2t ′ or b, whichever is smaller. That is, Rank (H ′) ≧ Min (2t + 2t ′, b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが２ｔ＋２ｔ’＜ｂのとき、行列Ｈ’は最小ハミング距離２ｔ＋２ｔ’＋１を有する符号の検査行列、すなわち、２ｔ＋２ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a unit matrix of b × b), and the rank of the matrix H ′ is 2t + 2t ′ <b. , Matrix H ′ is equal to a parity check matrix of a code having a minimum Hamming distance 2t + 2t ′ + 1, that is, a (b, b−q) code having a 2t + 2t ′ bit error detection function.

In addition, the matrix H ″ constituting the above equation 46 is 2 in r rows and b columns (r ≦ b) composed of r-order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in the following equation 48. It is an original matrix and has a rank equal to or larger than t + t ′ or b, whichever is smaller. That is, Rank (H ″) ≧ Min (t + t ′, b) is satisfied.

ここで、行列Ｈ”のランクがｂに等しいとき、行列Ｈ”はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ”のランクがｔ＋ｔ’＜ｂのとき、行列Ｈ”は最小ハミング距離ｔ＋ｔ’＋１を有する符号の検査行列、すなわち、ｔ＋ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b (for example, a b × b unit matrix), and the rank of the matrix H ″ is t + t ′ <b. , Matrix H ″ is equal to a parity check matrix of a code having a minimum Hamming distance t + t ′ + 1, ie, a (b, b−q) code having a t + t ′ bit error detection function.

Next, R ≧ q + 3r, and (Rq) is a multiple of 3, and γ is 2 as the base (Rq) / 3-order expansion GF (2 ^{(Rq) / 3} ) Γ ⁱ H ″ can be defined by Equation 49 below.

ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／３}）への準同型写像（homomorphism）である。

Here, Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / 3} ) under addition.

Next, it is specifically shown that the code represented by the parity check matrix (H) shown in the above equation 46 has a function of correcting (t / b + t ′ / b) error. It suffices to show that the parity check matrix H = [H ₀ , H ₁ ,..., H _n−1 ] satisfies the necessary and sufficient conditions shown below. Here, H _i is a small matrix of R × b.

ここで、Ｅ_ｔ／ｂを１バイト中のｔビットまでの誤りの集合とし、Ｅ_ｔ’／ｂを１バイト中のｔ’ビットまでの誤りの集合とする。また、

はすべて異なるものとする。

Here, E _{t / b} is a set of errors up to t bits in one byte, and E _{t ′ / b} is a set of errors up to t ′ bits in one byte. Also,

Are all different.

Similar to the necessary and sufficient conditions shown in the above equations 9, 10, and 11, it can be shown that the conditions shown in the equations 50 through 58 are satisfied.

<IV> D _{t / b} EC-S _{t ′ / b} EC code D _{t / b} EC-S _{t ′ / b} Parity check matrix (H) having R rows and N columns used for the EC code is shown in the following Expression 59. The structure is as follows. Here, since the D _{t / b} EC code has a function of correcting an error of up to 2t bits generated in one byte, t ′> 2t.

ただし、Ｒ≧ｑ＋３ｒ、かつ（Ｒ−ｑ）は３の倍数であり、Ｎ＝ｂ（ｎ＋１）＋（Ｒ−ｑ）／３、０≦ｉ≦ｎ−１、ｎ＝２^{（Ｒ−ｑ）／３}−１である。

However, R ≧ q + 3r and (Rq) is a multiple of 3, N = b (n + 1) + (Rq) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) /} 3-1.

The matrix H ′ constituting the equation 59 is a q-by-b binary matrix (q ≦ b) composed of q-th order column vectors h _j ′ (0 ≦ j ≦ b−1) shown in the following equation 60. And has a rank equal to or greater than the larger value of 4t or 2t ′ and the smaller value of b. That is, Rank (H ′) ≧ Min (Max (4t, 2t ′), b) is satisfied.

ここで、行列Ｈ’のランクがｂに等しいとき、行列Ｈ’はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ’のランクが４ｔのとき、行列Ｈ’は最小ハミング距離４ｔ＋１を有する符号の検査行列、すなわち、４ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。また、行列Ｈ’のランクが２ｔ’のとき、行列Ｈ’は最小ハミング距離２ｔ’＋１を有する符号の検査行列、すなわち、２ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b (for example, a unit matrix of b × b), and when the rank of the matrix H ′ is 4t, the matrix H ′ 'Is equal to a parity check matrix of a code having a minimum Hamming distance 4t + 1, that is, a (b, b-q) code having a 4t bit error detection function. When the rank of the matrix H ′ is 2t ′, the matrix H ′ is a parity check matrix of a code having a minimum Hamming distance 2t ′ + 1, that is, a parity of a (b, bq) code having a 2t ′ bit error detection function. Equal to the check matrix.

Further, the matrix H ″ constituting the above equation 59 is an r-th row and b-column (r ≦ b) 2 which is composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1) shown in the following equation 61. It is an original matrix and has a rank equal to or larger than the larger value of 2t or t ′ and the smaller value of b. That is, Rank (H ″) ≧ Min (Max (2t, t ′), b) is satisfied.

ここで、行列Ｈ”のランクがｂに等しいとき、行列Ｈ”はランクｂのｂ×ｂ行列（例えば、ｂ×ｂの単位行列）であり、行列Ｈ”のランクが２ｔのとき、行列Ｈ”は最小ハミング距離２ｔ＋１を有する符号の検査行列、すなわち、２ｔビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。また、行列Ｈ”のランクがｔ’のとき、行列Ｈ”は最小ハミング距離ｔ’＋１を有する符号の検査行列、すなわち、ｔ’ビット誤り検出機能を有する（ｂ、ｂ−ｑ）符号のパリティ検査行列に等しい。

Here, when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b (eg, a b × b unit matrix), and when the rank of the matrix H ″ is 2t, the matrix H "Is equal to a parity check matrix of a code having a minimum Hamming distance 2t + 1, that is, a (b, b-q) code having a 2t bit error detection function. When the rank of the matrix H ″ is t ′, the matrix H ″ is a parity check matrix of a code having a minimum Hamming distance t ′ + 1, that is, a parity of a (b, bq) code having a t′-bit error detection function. Equal to the check matrix.

Then, a multiple of R ≧ q + 3r, and (R-q) is 3, the base 2 to the γ of the (R-q) / 3-order extension field ^{GF (2 (R-q)} / 3) When the primitive element is used, γ ⁱ H ″ can be defined by Equation 62 below.

ここで、Φは加法のもとでＧＦ（２^ｑ）からＧＦ（２^{（Ｒ−ｑ）／３}）への準同型写像（homomorphism）である。

Here, Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / 3} ) under addition.

Next, the code represented by the parity check matrix (H) shown in Equation 59 corrects two t / b errors and corrects one t ′ / b error (t <t ′). It shows concretely that it has the function to do. It suffices to show that the parity check matrix H = [H ₀ , H ₁ ,..., H _n−1 ] satisfies the necessary and sufficient conditions shown below. Here, H _i is a small matrix of R × b.

ここで、Ｅ_ｔ／ｂを１バイト中のｔビットまでの誤りの集合とし、Ｅ_ｔ’／ｂを１バイト中のｔ’ビットまでの誤りの集合とする。また、

はすべて異なるものとする。

Here, E _{t / b} is a set of errors up to t bits in one byte, and E _{t ′ / b} is a set of errors up to t ′ bits in one byte. Also,

Are all different.

  Similar to the necessary and sufficient conditions shown in the above formulas 9, 10, and 11, it can be shown that the conditions shown in the formulas 63 to 67 are satisfied.

As described above, in the above, some examples of the configuration method of the parity check matrix (H) of the intra-byte multiple spotty byte error control codes are shown. Next, using this parity check matrix (H), The specific encoding and decoding methods to be processed and the respective circuit configurations will be described by taking the intra-byte multiple spotty byte error control code shown in Equation 1 as an example.

<A> Encoding Method and Circuit Configuration for Realizing This First, an encoding method performed by the encoding circuit 2 shown in FIG. 1 will be described.

Encoding circuit 2 includes an input information data D (row vector) 30, by using the information part H _R of the parity check matrix shown in FIG. 3 (H) a parity check matrix obtained by base line variations (H), Inspection information C (row vector) is generated. The generation of the inspection information (C) can be obtained by the following equation 68.

具体的には、符号化回路２は、入力情報データ（Ｄ）３０の情報ビット長６４ビット及び検査ビット長２６ビットを基に、パリティ検査行列Ｈである（５０４、４７８）Ｄ_２／８ＥＣ符号を構成した後に、後半４１４ビットに相当する列ベクトル４１４列を削除することにより、符号ビット長９０ビット、情報長６４ビットを有する図３に示す（９０、６４）Ｄ_２／８ＥＣ符号が構成することができる。この符号のパリティ検査行列Ｈを基本行変形すると、組織符号としてのパリティ検査行列Ｈを構成することができる。図４は、（９０、６４）Ｄ_２／８ＥＣ組織符号のパリティ検査行列を示している。

Specifically, the encoding circuit 2 is a parity check matrix H based on the information bit length 64 bits and the check bit length 26 bits of the input information data (D) 30 (504, 478) D _2/8 EC. After constructing the code, by deleting the column vector 414 columns corresponding to the latter 414 bits, the (90, 64) D _2/8 EC code shown in FIG. 3 having a code bit length of 90 bits and an information length of 64 bits is obtained. Can be configured. When the parity check matrix H of this code is transformed into a basic row, a parity check matrix H as a systematic code can be configured. FIG. 4 shows a parity check matrix of the (90, 64) D _2/8 EC system code.

In the parity check matrix of the (90, 64) D _2/8 EC systematic code shown in FIG. 4, d _{0 to} d ₆₃ correspond to information bits, and c _{0 to} c ₂₅ correspond to check bits. Here, in the parity check matrix of the (90, 64) D _2/8 EC systematic code shown in FIG. 4, a matrix in which column vectors of d ₀ to d ₆₃ corresponding to information bits are collected is an information part of the parity check matrix. the H _R.

  Here, the parity check matrix shown in FIG. 4 is used for encoding, and the parity check matrix shown in FIG. 3 is used for decoding. The matrix obtained by transforming the basic row is equivalent to the original matrix, and the code represented by the parity check matrix shown in FIG. 4 includes the code represented by the parity check matrix shown in FIG. Does not change at all. Therefore, in the encoding, the parity check matrix shown in FIG. 4 is used.

Next, the encoding circuit 2 generates 26-bit inspection information (C) based on the above formula 68. As apparent from C = D · H _R ^T shown in the above equation 68, for example, in order to generate the check bit c ₀ in the check information (C), (90, 64) D ₂ for encoding shown in FIG. _{/ 8 In} the first row of the EC code matrix, except for the bit corresponding to c ₀ , the sum of the bits corresponding to the location where “1” exists on GF (2) (ie, the sum modulo 2: An operation taking mod2) may be performed.

For example, when the check bit c ₀ is obtained, “1” is present except for the bit corresponding to c ₀ because d ₁ , d ₄ , d ₅ , d ₆ , d ₈ , d ₁₁ , d _{12, d 20, d 21,} d 24, d 26, d 31, d 33, d 37, d 38, d 39, d 40, d 41, d 42, d 43, d 44, d 47, d 48, d ₅₂ , d ₅₄ , d ₅₅ , d ₅₆ , d ₅₇ , and d _{58. For} these 29 bits, a sum modulo 2 (mod 2) may be taken.

In order to realize this, as shown in FIG. 5, the 29 bits may constitute the multi-input parity check circuit 20 (0), and the output of the multi-input parity check circuit 20 (0) is the check bit c _0. It becomes. Other check bits c _{1 to} c ₂₅ can be generated in the same manner as the check bit c ₀ . The upper 14 bit configuration of 26-bit check bits _c 0 _{to c} encoding circuit 2 the ₂₅ generating in parallel (made from the multi-input parity check circuit 20 (0) 20 (25)) in FIG. 5, lower 12 Each bit configuration is shown in FIG.

  Next, a code word in which the inspection information (C) generated by the encoding circuit 2 is added to the input information data (D) 30 is represented by the following expression 69. This is the transmission word (V) (90-bit vector) sent to the circuit 3.

＜Ｂ＞復号の方法及びこれを実現する回路の構成について
次に、送信語（Ｖ）３１に誤りが生じたとき（すなわち受信語３２に誤りが含まれているとき）に、その誤りに対する訂正・検出処理が、図３に示す（９０、６４）Ｄ_２／８ＥＣ符号を用いて生成されるシンドローム（Ｓ）３３の値に基づいて可能なことを示す。

<B> Decoding method and circuit configuration for realizing the same Next, when an error occurs in the transmission word (V) 31 (that is, when the reception word 32 includes an error), the error is corrected. The detection process is possible based on the value of the syndrome (S) 33 generated using the (90, 64) D _2/8 EC code shown in FIG.

The check matrix of the (90, 64) D _2/8 EC code shown in FIG. 3 has a distance d = 5, and thus has a four-stage configuration with a parity check matrix H ′ as shown in the above equation (1). Thus, the q = 8-bit syndrome obtained from the first stage is S _I , the r = 6-bit syndrome obtained from the second stage is S _II , and the r = 6 bit syndrome obtained from the third stage is S _III the r = 6 bits of the syndrome obtained from the fourth stage and S _IV.

  Using these pieces of information, errors are corrected and detected as follows. From the received word (V ′) 32 and the parity check matrix (H), the syndrome (S) 33 can be obtained by the following equation (70).

ここで、Ｓ_I∈ＧＦ（２^ｑ）は、ｑ次の行ベクトルである。また、Ｓ_II、Ｓ_III、Ｓ_IV∈ＧＦ（２^ｒ）は、それぞれｒ次の行ベクトルである。

Here, S _I εGF (2 ^q ) is a q-th row vector. S _II , S _III , and S _IV εGF (2 ^r ) are r-th row vectors, respectively.

In the case of the decompression code shown in Equation 5, S _I εGF (2 ^q ) is a q-th row vector. S _II , S _III , and S _IV εGF (2 ^{(R−q) / 3} ) are (R−q) / 3 cubic row vectors, respectively.

Incidentally, syndrome (S) 33 for example, an error of i _I th byte e _I, when the error e _II to i _II-th byte occurs, the following Expression 71.

Ｓ_Iに注目すると、下記数７２が成り立つ。数７２において、Ｈ’はランクＭｉｎ（（ｄ−１）ｔ、ｂ）を有しているため、ｅ_I＋ｅ_II（＝ｅ_Ａとする）を求めることができる。図３に示す（９０、６４）Ｄ_２／８ＥＣ符号の場合に、Ｈ’は単位行列であるため、ｅ_Ａ＝ｅ_I＋ｅ_II＝Ｓ_Iとなる。

Focusing on S _I , the following equation 72 holds. In Formula 72, since H ′ has a rank Min ((d−1) t, b), e _I + e _II (= e _A can be obtained). In the case of the (90, 64) D _2/8 EC code shown in FIG. 3, since H ′ is a unit matrix, e _A = e _I + e _II = S _I.

次に、ｅ_I＋ｅ_IIにＨ”^Ｔを右から乗算し、乗算した結果をＳ’_I∈ＧＦ（２^ｒ）とする。つまり、下記数７３の関係が成立する。

Next, e _I + e _II is multiplied by H ″ ^T from the right, and the result of multiplication is S ′ _I ∈GF (2 ^r ).

ここで、ｅ_I・Ｈ”^Ｔ、ｅ_II・Ｈ”^Ｔ（∈ＧＦ（２^ｒ））をＧＦ（２^ｒ）上の誤りｅ’_I、ｅ’_IIとし、Ｓ’＝［Ｓ’_IＳ_IIＳ_IIIＳ_IV］とすると、下記数７４の関係が成り立つ。

Here, e _I · H ″ ^T and e _II · H ″ ^T (∈GF (2 ^r )) are set to errors e ′ _I and e ′ _II on GF (2 ^r ), and S ′ = [S ′ _I S _II S _III S _IV ], the following relationship 74 holds.

数７４に示すＳ’は、誤りｅ’_I、ｅ’_IIを有する距離ｄ＝５のＲＳ符号におけるシンドロームの式と一致する。よって、距離ｄ＝５を有するＧＦ（２^ｒ）上のＲＳ符号の復号法を用いることで、誤り位置ｉ_I、ｉ_II及びＧＦ（２^ｒ）上の誤りｅ’_I、ｅ’_IIを求めることができる。また、誤り位置が求まらない場合に、誤りの訂正が不可能として誤りを検出する。

S ′ shown in the equation 74 coincides with the syndrome equation in the RS code of distance d = 5 having errors e ′ _I and e ′ _II . Therefore, by using the decoding method of the RS code on GF (2 ^r ) having the distance d = 5, the error positions i _I and i _II and the errors e ′ _I and e ′ _II on GF (2 ^r ) are obtained. be able to. Further, when the error position cannot be obtained, the error is detected as the error cannot be corrected.

Next, the errors e _I and e _II on GF (2 ^b ) are obtained from the errors e ′ _I and e ′ _II on GF (2 ^r ). In the error e ′ on GF (2 ^r ) obtained by decoding the RS code, the case where the errors e ′ _I and e ′ _II are generated in 2 bytes and in the case of 1 byte is divided. .

When e ′ _I and e ′ _II occur in 2 bytes, one spotty byte error occurs in each byte. At this time, in e _I · H ″ ^T = e ′ _I and e _II · H ″ ^T = e ′ _II , H ″ has a rank of Min (2t, b) = (4, 8) = 4, and e _I Since e ′ _I and e _II → e ′ _II are injective relations, errors e _I and e _II on GF (2 ^b ) can be obtained.

In addition, when e ′ _I and e ′ _II occur in one byte, one or two spotty byte errors occur in one byte. At this time, since e _A = e _I + e _II obtained from the equation 73 becomes an error, an error can also be obtained.

Note that an error e ′ on GF (2 ^r ) obtained by decoding the RS code is also obtained for a general distance d, that is, an arbitrary predetermined distance d, as in the case of the distance d = 5. in, by performing separation of cases by the number of bytes error has occurred, it is possible to determine the error in the GF (2 ^b).

  Decoding for an RS code can be realized using a parallel decoding method for a code with a small distance d. The general configuration of this parallel decoding method is disclosed in “Burst Error Generation Method and Burst and Byte Error Detection / Correction Device” (see Patent Document 4).

  However, although the parallel decoding method disclosed in Patent Document 4 can perform high-speed decoding, there is a problem that the circuit amount increases as the code distance d increases. For a code with a large distance d, for example, a sequential decoding method such as the Burlekamp-Massy method can be used. However, since the decoding by the sequential decoding method is performed serially, there is a problem that the decoding is slow. Arise. The configuration of the RS code decoding circuit using the Balecamp Massi method is disclosed in Non-Patent Document 11.

  According to the parallel decoding method disclosed in Patent Document 4, for example, a code of d = 5 is decoded by the following procedure.

に対し、Ｒ×２ｒの行列

を構成する。ただし、

はＲ×ｒの小行列である。 First, the parity check matrix of the RS code

R × 2r matrix

Configure. However,

Is an R × r submatrix.

にＲ×（Ｒ−２ｒ）の行列Ｂ_{（ｉ，ｊ）}を付加し、Ｒ×Ｒの正則行列

を構成する。 Then this matrix

R × (R−2r) matrix B _{(i, j)} is added to R × R regular matrix

Configure.

を求めると、下記数７５の関係が成り立つ。 And the inverse matrix of A _{(i, j)}

Is obtained, the following formula 75 is established.

ここで、

はｒ×Ｒの行列であり、

となる。ただし、

はｒ×ｒの単位行列である。また、

はｒ×Ｒの行列であり、

となる。また、

は２ｒ×Ｒの行列であり、

となる。ただし、

は２ｒ×２ｒの単位行列である。また、

は２ｒ×Ｒの行列であり、

となる。

here,

Is an r × R matrix,

It becomes. However,

Is an r × r unit matrix. Also,

Is an r × R matrix,

It becomes. Also,

Is a 2r × R matrix,

It becomes. However,

Is a 2r × 2r unit matrix. Also,

Is a 2r × R matrix,

It becomes.

に対し、

となるバイト位置ｉ，ｊが誤りの位置ｉ_I、ｉ_IIとなり、

が誤りの大きさｅ’_I、ｅ’_IIとなる。これから、２バイトの誤りを訂正することができる。また、

となるバイト位置ｉ，ｊが存在しない場合に、誤りの訂正が不可能として誤りを検出する。 Said

Whereas

Become byte positions i, j is the position i _I error, i _II, and the

Becomes the error magnitudes e ′ _I and e ′ _II . From this, a 2-byte error can be corrected. Also,

When there is no byte position i, j, the error is detected as being uncorrectable.

  Next, FIG. 7 shows a schematic configuration of the decoding circuit 4 for realizing the parallel decoding method for the above-mentioned code of d = 5 in the present invention.

  As shown in FIG. 1, the decoding circuit 4 includes a syndrome generation circuit 1 and an error correction circuit 5.

Further, as shown in FIG. 7, the error correction circuit 5 includes an H ′ decoding circuit 6, an H ″ multiplication circuit 7, a parallel decoding circuit 8 on GF (2 ^r ), and an error on GF (2 ^b ). The generating circuit 9 and the inverting circuit 10 are included.

Here, the H ′ decoding circuit 6 generates an error sum (e _A ) 38 for each byte based on the upper q bits S _I 36 of the syndrome (S) 33.

Also, the H ″ multiplier circuit 7 is based on the product of the upper q bits S _I 36 of the syndrome (S) 33 and the transpose (H ″ ^T ) of H ″ based on the error sum (e _A ) 38 for each byte. generating a S _'I) 39.

Next, the parallel decoding circuit 8 on GF (2 ^r ) generates the product (S ′ _I ) 39 of the upper q bits S _I 36 of the syndrome (S) 33 and the transpose (H ″ ^T ) of H ″, and the syndrome ( based on the lower 3r bits S _II S _III S _IV 37 of ^{S) 33, GF (2 r} ) on the bit-error pointer (e ') 40, and GF (error correction in the ^{2 r)} parallel decoding on non A DS (0) (Detection Signal) 41 is generated that is output when it is deemed possible.

Then, the error generation circuit 9 on GF (2 ^b ) uses GF (2 ′) based on the error sum (e _A ) 38 for each byte and the bit error pointer (e ′) 40 on GF (2 ^r ). errors on the 2 ^r) is converted to an error on the GF ^{(2 b),} is output when a bit error pointer on ^{GF (2 b) (e)} 42, and error correction is deemed not DS (1) (Detection Signal) 43 is output.

Finally, the inverting circuit 10 inverts the bit value of the received word (V ′) 32 corresponding to the error bit based on the bit error pointer (e) 42 on GF (2 ^b ), thereby receiving the received word. (V ′) 32 errors are corrected.

  Next, an outline of an operation procedure performed in the decoding circuit 4 shown in FIG. 7 will be described.

  First, the syndrome generation circuit 1 generates an R-bit syndrome (S) 33 when an N-bit received word (V ′) 32 is input.

Next, the generated R-bit syndrome (S) 33 is divided into upper q bits S _I 36 and lower 3r bits S _II S _III S _IV 37. The upper q bits S _I 36 of the syndrome (S) 33 are input to the H ′ decoding circuit 6. Further, the lower 3r bits S _II S _III S _IV 37 of the syndrome (S) 33 are inputted to the parallel decoding circuit 8 on GF (2 ^r ).

In the H ′ decoding circuit 6, as will be described in detail later, based on the upper q bits S _I 36 of the syndrome (S) 33 generated by the syndrome generation circuit 1, the sum of errors for each b-bit byte ( e _A ) 38 is output.

In the H ″ multiplier circuit 7, as will be described in detail later, the upper q bits S of the syndrome (S) 33 are based on the error sum (e _A ) 38 for each byte generated by the H ′ decoder circuit 6. The product (S ′ _I ) 39 of _I 36 and the transpose (H ″ ^T ) of H ″ is output.

ビットのＧＦ（２^ｒ）上のビット誤りポインタ

を生成する。ここで、

はｙを超える最小の整数を示す。また、ＧＦ（２^ｒ）上の並列復号回路８では、ＧＦ（２^ｒ）上の並列復号において、誤り訂正が不可能とみなされたときに、訂正不可能誤り検出信号（ＤＳ（０））４１を出力する。 Further, in the parallel decoding circuit 8 on GF (2 ^r ), as will be described in detail later, the upper q bits S _I 36 of the syndrome (S) 33 generated by the H ″ multiplier circuit 7 and the transposition (H ″) of H ″. ^{Based on} the product (S ′ _I ) 39 of ^T ) and the lower 3r bits S _II S _III S _IV 37 of the syndrome (S) 33 generated by the syndrome generation circuit 1, the error on GF (2 ^r ) Point out

Bit error pointer on bit GF ( ^2r )

Is generated. here,

Indicates the smallest integer exceeding y. Also, GF in parallel decoding circuit 8 on the ^{(2 r),} the parallel decoding on GF ^{(2 r),} when it is considered impossible error correction, uncorrectable error detection signal (DS (0)) 41 is output.

In the error generation circuit 9 on GF (2 ^b ), as will be described in detail later, the error sum (e _A ) 38 for each byte generated by the H ′ decoding circuit 6 and on the GF (2 ^r ) parallel decoding circuit 8-bit-error pointer on the generated GF ^{(2 r)} in (e ') 40 and based on the bit on GF ⁽² b) of the N bits to indicate errors in the GF ^{(2 b)} An error pointer e = (e ₀ , e ₁ ,..., E _N−1 ) 42 is generated. Further, the error generation circuit 9 on GF (2 ^b ) outputs an uncorrectable error detection signal (DS (1)) 43 when error correction is deemed impossible.

Then, the inverting circuit 10, GF ^{(2 b)} of the N bits generated by the error vector generating circuit 9 on GF ^{(2 b)} on the bit-error pointer (e) 42, and the received word a (V ') 32 Based on this, the bit of the received word (V ′) 32 corresponding to the bit error pointer (e) 42 on GF (2 ^b ) is inverted.

Finally, the inverting circuit 10 extracts a K-bit information word D ^* from the N-bit error-corrected received word V ^* and outputs it as output information data 34.

Further, the uncorrectable error detection signal (DS (0)) 41 generated by the parallel decoding circuit 8 on GF (2 ^r ) and the uncorrectable generated by the error generation circuit 9 on GF (2 ^b ). By calculating the logical sum of the error detection signal (DS (1)) 43, the value of the uncorrectable error detection signal UCE (Uncorrectable Error) 35 is output. For example, if the value of the uncorrectable error detection signal UCE35 is “1”, it indicates that an error exceeding the correction capability has been detected.

  It should be noted that the decoding method and circuit configuration of the decompression code shown in Formula 5 and the codes for controlling two types of intra-byte spotty byte errors having different sizes shown in Formula 28, Formula 36, Formula 46, and Formula 59 are also used. Is basically the same as described above.

Next, the syndrome generation circuit 1, the H ′ decoding circuit 6, the H ″ multiplication circuit 7, the parallel decoding circuit 8 on GF (2 ^r ), the error generation circuit 9 on GF (2 ^b ), and the inverting circuit 10 respectively. A specific configuration example will be described using the (90, 64) D _2/8 EC code shown in FIG.

<a> Configuration of Syndrome Generation Circuit 1 Here, the configuration of the syndrome generation circuit 1 will be described in detail.

First, in the syndrome generation circuit, when the received word (V ′) 32 composed of N = 90 (= 64 + 26) bits is expressed as shown in the following equation 76, the received word (V ′) 32 is input, _{S 0,} S 1 shown in the following Expression 77, _..., to generate the R = 26 bits of the syndrome (S) 33 consisting of _{S 25.}

As described above, since the parity check matrix of the D _2/8 EC code shown in FIG. 3 has a four-stage configuration, the syndrome (S) 33 is also divided into four parts correspondingly, and S _I = (S ₀ S ₁ S ₂ S ₃ S ₄ S ₅ S ₆ S ₇ ), S _II = (S ₈ S ₉ S ₁₀ S ₁₁ S ₁₂ S ₁₃ ), S _III = (S ₁₄ S ₁₅ S ₁₆ S ₁₇ S ₁₈ S ₁₉ ) and S _IV = (S ₂₀ S ₂₁ S ₂₂ S ₂₃ S ₂₄ S ₂₅ ).

上記数６８に示したように、シンドロームＳ＝Ｖ’・Ｈ^Ｔより、転置したパリティ検査行列（Ｈ^Ｔ）の各行は、入力する情報に対応し、例えば、行列（Ｈ^Ｔ）の第０行は、入力情報のｖ_０’に対応している。そこで、シンドローム（Ｓ）３３の各ビットを生成するには、符号であるパリティ検査行列（Ｈ^Ｔ）の各列方向に、“１”を有するビットに対応する受信語（Ｖ’）３２の受信情報をＧＦ（２）上で加算（ｍｏｄ２の計算）すればよい。

As shown in the above formula 68, from the syndrome S = V ′ · H ^T , each row of the transposed parity check matrix (H ^T ) corresponds to input information, for example, the 0th row of the matrix (H ^T ) Corresponds to v ₀ ′ of the input information. Therefore, in order to generate each bit of the syndrome (S) 33, reception of the received word (V ′) 32 corresponding to the bit having “1” in each column direction of the parity check matrix (H ^T ) that is a code. Information may be added on GF (2) (calculation of mod2).

8 and 9 are diagrams showing the syndrome generation circuit 1 configured based on the parity check matrix of the (90, 64) D _2/8 EC code shown in FIG. In Figure _{8, S 0, S 1,} ···, the upper 14 bits of the syndrome, such as _{S 13} (S) 33 Also, In FIG. _9, S _14, S 13, · · _·, such _{S 25} syndrome (S) 33 lower 12 bits are generated.

As shown in FIGS. 8 and 9, in this embodiment, in the syndrome generation circuit 1, first, 26 multi-input parity check circuits 21 (p), (p = 0, 1,..., 25) are provided. , Received information (v _q ′) having bit “1” in each corresponding row of the parity check matrix of the (90, 64) D _2/8 EC code shown in FIG. 3, (q = 0, 1,... , 89).

Next, in each multi-input parity check circuit 21 (p), (p = 0, 1,..., 25), the sum modulo 2 is applied to the input reception information (v _q ′). performs a calculation of (mod2), the result is _{S p.}

Specifically, for example, to generate a bit _{S 0} of syndrome (S) 33 90 bits of the received word _{v 0 ', v 1',} ···, of _{v 89} ', the parity check shown in FIG. 3 In the 0th row of the matrix, v ₀ ′, v ₈ ′, v ₁₆ ′, v ₂₄ ′, v ₃₂ ′, v ₄₀ ′, v ₄₈ ′, v ₅₆ ′, corresponding to the place where “1” exists, _{v 64 ', v 72',} v 80 ', v 88' for 12-bit, may take the sum (mod2) for modulo 2. Multi-input parity check circuit 21 of FIG. 8 (0) as inputs the received information of the 12 bits, and outputs a value S _0. Other bits _S p of the syndrome (S) 33, is the same for (p = 1, ···, 25 ).

<B> Configuration of H ′ Decoding Circuit 6 Next, the H ′ decoding circuit 6 will be described.

The H ′ decoding circuit 6 is shown in FIG. In (e _I + e _II ) · H ′ ^T = S _I shown in Equation 72, since H ′ has a rank Min ((d−1) t, b), e _I + e _II (= e _A ). Therefore, by using the fact that e _I + e _II → S _I is injective and performing logic synthesis, it can be realized by a combinational circuit.

Ｓ_I＝（Ｓ_０Ｓ_１Ｓ_２Ｓ_３Ｓ_４Ｓ_５Ｓ_６Ｓ_７）に対し、図１０に示すように、

となる。 In the case of the (90, 64) D _2/8 EC code shown in FIG. 3, since H ′ is a unit matrix, e _A = e _I + e _II = S _I. That is,

For S _I = (S ₀ S ₁ S ₂ S ₃ S ₄ S ₅ S ₆ S ₇ ), as shown in FIG.

It becomes.

On the other hand, when H ′ is not a unit matrix, the method described later in <e> is used.

<C> Configuration of H "Multiplication Circuit 7 Next, the H" multiplication circuit 7 will be described.

The H ″ multiplier circuit 7 is shown in FIG. 11. S ′ _I = (e _I + e _II ) · H ″ ^T = e _A · H ″ ^T shown in Equation 73 is calculated. Correspondence of H ″ shown in Equation 78 below E _A information having bit “1” in each row is input to the H ”multiplier circuit 7. The H” multiplier circuit 7 calculates mod2 for the input e _A information, The result is output as S ′ _p (p = 0, 1,..., 5).

具体的に、例えば、シンドローム（Ｓ）３３の上位ｑビットＳ_I３６とＨ”の転置（Ｈ”^Ｔ）の積（Ｓ’_I）３９のビットＳ’_０を生成するには、８ビットの

のうち、数７８に示すパリティ検査行列Ｈ”の第０行目において、“１”が存在する箇所に相当する２ビット

の値に対して、２を法とする和（ｍｏｄ２）をとればよい。

Specifically, for example, in order to generate the bit S ′ ₀ of the product (S ′ _I ) 39 of the transposition (H ″ ^T ) of the high-order q bit S _I 36 of the syndrome (S) 33 and H ″,

2 bits corresponding to the location where “1” exists in the 0th row of the parity check matrix H ”shown in Formula 78

For the value of, a sum modulo 2 (mod2) may be taken.

の値）が入力されて、値Ｓ’_０を出力していることを示している。 11, exclusive the OR circuit 22, the two bits of _{e A} information (that is, 2 bits

) Is input and the value S ′ ₀ is output.

Similarly, the exclusive OR circuit 22 and the other bits S ′ _p of the product (S ′ _I ) 39 of the transpose (H ″ ^T ) of H ″ with the upper q bits S _I 36 of the syndrome (S) 33 A three-input parity check circuit 23 can be used.

  Here, S ′ is configured as shown in Equation 79 below.

＜ｄ＞ＧＦ（２^６）上の並列復号回路８の構成
次に、ＧＦ（２^６）上の並列復号回路８について説明する。

Construction of <d> GF ^{(2 6)} on the parallel decoding circuit 8 will be described next parallel decoding circuit 8 over GF ^{(2 6).}

A parallel decoding method is used to find the bit error pointer 40 on GF (2 ⁶ ). FIG. 12 shows the overall configuration of the parallel decoding circuit 8 on GF (2 ⁶ ).

個を選び、ｉ、ｊ番目の２バイト（以下、（ｉ、ｊ）と表現することとする）に関する各々の誤りを生成する回路である（ｉ、ｊ）に対する誤り生成回路５０（０）・・・５０（６５）、（以下、代表として５０（ｍ）、０≦ｍ≦６５、と称する）と、ＧＦ（２^６）上のビット誤りポインタ（ｅ’）４０を出力するＧＦ（２^６）上の誤り算出回路５１とから構成されている。 As shown in FIG. 12, the parallel decoding circuit 8 on GF (2 ⁶ ) is a set of arbitrary 2 bytes in 12 bytes.

Error generation circuit 50 (0)... For (i, j), which is a circuit for generating each error for the i, j-th two bytes (hereinafter, expressed as (i, j)). .. 50 (65), (hereinafter represented as 50 (m), 0 ≦ m ≦ 65, and referred to) and, GF ^{(2 6)} GF ⁽² for outputting a bit error pointer (e ') 40 on ⁶ And the error calculation circuit 51 above.

を計算する回路である。要するに、（ｉ、ｊ）に対する誤り生成回路５０（０）〜５０（６５）は、符号語の１２バイト中のｉ、ｊ（０≦ｉ＜ｊ≦１１）番目のバイトに対する前述した

を計算し、Ｅ’_ｍ、ｉ、Ｅ’_ｍ、ｊになる誤り５２（ｍ）、０≦ｍ≦６５、０≦ｉ＜ｊ≦１１（それぞれｒビットのベクトル）、及び訂正可能信号５３（ｍ）、０≦ｍ≦６５、を出力する。 First, the error generation circuit 50 (m) for (i, j) has been described above for byte positions i, j.

Is a circuit for calculating In short, the error generation circuits 50 (0) to 50 (65) for (i, j) are as described above for the i, j (0 ≦ i <j ≦ 11) th byte in the 12 bytes of the codeword.

And an error 52 (m) that results in E ′ _{m, i} , E ′ _{m, j} , 0 ≦ m ≦ 65, 0 ≦ i <j ≦ 11 (respectively r-bit vectors), and a correctable signal 53 ( m), 0 ≦ m ≦ 65 is output.

The error calculating circuit 51 over GF ^{(2 6)} is a circuit for outputting the bit error pointer (e ') 40 over GF ^{(2 6).} In short, the error calculation circuit 51 on GF (2 ⁶ ) receives the errors E ′ _{m, i} , E ′ _{m, j} , which are the outputs of the error generation circuit 50 (m) _, and inputs the bits on GF (2 ⁶ ). An error pointer (e ′) 40 is output.

Here, the processing of the parallel decoding circuit 8 on GF (2 ⁶ ) will be described in more detail. As shown in FIG. 12, first, R = 24 bits S ′ (the upper q bits S _I of the syndrome (S) 33) 36 and H ″ transpose (H ″ ^T ) product (S ′ _I ) 39, and the lower 3r bits S _II S _III S _IV 37) of syndrome (S) 33, an error generation circuit 50 ( m).

Next, the error generation circuit 50 (m) for (i, j) generates errors E ′ _{m, i} , E ′ _{m, j} , and the generated errors E ′ _{m, i} , E ′ _{m, j} Is input to the error calculation circuit 51 on GF (2 ⁶ ). Next, the error calculating circuit on GF ^{(2 6)} 51 outputs the bit-error pointer (e ') 40 over GF ^{(2 6).}

Also, R = 24 bits of S ′ (the product (S ′ _I ) 39 of the upper q bits S _I 36 of the syndrome (S) 33 and the transpose (H ″ ^T ) of H ″, and the lower order of the syndrome (S) 33 The 3r bits S _II S _III S _IV 37) are input to the 24-bit input OR gate circuit 54.

  On the other hand, the correctable signal 53 (m) generated by the error generation circuit 50 (m) for (i, j) is input to the 66-input NOR gate circuit 55.

  Two signals respectively output from the 24-bit input OR gate circuit 54 and the 66-input NOR gate circuit 55 are input to the 2-input AND gate circuit 56. The 2-input AND gate circuit 56 outputs an uncorrectable error detection signal (DS (0)) 41. These circuits detect an error when the syndrome is non-zero and the correctable signal is all zero.

計算回路６０と、

計算回路６１と、

計算回路６２とを備える。 Next, a configuration example of the error generation circuit 50 (m) for (i, j) will be specifically shown. As an example, an error generation circuit 50 (0) for (0, 1) is shown in FIG. As shown in FIG. 13, the error generation circuit 50 (m) for (i, j)

A calculation circuit 60;

A calculation circuit 61;

And a calculation circuit 62.

は下記数８０に示すＧＦ（２^６）上のＲＳ符号の検査行列であり、符号長７２ビットと検査ビット長２４ビットとを有する。ただし、γはＧＦ（２^６）の元であり、下記数８１に示すように、生成多項式ｇ（ｘ）＝ｘ^６＋ｘ＋１で定義される２元の６×６随伴行列（companion matrix）で表現される。 here,

Is a check matrix of an RS code on GF (2 ⁶ ) shown in the following equation 80, and has a code length of 72 bits and a check bit length of 24 bits. However, gamma is the original GF ^{(2 6),} expressed in as shown in the following Expression 81, the generator polynomial ^{g (x) = x 6 +} x + 1 defined in the 2 original 6 × 6 adjoint (companion matrix) Is done.

例えば、（０、１）に対する誤り生成回路５０（０）では、

は、数８０の第１列、第２列に相当し、それぞれ下記数８２に示す２４×６行列となる。

For example, in the error generation circuit 50 (0) for (0, 1),

Corresponds to the first column and the second column of Formula 80, and is a 24 × 6 matrix shown in Formula 82 below.

次に、

から２４×１２の行列

を構成し、

に２４×１２の行列Ｂ_{（０，１）}を付加することにより、下記数８３に示す２４×２４の正則行列

を構成する。ここで、Ｂ_{（０，１）}はＡ_{（０，１）}が正則行列となるように求めた２４×１２の行列であり、一例である。

next,

24 × 12 matrix from

Configure

By adding a 24 × 12 matrix B _{(0, 1)} to the 24 × 24 regular matrix shown in the following equation 83

Configure. Here, B _(0,1) is a 24 × 12 matrix obtained so that A _(0,1) is a regular matrix, and is an example.

次に、Ａ_{（０，１）}の逆行列

を求めると、下記数８４の関係が成り立つ。

はそれぞれ下記数８５、数８６、数８７に示す行列となる。

Next, the inverse matrix of A _(0,1)

Is obtained, the following relationship 84 holds.

Are the matrices shown in the following equations 85, 86, and 87, respectively.

計算回路６０では、

の各列が入力する情報に対応し、例えば、

の第０行が入力情報のＳ’_０に対応している。そこで、

の各ビットを生成するには、

の各行方向に、“１”を有するビットに対応するシンドロームＳ’の情報をＧＦ（２）上で加算（ｍｏｄ２の計算）すればよい。

In the calculation circuit 60,

Corresponds to the information entered in each column, for example,

The 0th row corresponds to S ′ _{0 of the} input information. Therefore,

To generate each bit of

The information of the syndrome S ′ corresponding to the bit having “1” may be added on GF (2) (calculation of mod 2) in each row direction.

計算回路６０は、まず、前記

の対応する各行のビット“１”を有するシンドローム情報（Ｓ’_ｐ）、（ｐ＝０、１、・・・、２３）をそれぞれ６個の多入力パリティチェック回路６３（ｕ）、（ｕ＝０、１、・・・、５）に入力する。次に、これらのシンドローム情報についてｍｏｄ２の計算を行い、その結果をとしてＥ’_０、０、Ｅ’_０、１を出力する。 in short,

First, the calculation circuit 60

Syndrome information (S ′ _p ), (p = 0, 1,..., 23) having bit “1” of each corresponding row of six multi-input parity check circuits 63 (u), (u = 0, 1, ..., 5). Next, mod 2 is calculated for these syndrome information, and E ′ ₀ , ₀ , E ′ ₀ , ₁ are output as the result.

Specifically, for example, E 'to generate 0th bit of _0,0, 24-bit syndrome _{S' = S '0, S} ' 1, ···, of the S _'23, in the Expression 85 The value of 5 bits S ′ ₀ , S ′ ₅ , S ′ ₉ , S ′ ₂₁ , S ′ ₂₃ corresponding to the place where “1” exists in the 0th row of the parity check matrix shown is modulo 2. What is necessary is just to take the sum (mod2). The multi-input parity check circuit 63 (0) of FIG. 13 receives the syndromes of the 5 bits S ′ ₀ , S ′ ₅ , S ′ ₉ , S ′ ₂₁ , and S ′ ₂₃ . In addition, the multi-input parity check circuit 63 (0) outputs the 0th bit of _E′0 , 0 which is 52 (0). The same applies to the other bits of E ′ _0,0 .

計算回路６１は、６個の多入力パリティチェック回路６４（ｗ）、（ｗ＝０、１、・・・、５）で構成され、そして、

計算回路６２は、１２個の多入力パリティチェック回路６５（ｚ）、（ｚ＝０、１、・・・、１１）で構成される。これらの計算回路は、

計算回路６０と同様の方法で構成することができる。 Moreover, as shown in FIG.

The calculation circuit 61 includes six multi-input parity check circuits 64 (w), (w = 0, 1,..., 5), and

The calculation circuit 62 includes twelve multi-input parity check circuits 65 (z) (z = 0, 1,..., 11). These calculation circuits are

The calculation circuit 60 can be configured in the same way.

Here, the processing of the error generation circuit 50 (0) for (0, 1) will be described in more detail. As shown in FIG. 13, a 24-bit syndrome S ′ is converted into a multi-input parity check circuit 63 (u), (u). = 0, 1,..., 5) to generate E ′ ₀ , ₀ . Further, E ′ ₀ and ₁ are generated by inputting the 24-bit syndrome S ′ to the multi-input parity check circuit 64 (w) (w = 0, 1,..., 5).

となるバイトの組（ｉ、ｊ）が誤りのバイトの組であるため、

であることを検出し、バイトの組（ｉ、ｊ）で訂正可能であることを意味する。 Further, the 24-bit syndrome S ′ is input to the multi-input parity check circuit 65 (z) (z = 0, 1,..., 11). A 12-bit signal output from the multi-input parity check circuit 65 (z), (z = 0, 1,..., 11) is input to the 12-input NOR gate circuit 65, and (0, 1) can be corrected. The signal 53 (0) is output. These circuits are

Since the set of bytes (i, j) is the set of erroneous bytes,

This means that correction is possible with the byte set (i, j).

Further, the correctable signal 53 (0) for (0, 1) and the output signal from the multi-input parity check circuit 63 and multi-input parity check circuit 64 are input to the 2-input AND gate circuit 67, and E ′ _{0, 0} and E ' ₀ , ₁ are output. These circuits output an error if the set of bytes in which an error has occurred, and output a pattern of 0 otherwise.

From the above, the error generation circuit 50 (0) for (0, 1) receives the correctable signal 53 (0) for the errors E ′ ₀ , ₀ , E ′ _{0, 1} 52 (0), and (0, 1). Finally output. Here, the error generation circuit 50 (0) for (0, 1) has been described as an example, but the same applies to other bytes (i, j).

Next, a configuration example of the error calculation circuit 51 on GF (2 ⁶ ) is specifically shown. FIG. 14 shows an error calculation circuit 51 on GF (2 ⁶ ).

As shown in FIG. 14, the error calculation circuit 51 on GF (2 ⁶ ) inputs all the errors E ′ _{m, i} corresponding to the i-th byte to the OR operation circuit 68 bit by bit, and GF (2 ⁶⁾ on the bit-error pointer (e ') 40 and finally outputs. These circuits integrate the errors E ′ _{m, i} from the i-th corresponding byte set (i, j) and output the i-th error e _i ′.

Specifically, for example, to output e ′ ₆ of the bit error pointer (e ′) 40 on GF (2 ⁶ ), error generation circuits 50 (0), (1, 2) for (0, 1) , E ′ ₀ , ₁ , E ′ ₁₁ , ₁ ,..., E ′ ₂₀ output from the error generation circuit 50 (20) for (1, 11). It is obtained by inputting the 0th bit of ₁ to the bitwise OR operation circuit 68. The OR operation circuit 68 for each bit, E _{'0, 1,} E' with 6 bits _11,1, ..., by inputting 0-th bit of E _{'20, 1} to the respective 11 input OR circuit 69 , E ′ ₀ , ₁ , E ′ ₁₁ , ₁ ,..., E ′ ₁₉ , 1 are integrated to output e ₆ ′.

In the above description, e ′ ₆ of the bit error pointer (e ′) 40 on GF (2 ⁶ ) has been described as an example, but the other bit values e ′ ₀ ,..., E ′ ₆₅ are exactly the same. It is.

Configuration Next the error generation circuit 9 on ^{<e> GF (2 8)} , described error generation circuit 9 on the GF ^{(2 8).} FIG. 15 shows the overall configuration of the error generation circuit 9 on GF (2 ⁸ ).

As shown in FIG. 15, the error generation circuit 9 on GF (2 ⁸ ) includes an error byte detection circuit 70 that detects that the syndrome is non-zero, and a bit error pointer (e ′) on GF (2 ⁶ ). ) T-bit error correction decoding circuit 72 that outputs 1 byte of bit error pointer (e) 42 on GF (2 ⁸ ) from 1 byte of 40 and 12 bit-by-bit selection circuit 75 that selects an input signal, respectively. I have one by one. Further, in the case of a signal having a Hamming weight (number of 1s) of 1, a circuit 71 for detecting a Hamming weight 1 that outputs 1 is also provided.

Here, the error byte detection circuit 70 inputs 1 byte (6 bits) of the bit error pointer (e ′) 40 on GF (2 ⁶ ) and outputs a 1-bit syndrome detection signal. That is, 0 is output when all 6-bit inputs are 0, and 1 is output otherwise.

Further, the t-bit error correction decoding circuit (in this example, a 2-bit error correction decoding circuit) 72 receives the bit error pointer (e ′) 40 on GF (2 ⁶ ) as an input and starts from 1 byte to GF (2 ⁸ ). One byte of the upper bit error pointer (e) 42 is output. The t-bit error correction decoding circuit 72 also outputs a signal for detecting an error exceeding the correction capability.

  Then, the bit-by-bit selection circuit 75 selects each bit of the two signals each having 8 bits according to the control signal.

  Finally, the circuit 71 for detecting the Hamming weight 1 calculates the Hamming weight of the input signal, and outputs 1 when the Hamming weight is 1, and outputs 0 when it is not.

Here, the processing of the error generation circuit 9 on GF (2 ⁸ ) will be described in more detail. As shown in FIG. 15, the bit error pointer (e ′) 40 on GF (2 ⁶ ) is divided into 6 bits. Are input to the error byte detection circuit 70 and the 2-bit error correction decoding circuit 72, respectively.

  Next, the detection signal output from the error byte detection circuit 70 is input to the circuit 71 that detects the Hamming weight 1. The signal output from the circuit 71 for detecting the Hamming weight 1 and the detection signal output from the error byte detection circuit 70 are input to the 2-input AND gate circuit 73, respectively.

Then, the signal output from the 2-input AND gate circuit 73 is used as a control signal for the bit-by-bit selection circuit 75, and the bit-by-bit selection circuit 75 outputs the signal output from the 2-bit error correction decoding circuit 72 and the error for each byte. The sum (e _A ) 38 is selected according to this control signal. Collect the selected signals and output a bit error pointer 42 on 90 bits GF (2 ^b ).

  The detection signal output from the 2-bit error correction decoding circuit 72 is input to the 12-input OR gate circuit 74. The 12-input OR gate circuit 74 outputs an uncorrectable error detection signal (DS (1)) 43 based on the input detection signal.

Next, a configuration example of the error byte detection circuit 70 is specifically shown. As an example, FIG. 16 shows an error byte detection circuit 70 for the second byte of the bit error pointer (e ′) 40 on GF (2 ⁶ ).

As shown in FIG. 16, the error byte detecting circuit 70, GF ^{(2 6)} on the bit-error pointer (e ') 2 byte signal _{40 e' 6, e '7} , e' 8, e '9 _, E ′ _{10 and} e ′ ₁₁ are input to the 6-input OR gate circuit 80 to output a syndrome detection signal.

  Next, a configuration example of the circuit 71 for detecting the Hamming weight 1 is shown in FIG.

  As shown in FIG. 17, the circuit 71 that detects the Hamming weight 1 includes a 12-input sort circuit 81. The 12-input sort circuit 81 is a circuit that counts the weights (number of 1s) in the input 12-bit information, and continuously expresses 1 from the upper bits of the output by the number of the weights. For example, when there are six 1's in 12-bit input information, the upper 6 bits of the output 12 bits of this circuit all output 1 and the remaining 6 bits output all 0's.

  Here, the processing of the circuit 71 for detecting the Hamming weight 1 will be described in more detail. A 12-bit signal is input to a 12-input sort circuit 81 as shown in FIG. Of the signals output from the 12-input sort circuit 81, 11 bits excluding the upper 1 bit are input to the NOT gate circuit 82. Next, the high-order 1-bit signal output from the 12-input sort circuit 81 and the 11-bit signal output from the NOT gate circuit 82 are input to the 12-input AND gate circuit 83 to detect the Hamming weight 1. Output a signal.

  Next, a configuration example of the 12-input sort circuit 81 is shown in FIG. As shown in FIG. 18, 12-bit input information is sorted, and a 2-input 2-output circuit composed of a pair of 2-input OR gate circuit 84 and 2-input AND gate circuit 85 is used as a cell, and the input is 12 On the other hand, this cell is connected in multiple stages. This sort circuit is generally a circuit that outputs 1 to the upper x bits of n bits and outputs 0 to all the remaining outputs if there are x 1's in an n-bit input. The general configuration of this circuit is described in Non-Patent Document 12.

  As shown in FIG. 18, the 12-input sort circuit 81, which is a 12-input 12-output circuit, uses 39 cells (that is, 78 gates) and realizes a maximum of 12 cells (12 gate stages). Is possible. For example, when 12-bit input information is information of weight 6 such as (001011001011), the output is (111111000000000).

  Next, a configuration example of the 2-bit error correction decoding circuit 72 is specifically shown.

  As an example, FIG. 19 shows a circuit that outputs the upper 4 bits of the 2-bit error correction decoding circuit 72 for the second byte, and FIG. 20 shows a circuit that outputs the lower 4 bits of the 2-bit error correction decoding circuit 72 for the second byte. FIG. 21 shows a circuit for outputting a detection signal for outputting “1” when an error exceeds the correction capability.

The 2-bit error correction decoding circuit 72 receives the second byte of the bit error pointer (e ′) 40 on GF (2 ⁶ ) and receives the second byte of the bit error pointer (e) 42 on GF (2 ⁸ ). And a detection signal.

In the 2-bit error correction decoding circuit 72, in the error e _I on GF (2 ⁸ ) and the error e ′ _I on GF (2 ⁶ ), e _I → e ′ _I is injective relationship. Therefore, it can be realized by a combinational circuit by performing logic synthesis.

Specifically, for example, in FIG. 19, the information 2 byte, a ^{_{e I · H 'T = e}} I', H ' is a 2-bit error correction code check matrix having a rank 4 shown in Formula 26 Therefore, the error e _I on GF (2 ⁸ ) having a weight of 2 or less and the error e _I ′ on GF (2 ⁶ ) are uniquely determined. Thus, the error e _I = (e ₈ e ₉ e ₁₀ e ₁₁ e ₁₂ e ₁₃ e ₁₄ e ₁₅ ) on GF (2 ⁸ ) with a weight of 2 or less, and the error e _I '= on GF (2 ⁶ ) (E ₆ 'e ₇ ' e ₈ 'e ₉ ' e ₁₀ 'e ₁₁ ') has the relationship shown in Table 1 below.

ここで、ＧＦ（２^６）上の誤りｅ_I’は３７パターンあるが、残りの２^６−３７＝２７パターンに対するｅ_Iは、訂正能力外誤りとして検出し、ｅ_Iの出力はドントケア＊とする。

Here, GF ^{(2 6)} the error e _I on 'is some 37 patterns, e _I for the remaining ² 6 -37 = 27 patterns, detected as correction capability out error, the output of e _I and do not care * To do.

For example, from the correspondence between the error e _I on GF (2 ⁸ ) and the error e _I ′ on GF (2 ⁶ ) shown in Table 1 above, the value e ₈ of the first bit of the information second byte is _{e I '= (e 6'} e 7 'e 8' e 9 'e 10' e 11 ') = (100000), (110000), (101000), (100100), (011100), (100010), ( 101111) and (100001).

Further, in the correspondence relationship between the error e _I on GF (2 ⁸ ) and the error e _I 'on GF (2 ⁶ ) shown in Table 1, the error e on the remaining 27 patterns of GF (2 ⁶ ) _{I '= (e 6' e} 7 'e 8' e 9 'e 10' e 11 ') = (100110), (110110), (010110), (011110), (101110), (110010), (011010 ), (1111010), (101010), (1000011), (010011), (011011), (1111011), (101011), (100111), (110111), (010111), (111111), (100101), (110101), (010101), (011101), (101101), (110001), (011001), (111001), (101 The value _{e 8} of the first bit of information 2 byte for 001) is a do not care *.

When these logical functions are simplified, the value e ₈ of the first bit of the information second byte is expressed by the logical expression shown in the following equation 88.

ただし、

は

の否定で、

は

であり、また、

は論理和を、

は論理積を表す。

However,

Is

In denial of

Is

And also

Is logical OR

Represents a logical product.

を生成する。そして、

を３入力ＡＮＤゲート回路９１に、

を４入力ＡＮＤゲート回路９２に、

を５入力ＡＮＤゲート回路９３に、

を４入力ＡＮＤゲート回路９２に、

を４入力ＡＮＤゲート回路９２にそれぞれ入力する。それぞれのＡＮＤゲート回路から出力された信号を５入力ＯＲゲート回路９４に入力することにより、情報２バイト目の１ビット目の値ｅ_８が得られる。 Therefore, as shown in FIG. 19, first, the bit error pointers 40e ′ ₆ , e ′ ₇ , e ′ ₈ , e ′ ₉ , e ′ ₁₀ , e ′ ₁₁ on GF (2 ⁶ ) are transferred to the NOT gate circuit 90. Enter

Is generated. And

To the 3-input AND gate circuit 91,

To the 4-input AND gate circuit 92,

To the 5-input AND gate circuit 93,

To the 4-input AND gate circuit 92,

Are input to the 4-input AND gate circuit 92, respectively. By inputting respective signals outputted from the AND gate circuit 5-input OR gate circuit 94, the first bit of the value e ₈ Information 2 byte is obtained.

As shown in FIGS. 19 and 20, the values e ₉ ,..., E ₁₅ of the other bits are also a NOT gate circuit 90, a 3-input AND gate circuit 91, a 4-input AND gate circuit 92, and a 5-input AND gate. The circuit 93, the 5-input OR gate circuit 94, and the 6-input OR gate circuit 95 can be obtained in the same manner.

The detection signal output unit of the t-bit error correction decoding circuit (in this example, a 2-bit error correction decoding circuit) 72 can be configured in the same manner. The detection signal output unit detects an error e _I on GF (2 ⁸ ) that is not mapped from the error e ′ _I on GF (2 ⁶ ) as an uncorrectable error. For example, FIG. 21 shows a detection signal output unit for the second byte.

Specifically, for example, in the second byte of information, the remaining 27 patterns in the correspondence relationship between the error e _I on GF (2 ⁸ ) and the error e _I 'on GF (2 ⁶ ) shown in Table 1 above Error on GF (2 ⁶ ) e _I ′ = (e ₆ ′ e ₇ ′ e ₈ ′ e ₉ ′ e ₁₀ ′ e ₁₁ ′) = (100110), (110110), (010110), (011110), (101110), (110010), (011010), (1111010), (101010), (1000011), (010011), (011011), (1111011), (101011), (100111), (110111), (010111) ), (111111), (100101), (110101), (010101), (011101), (101101), (110001), (011) The detection signal values for (001), (111001), and (101001) are set to 1, and an error is detected.

  Therefore, when these logical functions are simplified, the value of the detection signal is expressed by the logical expression shown in the following equation 89.

よって、図２１に示されるように、まず、ＧＦ（２^６）上のビット誤りポインタ４０ｅ’_６、ｅ’_７、ｅ’_８、ｅ’_９、ｅ’_１０、ｅ’_１１をＮＯＴゲート回路９０に入力し、

を生成する。

Therefore, as shown in FIG. 21, first, the bit error pointers 40e ′ ₆ , e ′ ₇ , e ′ ₈ , e ′ ₉ , e ′ ₁₀ , e ′ ₁₁ on GF (2 ⁶ ) are transferred to the NOT gate circuit 90. Enter

Is generated.

を合計１４個の４入力ＡＮＤゲート９２及び５入力ＡＮＤゲート９３にそれぞれ入力する。 And

Are input to a total of 14 4-input AND gates 92 and 5-input AND gates 93, respectively.

  Finally, a signal output from each AND gate circuit is input to a 14-input OR circuit 96, thereby outputting a detection signal.

  In the above, the t-bit error correction decoding circuit 72 in the second byte has been described in detail as an example, but the same applies to other bytes.

  Finally, a configuration example of the bit-by-bit selection circuit 75 is specifically shown.

  As shown in FIG. 22, the bit-by-bit selection circuit 75 is a circuit that selects each bit of two signals each having 8 bits according to a control signal.

  Here, the processing of the bit-by-bit selection circuit 75 will be described in more detail. As shown in FIG. 22, the 0th bit among the 8-bit signals is input to the 2-input multiplexer 86. The 2-input multiplexer 86 outputs the upper signal when the control signal is 0, and outputs the lower signal when the control signal is 1. Similarly, signals other than the 0th bit are selected by a control signal. The signals output from the 2-input multiplexer 86 are combined and finally output as an 8-bit signal.

In has been described a code having distance d = 5 as an example, d = regard to codes having 5 than the distance, the sum of errors for each byte (e _A) and bit-error pointer on GF (2 ^r) or The circuit can be configured in the same manner by dividing the cases using the bit-by-bit selection circuit 75 in the error generation circuit on GF (2 ^b ).

(F) Configuration of Inversion Circuit 10 Finally, the configuration of the inversion circuit 10 will be described.

For example, FIG. 23 shows an inverting circuit 10 specifically configured for the second byte. The inverting circuit 10 shown in FIG. 23 is a circuit that corrects the received word (V ′) 32 by inverting the received bit value at the bit position where the location of the error is specifically pointed out. In FIG. 23, v ₈ ′ to v ₁₅ ′ are 8 bits corresponding to the second byte of the received word (V ′) 32, and v ₈ ^{* to} v ₁₅ ^* are output bits after correction.

The inverting circuit 10 has a plurality of exclusive OR circuits. In the inverting circuit 10 in the second byte shown in FIG. 23, a total of eight exclusive OR circuits 97 have corresponding bit error pointers e _i (i) for the eight input bits v ₈ ′ to v ₁₅ ′. = 8, 9,..., 15), for example, when the bit error pointer is “1”, the input bit value is inverted and corrected.

Note that the inverting circuit 10 requires 90 exclusive OR circuits for a received word (V ′) of N = 90 bits so as to correspond to each byte. The inverting circuit 10 finally obtains a 64-bit correction word D ^* shown in the following equation 90 from the received word (V ′) of N = 90 bits.

以上では、図３に示す距離ｄ＝５を有する（９０、６４）Ｄ_２／８ＥＣ符号を例にとり、距離ｄを有するバイト内複数スポッティバイト誤り制御符号における符号化・復号回路構成を詳細に説明した。ここで、ＧＦ（２^ｒ）上の並列復号回路８において、前記バーレカンプ・マッシィ法を用いた逐次復号を行う場合に、誤り位置多項式および誤り評価多項式から、誤り位置および誤りを求める既存の手法を用いればよい。この手法の実現手段は、ハードウェアでもソフトウェアでもよい。

In the above, the (90, 64) D _2/8 EC code having the distance d = 5 shown in FIG. 3 is taken as an example, and the encoding / decoding circuit configuration in the intra-byte multiple spotty byte error control code having the distance d is detailed. Explained. Here, in the parallel decoding circuit 8 on GF (2 ^r ), when performing sequential decoding using the Burlekamp-Massie method, an existing method for obtaining an error position and an error from an error position polynomial and an error evaluation polynomial is used. Use it. The means for realizing this technique may be hardware or software.

  Further, for the intra-byte multiple spotty byte error control codes having a distance d other than d = 5, the following concept can be used.

  First, the encoding circuit only needs to generate R-bit check information using a binary parity check matrix, and can be configured in exactly the same way.

Also, as described above, decoding is performed by dividing the error e ′ on GF (2 ^r ) obtained by decoding the RS code according to the number of bytes in which an error has occurred, thereby obtaining GF (2 ^b ) The above error can be obtained.

For example, when the distance d = 7, since the matrix H ″ is a matrix that satisfies Rank (H ″) ≧ Min (3t, b), the error on the GF (2 ^b ) in the example of the distance d = 5 In the generation circuit 9, the configuration of the t-bit error correction decoding circuit 72 is changed to a code decoding circuit having a correction capability of t-bit error correction and 2t-bit error detection.

In addition, by constructing a circuit for performing case division using the selection circuit 75 for each bit when the error byte is 1, 2, or 3 bytes in the error e ′ on GF (2 ^r ). Similarly, a decoding circuit can be configured. Therefore, it is obvious that the decoding circuit for the intra-byte multiple spotty byte error control code having the distance d can be similarly configured even when the distance d is not 5 or 7.

  Further, the multi-spotted byte error control code in the decompressed byte shown in the above equation 5 can be configured based on the following idea.

  First, the encoding circuit only needs to generate R-bit check information using a binary parity check matrix, and can be configured in exactly the same way.

In addition, decoding is performed by decoding an RS code on GF (2 ^{(R−r) / (d−2)} ) by a sequential decoding method using the parallel decoding method or the Burlekamp Massy method, By converting an error on GF (2 ^{(R−r) / (d−2)} ) into an error on GF (2 ^b ) in the same manner as in the example of the distance d = 5, the error can be similarly decoded.

Therefore, the decoding circuit also changes the parallel decoding circuit 8 on GF (2 ^r ) in the example of the distance d = 5 to a circuit that performs parallel decoding on GF (2 ^{(R−r) / (d−2)} ). In addition, in the error generation circuit 9 on the GF (2 ^b ) in the example of the distance d = 5, by changing r bits to (R−r) / (d−2) bits, the decoding circuit is changed. Obviously, it can be configured similarly.

  In addition, the two types of intra-byte multiple spotty byte error control codes having different sizes shown in the above equations 28, 36, 46, and 59 can be configured based on the following idea. .

  First, the encoding circuit only needs to generate R-bit check information using a binary parity check matrix, and can be configured in exactly the same way.

In addition, for example, in the case of the St _{/ b} EC- (S _{t / b} + S _{t ′ / b} ) ED code shown in Equation 28, an error occurs in the error e ′ on GF (2 ^r ). When the location is 1 byte, since H ″ is a matrix satisfying Rank (H ″) ≧ Max (t, t ′), it is an error within t bits in a byte having b bits, e _I On the other hand, the error e _I can be obtained from the relational expression e _I · H ′ ^T = e _I ′. In addition, in the error e ′ on GF (2 ^r ), when the location where the error occurs is 2 bytes, it can be detected during the parallel decoding.

  Therefore, the H ′ decoding circuit 6, the H ″ multiplication circuit 7, and the t-bit error correction decoding circuit 72 in the example where the distance d = 5 satisfy the rank (H ′) ≧ Min (2t + t ′, b). Corresponding to the matrix H ″ satisfying H ′, Rank (H ″) ≧ Max (t, t ′), the decoding circuit is similar to the decoding circuit for the multiple spotty byte error control codes in the distance d = 4. Can be configured.

  Similarly, the two types of intra-byte multiple spotty byte error control codes having different sizes shown in Equation 36 can be configured in the same manner as the decoding circuit for the intra-byte multiple spotty byte error control codes of distance d = 4. it is obvious.

  Also, the two types of intra-byte multiple spotty byte error control codes having different sizes shown in the equations 46 and 59 are configured in the same manner as the decoding circuit for the intra-byte multiple spotty byte error control codes of the distance d = 5. Clearly, it is possible.

  As described above, in the present invention, for a spotty byte error having an error of up to t bits in a byte, a general code configuration of an intra-byte multiple spotty byte error control code having an arbitrary predetermined distance d, In addition, a coding configuration of a code for controlling a plurality of spotty byte errors in two types of bytes having different sizes and a coding / decoding circuit configuration, which is a circuit capable of correcting / detecting an error, is shown. It was shown that it can be generated specifically, and that errors can be corrected and detected specifically.

  In the above description, the application of the present invention has been described mainly focusing on the memory device. However, the present invention is not limited to this, and for example, such a circuit and a module that are physically independent in units of bytes. And a device, and can be applied to a general information system or the like in which a limited number of errors are likely to occur. The present invention can also be applied to a circuit, device, or system for communication or transmission such as an optical communication circuit or a bus line circuit.

  Another object of the present invention is to supply a storage medium in which a program code of software that realizes the function of the intra-byte multiple spotty byte error correction / detection device of the present embodiment is supplied to the system or device. Needless to say, this can also be achieved by reading and executing the program code stored in the storage medium by the computer (or CPU or MPU) of the apparatus.

  In this case, the program code itself read from the storage medium realizes the functions of the present embodiment, and the storage medium storing the program code and the program code constitute the present invention. As a storage medium for supplying the program code, ROM, flexible disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, and the like can be used.

  Further, by executing the program code read by the computer, not only the functions of the present embodiment are realized, but also the OS or the like running on the computer based on the instruction of the program code performs the actual processing. It goes without saying that a case where the function of this embodiment is realized by performing part or all of the above and the processing thereof is included.

1 is a block diagram showing a schematic configuration of an intra-byte multiple spotty byte error correction / detection device according to an embodiment of the present invention. FIG. 2 is a flowchart showing a processing procedure of overall operation in the intra-byte multiple spotty byte error correction / detection apparatus of the present invention shown in FIG. 1. FIG. 4 is an example of a parity check matrix according to the present invention, which is a code parameter with a code length N = 90 bits, an information length K = 64 bits, a check length R = 26 bits, a byte length b = 8 bits, and an intra-byte correction bit length 2 bits. FIG. 6 is a diagram illustrating a parity check matrix of a shortened (90, 64) D _2/8 EC code having FIG. 4 is a diagram illustrating a parity check matrix of an encoding (90, 64) D _2/8 EC system code obtained by modifying the parity check matrix shown in FIG. 4 is a specific example of an encoding circuit (upper 14 bits) configured based on the (90, 64) D _2/8 EC systematic code for encoding shown in FIG. 4, and parity check is performed from K = 64-bit input information data. It is a conceptual diagram of the circuit which produces | generates 26 bits test | inspection information with a matrix. 4 is a specific example of an encoding circuit (lower 12 bits) configured based on the (90, 64) D _2/8 EC systematic code for encoding shown in FIG. 4, and parity check is performed from K = 64-bit input information data. It is a conceptual diagram of the circuit which produces | generates 26 bits test | inspection information with a matrix. It is a block diagram which shows schematic structure of the decoding circuit with respect to the code | symbol which has the function disclosed by this invention. FIG. 4 is a conceptual diagram for explaining a syndrome generation circuit (upper 14 bits) specifically configured based on the (90, 64) D _2/8 EC code shown in FIG. 3. FIG. 4 is a conceptual diagram for explaining a syndrome generation circuit (lower 12 bits) specifically configured based on the (90, 64) D _2/8 EC code shown in FIG. 3. FIG. 4 is a configuration diagram of an H ′ decoding circuit specifically configured based on the (90, 64) D _2/8 EC code shown in FIG. 3. FIG. 4 is a configuration diagram of an H ″ multiplier circuit specifically configured based on the (90, 64) D _2/8 EC code shown in FIG. 3. FIG. 4 is a block diagram showing a schematic configuration of a parallel decoding circuit on GF (2 ^r ) for the (90, 64) D _2/8 EC code shown in FIG. 3. It is a circuit block diagram of an example of the error generation circuit with respect to (i, j) in the parallel decoding circuit on GF (2 ^r ) shown in FIG. It is a configuration diagram of an error calculation circuit on GF ^{(2 r)} in the parallel decoding circuit on GF ^{(2 r)} shown in FIG. 12. FIG. 4 is a block diagram showing a schematic configuration of an error generation circuit on GF (2 ^b ) for the (90, 64) D _2/8 EC code shown in FIG. 3. FIG. 16 is a configuration diagram of an error byte detection circuit in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15. FIG. 16 is a configuration diagram of a circuit that detects a Hamming weight 1 in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15. It is a block diagram of the 12 input sort circuit in the circuit which detects the Hamming weight 1 shown in FIG. 15 is an example of a t-bit error correction decoding circuit in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15, and an error on GF (2 ^r ) is converted into an error on GF (2 ^b ) for one byte. FIG. 15 is an example of a t-bit error correction decoding circuit in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15, and an error on GF (2 ^r ) is converted into an error on GF (2 ^b ) for one byte. FIG. FIG. 16 is an example of a t-bit error correction decoding circuit in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15 and is a configuration diagram of a circuit that detects an error for one byte. FIG. 16 is a configuration diagram of a bit-by-bit selection circuit in the error generation circuit on GF (2 ^b ) illustrated in FIG. 15. It is an example of the inversion circuit with respect to the (90, 64) D _2/8 EC code shown in FIG. 3, and is a block diagram of the inversion circuit for 1 byte.

Explanation of symbols

６１

６２

６３ 多入力パリティチェック回路
６４ 多入力パリティチェック回路
６５ 多入力パリティチェック回路
６６ １２入力ＮＯＲゲート回路
６７ ２入力ＡＮＤゲート回路
６８ ビットごとＯＲ演算回路
６９ １１入力ＯＲゲート回路
７０ 誤りバイト検出回路
７１ ハミング重み１を検出する回路
７２ ｔビット誤り訂正復号回路
７３ ２入力ＡＮＤゲート回路
７４ １２入力ＯＲゲート回路
７５ ビットごと選択回路
８０ ６入力ＯＲゲート回路
８１ １２入力ソート回路
８２ ＮＯＴゲート回路
８３ １２入力ＡＮＤゲート回路
８４ ２入力ＯＲゲート回路
８５ ２入力ＡＮＤゲート回路
８６ ２入力マルチプレクサ回路
９０ ＮＯＴゲート回路
９１ ３入力ＡＮＤゲート回路
９２ ４入力ＡＮＤゲート回路
９３ ５入力ＡＮＤゲート回路
９４ ５入力ＯＲゲート回路
９５ ６入力ＯＲゲート回路
９６ １５入力ＯＲゲート回路
９７ 排他的論理和回路
１００ バイト内複数スポッティバイト誤り訂正・検出装置 1 Syndrome generation circuit 2 Encoding circuit 3 Circuit (communication path such as memory)
4 Decoding Circuit 5 Error Correction Circuit 6 H ′ Decoding Circuit 7 H ”Multiplication Circuit 8 Parallel Decoding Circuit 9 on GF (2 ^r ) Error Generation Circuit 10 on GF (2 ^b ) Inverting Circuit 20 Multi-Input Parity Check Circuit 21 Multi Input parity check circuit 22 2-input exclusive OR circuit 23 3-input parity check circuit 30 Input information data 31 Transmission word 32 Reception word 33 Syndrome (S)
34 Output information data 35 Uncorrectable error detection signal (UCE)
36 upper q bits (S _I ) of syndrome (S) 33
37 Lower 3r bits of syndrome (S) 33 (S _II S _III S _IV )
Sum of errors every 38 bytes (e _A )
39 Product (S ′ _I ) of high-order q bit S _I 36 of syndrome (S) 33 and transposition (H ″ ^T ) of H ″
40 Bit error pointer 41 on GF (2 ^r ) 41 Uncorrectable error detection signal (DS (0))
42 Bit error pointer 43 on GF (2 ^b ) 43 Uncorrectable error detection signal (DS (1))
44 Error generation circuit 51 on 2-input AND gate circuit 50 (i, j) Error correction circuit 52 on GF (2 ^r ) 52 Error correction circuit 52 (i, j) 53 (i, j) Correctable signal 54 24-input OR gate Circuit 55 66 input NOR gate circuit 56 2-input AND gate circuit 60

61

62

63 Multi-input parity check circuit 64 Multi-input parity check circuit 65 Multi-input parity check circuit 66 12-input NOR gate circuit 67 2-input AND gate circuit 68 Bitwise OR operation circuit 69 11-input OR gate circuit 70 Error byte detection circuit 71 Hamming weight 1 detection circuit 72 t-bit error correction decoding circuit 73 2-input AND gate circuit 74 12-input OR gate circuit 75 bit-by-bit selection circuit 80 6-input OR gate circuit 81 12-input sort circuit 82 NOT gate circuit 83 12-input AND gate circuit 84 2-input OR gate circuit 85 2-input AND gate circuit 86 2-input multiplexer circuit 90 NOT gate circuit 91 3-input AND gate circuit 92 4-input AND gate circuit 93 5-input AND gate circuit 94 5-input OR gate circuit 95 6-input OR gate circuit 96 15-input OR gate circuit 97 exclusive OR circuit 100 multiple spotty byte error correction / detection device in byte

Claims (48)

A plurality of in-byte units, comprising: encoding means for generating a transmission word based on input information data; and decoding means for correcting or detecting the error by inputting the transmission word in which an error has occurred in an information transmission path as a reception word Spotty byte error correction / detection device,
The encoding means generates the transmission word by adding check information generated based on a parity check matrix expressing a spotty byte error control code and the input information data to the input information data,
The decoding means includes a syndrome generating means for generating a syndrome of the received word based on the parity check matrix, and an error correcting means for correcting or detecting an error of the received word based on the syndrome generated by the syndrome generating means And an intra-byte multiple spotty byte error correction / detection device. In the case where the input information data is composed of a plurality of bytes with b (b is an integer of 2 or more) bits, an error up to t bits (1 ≦ t ≦ b) in the bytes is detected. Assuming that the spotty byte error is an error in which a plurality of the spotty byte errors occur in one byte is called a spotty byte error in a byte,
The spotty byte error control code represented by the parity check matrix is represented by a distance d.

The intra-byte multiple spotty byte error correction / detection device according to claim 1.   The intra-byte multiple spotty byte error correction / detection device according to claim 2, wherein the t value, the b value, and the d value are arbitrarily set.   4. The intra-byte multiple spotty byte error correction / detection device according to claim 1, wherein the information transmission path is an information communication system.   4. The intra-byte multiple spotty byte error correction / detection apparatus according to claim 1, wherein the information transmission path is a memory system.   The intra-byte multiple spotty byte error correction / detection device according to any one of claims 1 to 3, wherein the information transmission path is a bus line circuit. The parity check matrix is a next matrix H having R rows and N columns used for an intra-byte multiple spotty byte error control code having the distance d.

However, R = q + (d−2) r, N = bn, 0 ≦ i ≦ n−1, n = 2 ^r −1, and the matrix H ′ has H ′ = [h ₀ ′, h ₁ ′, .., H _b-1 ′], a q-th column vector h _j ′ (0 ≦ j ≦ b−1) and a q × b binary matrix (q ≦ b), d-1) has a rank equal to or larger than either t or b, i.e. Rank (H ′) ≧ Min ((d−1) t, b), and the matrix When the rank of H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and when the rank of the matrix H ′ is (d−1) t <b, the matrix H ′ is the minimum Hamming A parity check matrix of a code having a distance (d-1) t + 1, that is, a parity check matrix of a (d-1, b) code having a (d-1) t-bit error detection function, and Matrix H _"is, H" = consists _{[h 0 ", h 1"} , ···, h b-1 "] are shown r next column vector _{h j" (0 ≦ j ≦} b-1) a binary matrix of r rows and b columns (r ≦ b),

Or has a rank equal to or greater than the smaller value of b, ie,

Satisfied here,

Represents the smallest integer not exceeding x, and when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

Is equal to a parity check matrix of a (b, b−r) code having a bit error detection function, and γ is a primitive element of an r-order extension field GF (2 ^r ) with 2 as a base, and γ ⁱ H ″ The in-byte multiple spotty according to any one of claims 2 to 6, which is configured such that = [γ ⁱ h ₀ ", γ ⁱ h ₁ ", ..., γ ⁱ h _b-1 "] Byte error correction / detection device. The parity check matrix is a next matrix H having R rows and N columns used for a multi-spotted byte error control code in extended bytes having the distance d.

However, R ≧ q + (d−2) r and (R−q) is a multiple of (d−2), N = b (n + 1) + (R−q) / (d−2), 0 ≦ i ≦ n−1, (Rq) is a multiple of (d−2), n = 2 ^{(Rq) / (d−2)} −1, and the matrix H ′ is H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′] of q-th column vector h _j ′ (0 ≦ j ≦ b−1) of q rows and b columns (q ≦ b) It is a binary matrix and has a rank (Rank) that is equal to or greater than (d-1) t or b, i.e., Rank, that is, Rank (H ′) ≧ Min ((d−1) t, b ) And the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and the rank of the matrix H ′ is (d−1) t <b. The matrix H ′ is the minimum Hamming distance (d−1) t + 1. Check matrix of a code having, i.e., (d-1) is equal to t bits having an error detection function (b, b-q) code of the parity check matrix, also the matrix H "is, H" = _[h 0 " , H ₁ ″,..., H _b−1 ″], r-row b column (r ≦ b) binary composed of r-th column vector h _j ″ (0 ≦ j ≦ b−1) Matrix

Or has a rank equal to or greater than the smaller value of b, ie,

And the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

It is equal to the parity check matrix of a (b, b−r) code having a bit error detection function, R ≧ q + (d−2) r, Rq is a multiple of d−2, and γ is 2 ( ^{Rq) / (d-2} ) is a primitive element of the next extension field GF (2 ^{(Rq) / (d-2)} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ”
), Γ ⁱ Φ (h ₁ ″),..., Γ ⁱ Φ (h _b-1 ″)
)], Where Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(Rq) / (d-2)} ) under addition 7. In-byte multiple spotty byte error correction according to claim 2, wherein Φ: GF (2 ^q ) → GF (2 ^{(R−q) / (d−2) 2)} -Detection device. When the input information data includes b (b is an integer of 2 or more) bits and is composed of a plurality of bytes, an error up to t bits in the byte is referred to as a t / b error. Assuming that errors up to t ′ bits in a byte are referred to as t ′ / b errors, where 1 ≦ t, t ′ ≦ b, and t ≠ t ′,
The spotty byte error control code expressed by the parity check matrix includes two types of spotty byte errors having different sizes generated in one byte (that is, the t / b error and the t ′ / b error). The intra-byte multiple spotty byte error correction / detection device according to claim 1, further comprising a function for controlling the error.   The intra-byte multiple spotty byte error correction / detection device according to claim 9, wherein the information transmission path is an information communication system.   The intra-byte multiple spotty byte error correction / detection apparatus according to claim 9, wherein the information transmission path is a memory system.   The intra-byte multiple spotty byte error correction / detection device according to claim 9, wherein the information transmission path is a bus line circuit. The spotty byte error control code corrects one t / b error and detects a (t / b + t ′ / b) error (that is, a combined error of t / b error and t ′ / b error). St _{/ b} EC− (S _{t / b} + S _{t ′ / b} ) ED code having the function of
The parity check matrix used for the S _{t / b} EC− (S _{t / b} + S _{t ′ / b} ) ED code is the following matrix H having R rows and N columns,

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b) and has a rank equal to or smaller than 2t + t ′ or b, ie, Rank (H ′) ≧ Min (2t + t ′, b) is satisfied, and the matrix H ″ has an r-th column vector h _j ″ represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. It is a binary matrix of r rows and b columns (r ≦ b) composed of (0 ≦ j ≦ b−1), and has a rank equal to or greater than t or t ′, whichever is greater ,sand That is, Rank (H ″) ≧ Max (t, t ′) is satisfied, R ≧ q + 2r, (Rq) is a multiple of 2, and γ is 2 (Rq) / Primordial element of the secondary extension GF (2 ^{(Rq) / 2} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),... , Γ ⁱ Φ (h _b-1 ″)] holds, and Φ is a homomorphic mapping from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) under addition ( The intra-byte multiple spotty byte error correction / detection device according to any one of claims 9 to 12, which is homomorphism). The spotty byte error control code is an S _{t / b} EC-D _{t ′ / b} ED code having a function of correcting one t / b error and detecting two t ′ / b errors. Yes,
The parity check matrix used for the _{St / b} EC-D _{t ′ / b} ED code is the following matrix H having R rows and N columns;

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b), and has a rank that is equal to or greater than the larger value of 2t or t + 2t ′ and the smaller value of b That is, Rank (H ′) ≧ Min (Max (2t, t + 2t ′), b) is satisfied, and the matrix H ″ is H ″ = [h ₀ ″, h ₁ ″,..., H _{b −1} ″] is a binary matrix of r rows and b columns (r ≦ b) composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1), and either t or t ′ Or big Has a rank (Rank) that is equal to or greater than the value, ie, satisfies Rank (H ″) ≧ Max (t, t ′), R ≧ q + 2r, and (R−q) is a multiple of 2, and γ Is the primitive element of the base 2 (Rq) / 2 quadratic extension GF (2 ^{(Rq) / 2} ), where γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b-1 ″)] is established, and Φ is additively converted from GF (2 ^q ) to GF (2 ^{(R The} intra-byte multiple spotty byte error correction / detection device according to any one of claims 9 to 12, which is a homomorphism to ^{-q) / 2} ). The spotty byte error control code is a (S _{t / b} + S _{t ′ / b} ) EC code having a function of correcting an error ( _{t / b} + _{t ′ / b} ),
The parity check matrix used for the (S _{t / b} + S _{t ′ / b} ) EC code is the following matrix H having R rows and N columns:

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1), a q × b binary matrix having a rank equal to or greater than 2t + 2t ′ or b, i.e., Rank, Rank (H ′) ≧ Min (2t + 2t ′, b) is satisfied, and the matrix H ″ is an r-th order represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. Is a binary matrix of r rows and b columns (r ≦ b) made up of column vectors h _j ″ (0 ≦ j ≦ b−1), and rank equal to or greater than t + t ′ or b. (Ra nk), that is, Rank (H ″) ≧ Min (t + t ′, b) is satisfied, R ≧ q + 3r, and (R−q) is a multiple of 3, and γ is based on 2 ( Rq) / 3 primitive field GF (2 ^{(Rq) / 3} ) primitive element, and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″ _{^{), ···, γ i Φ (}} h b-1 ")] it is configured to establish, [Phi from under additive ^{GF (2 q) GF (2} (R-q) / 2) to The intra-byte multiple spotty byte error correction / detection device according to claim 9, wherein the device is a homomorphism. The spotty byte error control code corrects two t / b errors and has a function of correcting one t ′ / b error (t <t ′). D _{t / b} EC-S _{t '/ B} EC code,
The parity check matrix used for the D _{t / b} EC-S _{t ′ / b} EC code is the following matrix H having R rows and N columns:

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1) is a binary matrix of q rows and b columns (q ≦ b), and rank equal to or greater than the larger value of 4t or 2t ′ and the smaller value of b (Rank), that is, Rank (H ′) ≧ Min (Max (4t, 2t ′), b) is satisfied, and the matrix H ″ has H ″ = [h ₀ ″, h ₁ ″, .., H _b-1 ″] is an r-th column vector h _j ″ (0 ≦ j ≦ b−1) and is a binary matrix of r rows and b columns (r ≦ b), 2t Or t ', whichever is greater It has a rank (Rank) that is equal to or greater than the threshold value and whichever is smaller of b, that is, Rank (H ″) ≧ Min (Max (2t, t ′), b) is satisfied, and R ≧ q + 3r And (Rq) is a multiple of 3, and γ is the primitive element of (Rq) / 3-order extension GF (2 ^{(Rq) / 3} ) with 2 as the base, γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b−1 ″)] is established, and Φ is additive The intra-byte multiple spotty bytes according to claim 9, which is a homomorphism from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) Error correction / detection device.   The error correction unit generates a bit error pointer for detecting which bit of the received word is incorrect based on the syndrome, and the reception corresponding to the error bit is generated based on the generated bit error pointer. An uncorrectable error detection signal is output when an error of the received word is corrected by inverting the bit value of the word, and when it is detected that the bit error of the received word cannot be corrected. The intra-byte multiple spotty byte error correction / detection device according to claim 16. The error correction means comprises H ′ decoding means, H ″ multiplication means, parallel decoding means on GF (2 ^r ), error generation means on GF (2 ^b ), and inversion means. The intra-byte multiple spotty byte error correction / detection device according to any one of items 7, 8, 13, 13, 14, 15 and 16. The H ′ decoding means generates a sum of errors (e _A ) for each byte based on the upper q bits of the syndrome generated by the syndrome generation means,
The H ″ multiplying unit generates a product of the high-order q bits of the syndrome and a transposed matrix of H ″ based on the sum of errors (e _A ) for each byte generated by the H ′ decoding unit,
The parallel decoding means on the GF (2 ^r ) is a product of the upper q bits of the syndrome generated by the H ″ multiplication means and a transposed matrix of H ″, and the higher order of the syndrome generated by the syndrome generation means. Based on the remaining low-order bits excluding q bits, the bit error pointer on GF (2 ^r ) and the first bit output when error correction is considered impossible in parallel decoding on GF (2 ^r ) 1 uncorrectable error detection signal is generated,
The error generation means on the GF (2 ^b ) is generated by the sum of errors (e _A ) for each byte generated by the H ′ decoding means and the parallel decoding means on the GF (2 ^r ). wherein based on the bit error pointer on GF ^{(2 r),} and converts the error on GF ⁽² r) the error on ^{GF (2 b), GF (} 2 b) on the bit-error pointer has, And generating a second uncorrectable error detection signal that is output when error correction is deemed impossible,
It said inverting means, based on the bit error pointer on the GF (2 ^b) generated by the error vector generating means on the GF (2 ^b), corresponding to the bit-error pointer of the on GF (2 ^b) 19. The intra-byte multiple spotty byte error correction / detection device according to claim 18, wherein an error of the received word is corrected by inverting the bit value of the received word. In the error correction means, the first uncorrectable error detection signal generated by the parallel decoding means on the GF (2 ^r ) and the first error detection means generated by the error generation means on the GF (2 ^b ). 20. The multi-spot in byte according to claim 19, wherein a third uncorrectable error detection signal indicating that an error exceeding the correction capability is detected is obtained by performing a logical sum of the two uncorrectable error detection signals. Tbyte error correction / detection device. The error generation means on GF (2 ^b ) is:
Error byte detection means for detecting that the syndrome is non-zero;
T-bit error correction decoding means for outputting 1 byte of the bit error pointer on the GF (2 ^b ) from 1 byte of the bit error pointer on the GF (2 ^r );
A bit-by-bit selection means for selecting an input signal according to a control signal;
21. The intra-byte multiple spotty byte error correction / detection device according to claim 19 or 20, further comprising a Hamming weight detection means for detecting a Hamming weight 1 of an input signal. The error generation means on the GF (2 ^b ) includes error byte detection means, t-bit error correction decoding means, bit-by-bit selection means, and Hamming weight detection means.
The error byte detection means inputs 1 byte of a bit error pointer on the GF (2 ^r ), outputs a 1-bit syndrome detection signal,
The t-bit error correction decoding means receives a predetermined 1 byte of the bit error pointer on the GF (2 ^r ) as an input, and corresponds to the predetermined 1 byte of the bit error pointer on the GF (2 ^b ). In addition to outputting bytes, it also outputs detection signals that detect errors beyond the correction capability,
The bit-by-bit selection means selects each bit of the two input signals according to the control signal,
The Hamming weight detection means receives the syndrome detection signal output from the error byte detection means, calculates a Hamming weight of the input syndrome detection signal, and outputs 1 when the Hamming weight is 1 21. The intra-byte multiple spotty byte error correction / detection device according to claim 19 or 20, wherein the device is configured to output 0 if not. In the t-bit error correction decoding means, the error exceeding the correction capability is the error e _I on the GF (2 ^b ) that is not mapped from the error e ′ _I on the GF (2 ^r ). The intra-byte multiple spotty byte error correction / detection device according to claim 22. In the error generation means on the GF (2 ^b ), the detection signal output from the t-bit error correction decoding means is input to a multi-input OR gate circuit, and the multi-input OR gate circuit inputs the detection signal Outputting the second uncorrectable error detection signal based on the signal;
In the error generation means on GF (2 ^b ), the signal output from the Hamming weight detection means and the syndrome detection signal output from the error byte detection means are respectively input to the 2-input AND gate circuit. The signal output from the two-input AND gate circuit is used as the control signal of the bit-by-bit selection means,
The bit-by-bit selection means selects the signal output from the t-bit error correction decoding means and the error sum (e _A ) for each byte according to the control signal, collects the selected signals, The intra-byte multiple spotty byte error correction / detection device according to claim 23, wherein a bit error pointer on GF ( ^2b ) is output. A byte having an encoding processing step for generating a transmission word based on input information data, and a decoding processing step for correcting or detecting the error by inputting the transmission word in which an error has occurred in an information transmission path as a reception word Of which multiple spotty byte errors are corrected and detected.
The encoding processing step generates the transmission word by adding check information generated based on a parity check matrix expressing a spotty byte error control code and the input information data to the input information data. ,
The decoding processing step corrects or detects an error of the received word based on a syndrome generation processing step of generating a syndrome of the received word based on the parity check matrix and a syndrome generated by the syndrome generation processing step. An error correction processing step, and an intra-byte multiple spotty byte error correction / detection method. In the case where the input information data is composed of a plurality of bytes with b (b is an integer of 2 or more) bits, an error up to t bits (1 ≦ t ≦ b) in the bytes is detected. Assuming that the spotty byte error is an error in which a plurality of the spotty byte errors occur in one byte is called a spotty byte error in a byte,
The spotty byte error control code represented by the parity check matrix is represented by a distance d.

The method for correcting and detecting a plurality of spotty byte errors in bytes according to claim 25.   27. The intra-byte multiple spotty byte error correction / detection method according to claim 26, wherein the t value, b value, and d value are arbitrarily set.   28. The intra-byte multiple spotty byte error correction / detection method according to claim 25, wherein the information transmission path is an information communication system.   28. The intra-byte multiple spotty byte error correction / detection method according to claim 25, wherein the information transmission path is a memory system.   28. The intra-byte multiple spotty byte error correction / detection method according to claim 25, wherein the information transmission path is a bus line circuit. The parity check matrix is a next matrix H having R rows and N columns used for an intra-byte multiple spotty byte error control code having the distance d.

However, R = q + (d−2) r, N = bn, 0 ≦ i ≦ n−1, n = 2 ^r −1, and the matrix H ′ has H ′ = [h ₀ ′, h ₁ ′, .., H _b-1 ′], a q-th column vector h _j ′ (0 ≦ j ≦ b−1) and a q × b binary matrix (q ≦ b), d-1) has a rank equal to or larger than either t or b, i.e. Rank (H ′) ≧ Min ((d−1) t, b), and the matrix When the rank of H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and when the rank of the matrix H ′ is (d−1) t <b, the matrix H ′ is the minimum Hamming A parity check matrix of a code having a distance (d-1) t + 1, that is, a parity check matrix of a (d-1, b) code having a (d-1) t-bit error detection function, and Matrix H _"is, H" = consists _{[h 0 ", h 1"} , ···, h b-1 "] are shown r next column vector _{h j" (0 ≦ j ≦} b-1) a binary matrix of r rows and b columns (r ≦ b),

Or has a rank equal to or greater than the smaller value of b, ie,

Satisfied here,

Represents the smallest integer not exceeding x, and when the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

Is equal to a parity check matrix of a (b, b−r) code having a bit error detection function, and γ is a primitive element of an r-order extension field GF (2 ^r ) with 2 as a base, and γ ⁱ H ″ The in-byte multiple spotty according to any one of claims 26 to 30, wherein = [γ ⁱ h ₀ ", γ ⁱ h ₁ ", ..., γ ⁱ h _b-1 "] is established. Byte error correction / detection method. The parity check matrix is a next matrix H having R rows and N columns used for a multi-spotted byte error control code in extended bytes having the distance d.

However, R ≧ q + (d−2) r and (R−q) is a multiple of (d−2), N = b (n + 1) + (R−q) / (d−2), 0 ≦ i ≦ n−1, (Rq) is a multiple of (d−2), n = 2 ^{(Rq) / (d−2)} −1, and the matrix H ′ is H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′] of q-th column vector h _j ′ (0 ≦ j ≦ b−1) of q rows and b columns (q ≦ b) It is a binary matrix and has a rank (Rank) that is equal to or greater than (d-1) t or b, i.e., Rank, that is, Rank (H ′) ≧ Min ((d−1) t, b ) And the rank of the matrix H ′ is equal to b, the matrix H ′ is a b × b matrix of rank b, and the rank of the matrix H ′ is (d−1) t <b. The matrix H ′ is the minimum Hamming distance (d−1) t + 1. Check matrix of a code having, i.e., (d-1) is equal to t bits having an error detection function (b, b-q) code of the parity check matrix, also the matrix H "is, H" = _[h 0 " , H ₁ ″,..., H _b−1 ″], r-row b column (r ≦ b) binary composed of r-th column vector h _j ″ (0 ≦ j ≦ b−1) Matrix

Or has a rank equal to or greater than the smaller value of b, ie,

And the rank of the matrix H ″ is equal to b, the matrix H ″ is a b × b matrix of rank b, and the rank of the matrix H ″ is

The matrix H ″ is the minimum Hamming distance

A check matrix of codes with

It is equal to the parity check matrix of a (b, b−r) code having a bit error detection function, R ≧ q + (d−2) r, Rq is a multiple of d−2, and γ is 2 ( ^{Rq) / (d-2} ) is a primitive element of the next extension field GF (2 ^{(Rq) / (d-2)} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ”
), Γ ⁱ Φ (h ₁ ″),..., Γ ⁱ Φ (h _b-1 ″)
)], Where Φ is a homomorphism from GF (2 ^q ) to GF (2 ^{(Rq) / (d-2)} ) under addition 31. In-byte multiple spotty byte error correction according to any one of claims 26 to 30, wherein: Φ: GF ( ^2q ) → GF (2 ^{(Rq) / (d-2)} ) -Detection method. When the input information data includes b (b is an integer of 2 or more) bits and is composed of a plurality of bytes, an error up to t bits in the byte is referred to as a t / b error. Assume that errors up to t ′ bits in a byte are referred to as t ′ / b errors, provided that 1 ≦ t, t ′ ≦ b, and t ≠ t ′.
The spotty byte error control code represented by the parity check matrix includes two types of spotty byte errors having different sizes generated in one byte (that is, the t / b error and the t ′ / b error). 26. The intra-byte multiple spotty byte error correction / detection method according to claim 25, comprising a function for controlling the error.   34. The intra-byte multiple spotty byte error correction / detection method according to claim 33, wherein the information transmission path is an information communication system.   34. The intra-byte multiple spotty byte error correction / detection method according to claim 33, wherein the information transmission path is a memory system.   34. The intra-byte multiple spotty byte error correction / detection method according to claim 33, wherein the information transmission path is a bus line circuit. The spotty byte error control code corrects one t / b error and detects a (t / b + t ′ / b) error (that is, a combined error of t / b error and t ′ / b error). St _{/ b} EC− (S _{t / b} + S _{t ′ / b} ) ED code having the function of
The parity check matrix used for the S _{t / b} EC− (S _{t / b} + S _{t ′ / b} ) ED code is the following matrix H having R rows and N columns,

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b) and has a rank equal to or smaller than 2t + t ′ or b, ie, Rank (H ′) ≧ Min (2t + t ′, b) is satisfied, and the matrix H ″ has an r-th column vector h _j ″ represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. It is a binary matrix of r rows and b columns (r ≦ b) composed of (0 ≦ j ≦ b−1), and has a rank equal to or greater than t or t ′, whichever is greater ,sand That is, Rank (H ″) ≧ Max (t, t ′) is satisfied, R ≧ q + 2r, (Rq) is a multiple of 2, and γ is 2 (Rq) / Primordial element of the secondary extension GF (2 ^{(Rq) / 2} ), and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),... , Γ ⁱ Φ (h _b-1 ″)] holds, and Φ is a homomorphic mapping from GF (2 ^q ) to GF (2 ^{(R−q) / 2} ) under addition ( 37. The intra-byte multiple spotty byte error correction / detection method according to any one of claims 33 to 36, which is homomorphism). The spotty byte error control code is an S _{t / b} EC-D _{t ′ / b} ED code having a function of correcting one t / b error and detecting two t ′ / b errors. Yes,
The parity check matrix used for the _{St / b} EC-D _{t ′ / b} ED code is the following matrix H having R rows and N columns;

However, R ≧ q + 2r and (Rq) is a multiple of 2, and N = b (n + 1) + Rq, 0 ≦ i ≦ n−1, n = 2 ^{(Rq) / 2} − 1 and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ j ≦ b−1) represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. Is a binary matrix of q rows and b columns (q ≦ b), and has a rank that is equal to or greater than the larger value of 2t or t + 2t ′ and the smaller value of b That is, Rank (H ′) ≧ Min (Max (2t, t + 2t ′), b) is satisfied, and the matrix H ″ is H ″ = [h ₀ ″, h ₁ ″,..., H _{b −1} ″] is a binary matrix of r rows and b columns (r ≦ b) composed of r-th order column vectors h _j ″ (0 ≦ j ≦ b−1), and either t or t ′ Or big Has a rank (Rank) that is equal to or greater than the value, ie, satisfies Rank (H ″) ≧ Max (t, t ′), R ≧ q + 2r, and (R−q) is a multiple of 2, and γ Is the primitive element of the base 2 (Rq) / 2 quadratic extension GF (2 ^{(Rq) / 2} ), where γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b-1 ″)] is established, and Φ is additively converted from GF (2 ^q ) to GF (2 ^{(R 37. The} intra-byte multiple spotty byte error correction / detection method according to claim 33, which is a homomorphism to ^{-q) / 2} ). The spotty byte error control code is a (S _{t / b} + S _{t ′ / b} ) EC code having a function of correcting an error ( _{t / b} + _{t ′ / b} ),
The parity check matrix used for the (S _{t / b} + S _{t ′ / b} ) EC code is the following matrix H having R rows and N columns:

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1), a q × b binary matrix having a rank equal to or greater than 2t + 2t ′ or b, i.e., Rank, Rank (H ′) ≧ Min (2t + 2t ′, b) is satisfied, and the matrix H ″ is an r-th order represented by H ″ = [h ₀ ″, h ₁ ″,..., H _b−1 ″]. Is a binary matrix of r rows and b columns (r ≦ b) made up of column vectors h _j ″ (0 ≦ j ≦ b−1), and rank equal to or greater than t + t ′ or b. (Ra nk), that is, Rank (H ″) ≧ Min (t + t ′, b) is satisfied, R ≧ q + 3r, and (R−q) is a multiple of 3, and γ is based on 2 ( Rq) / 3 primitive field GF (2 ^{(Rq) / 3} ) primitive element, and γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″ _{^{), ···, γ i Φ (}} h b-1 ")] it is configured to establish, [Phi from under additive ^{GF (2 q) GF (2} (R-q) / 2) to 37. The intra-byte multi-spotty byte error correction / detection method according to claim 33, wherein the homomorphism is a homomorphism. The spotty byte error control code corrects two t / b errors and has a function of correcting one t ′ / b error (t <t ′). D _{t / b} EC-S _{t '/ B} EC code,
The parity check matrix used for the D _{t / b} EC-S _{t ′ / b} EC code is the following matrix H having R rows and N columns:

However, R ≧ q + 3r and (R−q) is a multiple of 3, and N = b (n + 1) + (R−q) / 3, 0 ≦ i ≦ n−1, n = 2 ^{(R −q) /} 3−1, and the matrix H ′ is a q-th order column vector h _j ′ (0 ≦ 0 ⁾ represented by H ′ = [h ₀ ′, h ₁ ′,..., H _b−1 ′]. j ≦ b−1) is a binary matrix of q rows and b columns (q ≦ b), and rank equal to or greater than the larger value of 4t or 2t ′ and the smaller value of b (Rank), that is, Rank (H ′) ≧ Min (Max (4t, 2t ′), b) is satisfied, and the matrix H ″ has H ″ = [h ₀ ″, h ₁ ″, .., H _b-1 ″] is an r-th column vector h _j ″ (0 ≦ j ≦ b−1) and is a binary matrix of r rows and b columns (r ≦ b), 2t Or t ', whichever is greater It has a rank (Rank) that is equal to or greater than the threshold value and whichever is smaller of b, that is, Rank (H ″) ≧ Min (Max (2t, t ′), b) is satisfied, and R ≧ q + 3r And (Rq) is a multiple of 3, and γ is the primitive element of (Rq) / 3-order extension GF (2 ^{(Rq) / 3} ) with 2 as the base, γ ⁱ H ″ = [γ ⁱ Φ (h ₀ ″), γ ⁱ Φ (h ₁ ″),..., γ ⁱ Φ (h _b−1 ″)] is established, and Φ is additive 37. A plurality of intra-byte spotty bytes according to any one of claims 33 to 36, which is a homomorphism from GF ( ^2q ) to GF (2 ^{(R-q) / 2} ) Error correction / detection method.   The error correction processing step generates a bit error pointer that detects which bit of the received word is incorrect based on the syndrome, and the error correction bit corresponds to the error bit based on the generated bit error pointer. 26. When an error in the received word is corrected by inverting the bit value of the received word, and when it is detected that the bit error in the received word cannot be corrected, an uncorrectable error detection signal is output. 41. The method for correcting and detecting a plurality of intra-byte spotty byte errors according to claim 40. The error correction processing step includes an H ′ decoding processing step, an H ″ multiplication processing step, a parallel decoding processing step on GF (2 ^r ), an error generation processing step on GF (2 ^b ), and an inversion processing step. 41. The method for correcting and detecting a plurality of intra-byte spotty byte errors according to claim 31, claim 32, claim 37, claim 38, claim 39, or claim 40. The H ′ decoding processing step generates a sum of errors (e _A ) for each byte based on the upper q bits of the syndrome generated in the syndrome generation processing step,
The H ″ multiplication processing step generates a product of the upper q bits of the syndrome and a transpose matrix of H ″ based on the sum of errors (e _A ) for each byte generated in the H ′ decoding processing step. And
The parallel decoding processing step on GF (2 ^r ) includes the product of the upper q bits of the syndrome generated in the H ″ multiplication processing step and the transpose matrix of H ″, and the syndrome generation processing step. A bit error pointer on GF (2 ^r ) based on the remaining lower bits except the upper q bits of the syndrome, and output when error correction is considered impossible in parallel decoding on GF (2 ^r ) Generating a first uncorrectable error detection signal,
The error generation processing step on the GF (2 ^b ) includes the sum of errors for each byte generated in the H ′ decoding processing step (e _A ) and the parallel decoding processing step on the GF (2 ^r ). the bit-error pointer on the GF ^{(2 r)} tHAT generated based on, by converting the error on GF ⁽² r) the error on GF ^{(2 b),} bits on GF ⁽² b) Generating an error pointer and a second uncorrectable error detection signal that is output when error correction is deemed impossible;
The reversal processing step, based on the bit error pointer on the GF (2 ^b) generated by the error vector generating process step of the on GF (2 ^b), the bit-error pointer on the GF (2 ^b) 43. The intra-byte multiple spotty byte error correction / detection method according to claim 42, wherein an error of the received word is corrected by inverting a bit value of the corresponding received word. In the error correction processing step, the first uncorrectable error detection signal generated in the parallel decoding processing step on the GF (2 ^r ) and the error generation processing step on the GF (2 ^b ) are generated. 44. The byte according to claim 43, further comprising: outputting a third uncorrectable error detection signal indicating that an error exceeding the correction capability is detected by calculating a logical sum of the second uncorrectable error detection signal. Multiple spotty byte error correction / detection method. The error generation processing step on GF (2 ^b )
An error byte detection processing step for detecting that the syndrome is non-zero;
A t-bit error correction decoding step of outputting one byte of the bit error pointer on the GF (2 ^b ) from one byte of the bit error pointer on the GF (2 ^r );
A bit-by-bit selection processing step for selecting an input signal according to a control signal;
45. The intra-byte multiple spotty byte error correction / detection method according to claim 43, further comprising a Hamming weight detection processing step for detecting a Hamming weight 1 of the input signal. The error generation processing step on the GF (2 ^b ) includes an error byte detection processing step, a t-bit error correction decoding processing step, a bit-by-bit selection processing step, and a Hamming weight detection processing step.
In the error byte detection processing step, 1 byte of a bit error pointer on the GF (2 ^r ) is input, and a 1-bit syndrome detection signal is output.
The t-bit error correction decoding processing step receives a predetermined one byte of the bit error pointer on the GF (2 ^r ) as an input, and corresponds to the predetermined one byte of the bit error pointer on the GF (2 ^b ). In addition to outputting 1 byte, it also outputs a detection signal that detects errors beyond the correction capability,
The bit-by-bit selection processing step selects each bit of the two input signals according to the control signal,
The Hamming weight detection processing step receives the syndrome detection signal output from the error byte detection processing step, calculates a Hamming weight of the input syndrome detection signal, and sets 1 when the Hamming weight is 1. 45. The intra-byte multi-spotty byte error correction / detection method according to claim 43, wherein the output is performed and 0 is output otherwise. In the t-bit error correction decoding processing step, the error exceeding the correction capability is not mapped from the error e ′ _I on the GF (2 ^r ) by the error e _I on the GF (2 ^b ). 47. The method for correcting and detecting a plurality of spotty byte errors in bytes according to claim 46. In the error generation processing step on the GF (2 ^b ), the detection signal output from the t-bit error correction decoding processing step is input to a multi-input OR gate circuit, and the multi-input OR gate circuit is input Outputting the second uncorrectable error detection signal based on the detection signal;
Further, in the error generation processing step on the GF (2 ^b ), the signal output from the Hamming weight detection processing step and the syndrome detection signal output from the error byte detection processing step are each a two-input AND gate. A signal input to the circuit and output from the 2-input AND gate circuit as the control signal used for the selection processing step for each bit,
In the bit-by-bit selection processing step, the signal output from the t-bit error correction decoding processing step and the error sum (e _A ) for each byte are selected according to the control signal, and the selected signals are collected. 48. The intra-byte multiple spotty byte error correction / detection method according to claim 47, wherein a bit error pointer on the GF (2 ^b ) is output.

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