JP2006100603A - Thin-film capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve yields and reliability by dispersing and reducing stress generated in a thin-film capacitor and restraining deterioration in leakage current characteristics. <P>SOLUTION: An interlayer insulating film 20 is formed so that it is located at the end of the upper electrode 18 of the thin-film capacitor and has a straight inclination 20A. More specifically, when distance from a point A to the end of the upper electrode 18 is set to L, and distance on the main surface of A-B is set at W; an inclination 20A in the interlayer insulating film 20 is formed so that a relation in a level of W/2>L is established, thus dispersing stress generated at the side of the thin-film capacitor along the inclination in the interface for escaping to the outside of the thin-film capacitor, and hence relaxing the concentration of a stress field generated inside the thin-film capacitor, and further suppressing deterioration in the leakage current characteristics. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an MIM (metal-insulator-metal) type thin film capacitor using, for example, a perovskite type high dielectric constant dielectric thin film, and more particularly to improvement of an element structure for reducing stress generated in the element. is there.

  Oxides classified as perovskite-type structures are generally well-known for having good high ferroelectricity, piezoelectricity, pyroelectricity, electro-optic effect, etc., and are indispensable in the field of electronic components. Material. In addition to bulk requirements, perovskite-type oxides with these characteristics have recently become more high-frequency, smaller, and more functional in consumer electronic devices such as mobile phones, personal digital assistants, and personal computers. There is a growing demand for thin films to meet the demands for manufacturing. In particular, since the 1980s, DRAM (Dynamic Random Access Memory) and MMIC (Monolithic Microwave Integrated Circuit) have been highly integrated and highly functionalized by utilizing the high dielectric constant of perovskite oxide thin films. In addition, development of ferroelectric thin film capacitors for memory cells using spontaneous polarization inversion for non-volatile RAM (FeRAM) has been actively promoted.

  In general, a thin film capacitor has a structure in which a lower electrode, a dielectric, and an upper electrode are sequentially stacked on a substrate, and then processed under general conditions in order from the upper layer. In particular, perovskite-type oxide dielectric thin films can be fabricated by sputtering, MOCVD (Metal Organic Chemical Vapor Deposition), molecular beam epitaxy (Molecular Beam) depending on the purpose such as process reproducibility, composition controllability, and process temperature reduction. Each method such as Epitaxy method is used properly.

  In order to apply the thin film capacitor produced through such a process to a thin film module, a passivation film such as a silicon oxide film or a silicon nitride film is formed after the capacitor is formed, or a connection hole formed in the plane of the organic interlayer insulating film. It is necessary to connect elements with metal wiring such as aluminum or copper via (via). For this reason, in the thin film module form, due to differences in physical properties (thermal expansion coefficient, Young's modulus, etc.) such as interlayer insulation films, connection holes, wiring, substrates, etc. Residual stress (Stress) is generated. In addition, it is known that when a thin film capacitor is used in a semiconductor device in the presence of a large stress, leakage current characteristic deterioration appears in the capacitor.

  More specifically, the leakage current in the MIM thin film capacitor is limited by the Schottky emission process that flows over the Schottky barrier formed at the interface between the dielectric thin film and the electrode interface on the low electric field side, and the dielectric current on the high electric field side. It is characterized by being limited to the bulk resistance of the thin film. Among these, it has been found that the heat emission current flowing over the Schottky barrier that is dominant on the low electric field side is greatly influenced by the stress acting on the interface and drastically changes the leakage current characteristics. As described above, when the leakage current characteristic is deteriorated, as a result, the thin film capacitor is likely to be electrically short-circuited, and finally, it becomes difficult to form a multilayer wiring, resulting in a decrease in yield. In addition, the stress remaining in the thin film capacitor is a factor that causes deterioration of the capacitor characteristics over time even through a thermal history in a practical environment, and avoidance of stress is indispensable for improving reliability. ing.

  As described above, the leakage current of a thin film capacitor using a dielectric thin film is sensitive to stress, and the influence of the stress remaining in the interlayer insulating film on the upper surface of the capacitor on the thin film capacitor cannot be ignored.

In order to eliminate the influence of stress from the thin film capacitor, there is a method of directly eliminating the residual stress in the interlayer insulating film. However, the interlayer insulating film capable of such stress control is limited to the SiO ₂ film formed by the CVD method, and the possibility of stress control is low in a general organic interlayer insulating film. Further, even in an interlayer insulating film having no stress at room temperature, stress is generated through a thermal history in the subsequent manufacturing process, and damage is accumulated in the thin film capacitor.

  As a conventional technique for suppressing stress, for example, there is a “ferroelectric element” described in Patent Document 1 below. However, this is intended to suppress the deterioration of the ferroelectric layer due to the stress caused by the expansion of the aluminum wiring due to the device structure, and is not related to the stress suppression by the interlayer insulating film. The “semiconductor device and manufacturing method thereof” described in Patent Document 2 below relates to current leakage, and there is no description or suggestion regarding stress suppression.

The present invention pays attention to the above points, and its purpose is to structurally reduce the stress generated in the thin film capacitor. Another object is to provide a structure in which stress is distributed so that it does not concentrate in a small area even if stress occurs. Still another object is to minimize the influence of stress on the Schottky barrier formed at the electrode / dielectric thin film interface, suppress the deterioration of the leakage current characteristics, and improve the yield and reliability.
JP 2000-243923 A JP 2003-282719 A

  In order to achieve the above object, the present invention provides a thin film capacitor having a substrate, a lower electrode, an insulating layer and an upper electrode, further comprising an interlayer insulating film on the upper surface, and the interlayer insulating film is exposed to the upper electrode. A connection hole is provided, and the connection hole is formed so that the stress peak of the interlayer insulating film is outside the position of the upper electrode.

  One form of the thin film capacitor is an MIM type capacitor formed by laminating a lower electrode, a dielectric layer, and an upper electrode in this order on the substrate, and the other form is the lower electrode, first electrode on the substrate. It is a MIIM type capacitor formed in the order of an insulating layer, a second insulating layer, and an upper electrode.

  One of the main aspects of the present invention is that the interface between the connection hole and the interlayer insulating film is a substantially straight inclined surface, and further, the inclination angle is 60 ° or less. Features. In another embodiment of the present invention, the interface between the connection hole and the interlayer insulating film is a curved inclined surface.

  Another aspect of the present invention is characterized in that an inclination angle of a straight line connecting an upper end portion and a lower end portion of the interface between the connection hole and the interlayer insulating film is 60 ° or less. Still another embodiment is characterized in that the midpoint of the upper end and the lower end of the interface between the connection hole and the interlayer insulating film is located outside the upper electrode of the thin film capacitor. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

  According to the present invention, since the connection hole is formed so that the stress peak of the interlayer insulating film on the upper surface of the thin film capacitor is outside the position of the upper electrode, the stress generated in the thin film capacitor is reduced and dispersed. As a result, deterioration of leakage current characteristics is suppressed, and yield and reliability are improved.

  Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

  First, Embodiment 1 which is a basic form of the present invention will be described with reference to FIG. FIGS. 1A and 1B both show a laminated structure of a thin film capacitor, and an insulator film 12, a lower electrode 14, a dielectric thin film 16, and an upper electrode 18 are laminated in this order on the main surface of the substrate 10. FIG. A capacitor or a capacitor is constituted by an MIM structure in which the dielectric thin film 16 is sandwiched between the upper and lower electrodes 14 and 18. The main surface is covered with an interlayer insulating film 20 except for the vicinity of the center of the upper electrode 18. In addition, the specific material and manufacturing method of each part are demonstrated in the Example mentioned later.

  Conventionally, as shown in FIG. 1B, a via hole 22 for connection is formed on the upper electrode 18, and the interface between the interlayer insulating film 20 and the via hole 22 is substantially vertical. In such a state, when thermally affected, the interface between the interlayer insulating film 20 and the via hole 22 is pulled in one of the directions indicated by the arrows, and stress is generated near the portion immediately below the interface indicated by the dotted line.

In order to avoid stress being transmitted to the thin film capacitor due to the structure and arrangement of the interlayer insulating film 20, in this embodiment,
(1) Even if stress is generated in the thin film capacitor portion, the stress is not concentrated, and the end of the interlayer insulating film 20 is inclined so that it is distributed over a wide range.
(2) Since a stress concentration field can be formed at the end of the interlayer insulating film 20, the inclined end is designed to be located outside the position directly above the upper electrode 18 of the thin film capacitor.
Thus, the deterioration of the leakage current characteristic of the thin film capacitor is suppressed.

  FIG. 1 (A) shows this state, and is an end portion of the upper electrode 18 of the thin film capacitor, has an approximately linear slope 20A, and an interlayer insulating film so that stress can escape to the outside. 20 is formed. More specifically, the lower end of the slope 20A is A, and the upper end is B. When the midpoint of AB connecting them is C, the point C is in a positional relationship such that it goes out from above the upper electrode 18 of the thin film capacitor. That is, when the distance from the point A to the end of the upper electrode 18 is L, and the distance on the main surface of AB is W, the interlayer insulation is such that the relationship of W / 2> L holds. An inclination 20A of the film 20 is formed.

  Next, the operation of this embodiment will be described. As is apparent from a comparison between FIGS. 1A and 1B, in this embodiment, the interface between the interlayer insulating film 20 and the via hole 22 is also inclined as compared with the prior art. For this reason, the stress generated on the thin film capacitor side at the interface is distributed along the inclination and escapes from the thin film capacitor. Therefore, the concentration of the stress field generated inside the thin film capacitor is relaxed, the influence of the stress on the Schottky barrier formed at the interface between the dielectric thin film 16 and the upper electrode 18 is minimized, and the leakage current characteristic is deteriorated. It will be suppressed. Furthermore, a thin film capacitor with less process damage can be provided, and yield and reliability can be improved.

  Note that the smaller the angle θ of the slope 20A of the interlayer insulating film 20, the higher the stress dispersion effect, and it is desirable that the angle θ be 60 ° or less. Stress can be dispersed even with a steep inclination exceeding 60 °, but it is not necessarily good.

Next, Example 2 will be described with reference to FIG. In addition, the same code | symbol is used for the component corresponding to Example 1 mentioned above. In the first embodiment described above, the linear slope 20A is provided in the interlayer insulating film 20. However, in this embodiment, a curved slope 20B is provided as shown in FIG. 2, and similarly, the center of the slope 20B is provided. Is removed from the upper electrode 18 of the thin film capacitor. More specifically, similarly, the lower end of the slope 20A is A, and the upper end is B. Then, the middle point of A-B connecting them with a straight line is C, and the intersection of the vertical line (perpendicular line) at the point C of the AB line and the inclination 20B of the interlayer insulating film 20 is D (center of the inclination 20B). The point relationship is such that the point D goes out from above the upper electrode 18 of the thin film capacitor. That is, when the distance from the point A to the end of the upper electrode 18 is L and the distance on the main surface of A−D is W _D , the interlayer insulating film is such that the relationship of W _D > L holds. Twenty slopes 20B are formed.

  According to this embodiment, the interface between the interlayer insulating film 20 and the via hole 22 is curved and inclined. For this reason, the stress generated on the thin film capacitor side at the interface is distributed along the inclination, and the concentration of the stress field generated in the thin film capacitor is relaxed as in the above embodiment.

  Also in this example, the inclination angle of the line AB is preferably 60 ° or less as in the first embodiment. If the degree of curvature of the slope 20B of the interlayer insulating film 20 is extremely large, the interface between the interlayer insulating film and the via hole 22 becomes similar to the conventional one shown in FIG. 1B, and stress tends to concentrate. Therefore, it is not preferable.

Next, Embodiment 3 will be described with reference to FIGS. This embodiment is a more specific example of the first or second embodiment described above, and compares a plurality of thin film capacitors having different interface shapes between via holes and interlayer insulating films as shown in FIG. In FIG. 3, an insulating layer 102 made of SiO ₂ or the like is formed on the main surface of the substrate 100 made of Si or the like. Next, on this insulating layer 102, a lower electrode 104 in which Pt and TiOx are laminated, a dielectric layer 106 mainly composed of BSTO (BaSrTiO ₃ ), and an upper electrode 108 made of Pt are laminated in this order. Thereafter, dry etching is sequentially performed from the upper layer, and the thin film capacitor is formed in a desired shape. After that, the thin film capacitor was subjected to recovery annealing for 30 minutes in an oxygen atmosphere at 600 ° C.

Next, on the main surface of the thin film capacitor obtained as described above, an interlayer insulating film 110 made of a P-TEOS SiO ₂ film serving as an interlayer insulation between the electrodes and as a passivation (protection) is formed. A film having a thickness of 3 μm was formed. Then, a positive resist is patterned and formed using a conventional photolithography process (not shown), and the interlayer insulating film 110 is dry-etched with a mixed etchant gas of CF ₄ + oxygen using the resist as a mask to form via holes. A considerable opening was made. As described above, by mixing oxygen with the etchant gas, it is possible to cause the resist to recede during etching so that the processed end shape of the interlayer insulating film 110 is inclined. The resist used as a mask at this time is removed using an ashing device after the processing of the interlayer insulating film 110 is completed. Subsequently, after a barrier layer and a seed layer (both not shown) are formed on the interlayer insulating film 110, a copper wiring portion is formed by plating, and this is processed by CMP (Chemical Mechanical Polishing) to form a via hole 112. 114 and other wiring layers were formed. Note that the interlayer insulating film 110 and the via holes 112 and 114 are denoted by reference numerals A to D to distinguish FIGS. 3A to 3D.

  FIG. 3A shows an example in which the interface between the interlayer insulating film 110A and the via holes 112A and 114A is substantially vertical. FIG. 3B shows an example in which the interface between the interlayer insulating film 110B and the via holes 112B and 114B is inclined by 45 °. FIG. 3C shows an example in which the interface between the interlayer insulating film 110C and the via holes 112C and 114C has a small inclination angle below the via hole and a large inclination angle above the via hole. FIG. 3D shows a bowl-shaped example in which the interface between the interlayer insulating film 110D and the via holes 112D and 114D is curved so that the inclination angle is small at the bottom of the via hole and the inclination angle is large at the top of the via hole.

  In each of the above examples, the stress distribution at the interface between the dielectric layer 106 and the upper electrode 108 immediately below the end of the via hole 114, that is, the portion indicated by the dotted line in the figure is calculated by simulation, and as shown in FIG. Results were obtained. 4A shows the X direction-stress, and FIG. 4B shows the XY direction-shear-stress. In both cases, the bottom end portion of the via hole 114 is set as a reference position, the outside of the via hole is plus, and the inside is minus.

  Comparing these graphs, the sample with a gentler inclination such as via holes 114B to 114D tends to have a smaller maximum stress value as compared with the sample of FIG. 3A in which the via hole 114A stands vertically. It can be seen that the stress tends to be dispersed.

  Note that, as in the example of FIG. 3B, when the slope of the processed end of the interlayer insulating film 110B is simply laid, the capacity (dimension) controllability of the thin film capacitor may be reduced. However, as shown in the examples in FIGS. 3C and 3D, the inclination angle is divided into two steps (or multiple steps), or a bowl-shaped curved shape is used. By reducing the taper of the insulating film 110 and increasing the taper toward the upper side of the via hole 114, it is possible to achieve both reduction of the maximum stress generated in the thin film capacitor and dimensional controllability.

  Next, Embodiment 4 will be described with reference to FIGS. When the capacitance of the thin film capacitor is extremely small, or when it is necessary to improve the breakdown voltage and reliability of the thin film capacitor, the simple multilayer MIM structure as in the above-described embodiments may not be able to cope with it. The present embodiment corresponds to this case, and has a structure in which the capacitor insulating layer has a two-layer structure so that only the effective capacitance control region has a concave shape, and the upper electrode is formed so as to cover the concave portion. ing.

  In FIG. 5, as in the third embodiment, an insulating layer 102 is formed on a substrate 100, and a lower electrode 104 and a dielectric layer 106 are sequentially stacked on the insulating layer 102.

In this embodiment, at this point, the dielectric layer 106 and the lower electrode 104 are processed so as to have a capacitor shape. Next, a capacitive insulating layer 200 made of SiO ₂ or the like is formed thereon, and a hole 202 is formed at a location where a thin film capacitor is to be formed, thereby setting an effective thin film capacitor region. Thereafter, the upper electrode 204 is formed so as to cover the hole 202 that will eventually become an effective thin film capacitor region, thereby completing the thin film capacitor forming step. If necessary, recovery annealing is performed on the completed thin film capacitor. As described above, in this embodiment, the capacitor insulating layer 200 having a low dielectric constant for controlling the capacitance is inserted under the upper electrode 204.

  Next, via holes 206 and 208 are formed on the main surface. Among these, the via hole 206 on the lower electrode side is the same in FIGS. 5A to 5C, and is connected to the lower electrode 104 through the holes in the interlayer insulating film 210 and the capacitor insulating layer 200. On the other hand, the via holes 208 </ b> A to 208 </ b> C on the upper electrode side have different attachment positions with respect to the upper electrode 204.

  First, in FIG. 5A, a via hole 208 A is connected to the upper electrode 204 at a position outside the region of the recess 205 corresponding to the hole 202 of the upper electrode 204. In FIG. 5B, the via hole 208B is connected to the upper electrode 204 so as to cover the concave portion 205 corresponding to the hole 202 of the upper electrode 204. The taper angle at the interface between the via hole 208 and the interlayer insulating film 210 is the same. FIG. 5C is a comparative example, in which a via hole 208C is connected to the upper electrode 204 so as to be located in the recess 205 corresponding to the hole 202 of the upper electrode 204, and an end portion of the interlayer insulating film 210 is It is located on the upper electrode 204.

5A and 5B, the end portions of the interlayer insulating films 210A and 210B are used as the upper electrode of the Pt (104) / BSTO (106) / Pt (204) laminated portion having a low breakdown voltage in the thin film capacitor. By removing from above 204, the influence of stress is reduced as in the above-described embodiment. The other Pt (104) / SiO ₂ (200) / BSTO (106) / Pt (204) laminated portions have a small capacity and a high breakdown voltage because SiO ₂ having a low dielectric constant is connected in series. Therefore, even if the end portions of the interlayer insulating films 210A and 210B are located, there is no particular inconvenience.

Next, a sample was prepared for each of the above examples, and leakage current characteristics were measured. FIG. 6 shows the measurement results. In the figure, the horizontal axis represents the applied voltage, and the vertical axis represents the leakage current value. Comparing FIGS. 5A to 5C, FIGS. 5A and 5C are thin film capacitor area> via hole area, and FIG. 5B is thin film capacitor area <via hole area. The leak current value is shown for each. According to this, the leakage current is smaller when the area of the via hole 208 on the main surface is larger than the capacitor area. This is because the large area of the via hole 208 means that the interface with the interlayer insulating film 210 is located at the end of the upper electrode 204, that is, outside, and thus the effect of effectiveness is reduced. Can do.
<Other embodiments>

In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) The materials and manufacturing methods of the respective parts shown in the above-described embodiments are examples, and known appropriate materials and appropriate manufacturing methods may be applied. For example, in the above embodiment, a BSTO thin film is used as the dielectric thin film material. However, the same effect has been confirmed for other strong and high dielectric thin film materials having a perovskite type structure, and the present invention also includes them. Applicable. Further, the interlayer insulating film is not limited to a single inorganic film, but may be a laminated film of an organic film and an inorganic film (for example, a SiO ₂ film and a PI film).
(2) The present invention is applicable to the case where an interlayer insulating film is formed on the upper surface of a thin film capacitor having a lower electrode, an insulating layer, and an upper electrode, and does not prevent the presence of other layers. .

  According to the present invention, since the stress due to the interlayer insulating film is reduced, it is effective for a thin film capacitor using an oxide classified into a perovskite structure, for example.

It is a figure which shows Example 1 of this invention, (A) is sectional drawing which shows the laminated structure of a present Example, (B) is sectional drawing which shows the laminated structure of a prior art example. 6 is a cross-sectional view showing a laminated structure of Example 2. FIG. 6 is a cross-sectional view showing a laminated structure of a sample of Example 3. FIG. It is a graph which shows the simulation result of the stress in the said Example 3. 6 is a cross-sectional view showing a laminated structure of a sample of Example 4. FIG. It is a gram which shows the measured value of the leakage current in the said Example 4.

Explanation of symbols

10: substrate 12: insulator film 14: lower electrode 16: dielectric thin film 18: upper electrode 20: interlayer insulating film 22: via hole 100: substrate 102: insulating layer 104: lower electrode 106: dielectric layer 108: upper electrode 110 : Interlayer insulating films 112 and 114: Via hole 200: Capacitance insulating layer 202: Hole 204: Upper electrode 205: Recess 206 and 208: Via hole 210: Interlayer insulating film

Claims (8)

A thin film capacitor having a substrate, a lower electrode, an insulating layer and an upper electrode,
Further, an interlayer insulating film is provided on the upper surface, and the interlayer insulating film is provided with a connection hole so as to be exposed to the upper electrode, and the stress peak of the interlayer insulating film is outside the position of the upper electrode. The thin film capacitor is characterized in that the connection hole is formed.   2. The thin film capacitor according to claim 1, wherein the thin film capacitor is an MIM type capacitor formed by laminating a lower electrode, a dielectric layer, and an upper electrode in this order on a substrate.   2. The thin film capacitor according to claim 1, wherein the thin film capacitor is a MIIM type capacitor formed on a substrate in the order of a lower electrode, a first insulating layer, a second insulating layer, and an upper electrode.   The thin film capacitor according to claim 1, wherein an interface between the connection hole and the interlayer insulating film is a substantially straight inclined surface.   The thin film capacitor according to claim 4, wherein an inclination angle of an interface between the connection hole and the interlayer insulating film is 60 ° or less.   The thin film capacitor according to claim 1, wherein an interface between the connection hole and the interlayer insulating film is a curved inclined surface.   The thin film capacitor according to claim 6, wherein an inclination angle of a straight line connecting an upper end portion and a lower end portion of the interface between the connection hole and the interlayer insulating film is 60 ° or less. The thin film according to any one of claims 4 to 7, wherein a middle point of an upper end portion and a lower end portion of an interface between the connection hole and the interlayer insulating film is located outside an upper electrode of the thin film capacitor. Capacitor.

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