JP2006100506A - Thin film semiconductor device, photoelectric device, electronic instrument, method of manufacturing thin film semiconductor device and thin film electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise voltage withstand property and reduce off leakage current, in a thin film semiconductor device such as TFT (Thin Film Transistor) or the like, for example. <P>SOLUTION: A semiconductor film comprises a channel region and a source region as well as a drain region, into both of which impurity is doped and which are provided with an island-type plane pattern, and a gate electrode arranged so as to be opposed to the channel region through a gate insulating film. The concentration of the impurity in a first part neighbored to at least the channel region among the peripheral regions of the island-type plane patterns in respective source region and drain region is lower compared with a central region excluding a second part, excluding the peripheral region and neighbored to the channel region along the channel region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technical field of a thin film semiconductor device such as a thin film transistor (hereinafter referred to as TFT as appropriate), a liquid crystal device including the thin film semiconductor device, an electro-optical device such as an organic EL (Electro-Luminescence) device, and various electronic devices. . Further, the present invention relates to a manufacturing method of such a thin film semiconductor device and a technical field of a thin film electronic device such as a capacitor.

  In this type of thin film semiconductor device, for example, at the time of manufacture, the semiconductor film is formed so as to have an island-like plane pattern on the substrate, the gate insulating film is formed thereon, and the gate electrode is further formed thereon. The Here, the coverage of the gate insulating film formed on the edge portion (that is, the pattern edge portion) of the semiconductor film having an island-like planar pattern is particularly large or small. For this reason, in such an edge portion, the withstand voltage between the gate electrode opposed to the gate insulating film and the channel region and the source and drain regions adjacent to the channel electrode is reduced, and the off-leakage current is increased. It is known. In order to improve the coverage of such a gate insulating film, a technique has been proposed in which a semiconductor film is tapered at an edge portion (see Non-Patent Document 1, Patent Document 1, etc.).

(IEEE Trans. On Electron Devices, vol.ED-25, No. 8 (1978) pp. 971-978) JP 2004-6951 A

  However, according to the technique of Non-Patent Document 1, since the coverage of the oxide film on the island-like planar pattern of the semiconductor film is poor, when performing impurity diffusion, the channel region is adjacent to the source region or the drain region. At the edge portion of the semiconductor film at the location, impurities enter the semiconductor film in a V shape from the side of the gate electrode. As a result, in the portion along the edge portion of the semiconductor film constituting the channel region, the distance between the source region and the drain region is substantially shortened, and the withstand voltage resistance between the source and the drain is lowered. There is.

  Further, according to the technique of Patent Document 1, it may be possible to improve the coverage of the gate electrode by adopting a tapered shape, but at the edge portion of the semiconductor film in the channel region adjacent to the source region or the drain region. The gate voltage is also applied to the tapered region where the gate electrodes overlap. For this reason, it is inevitable that the withstand voltage is lowered in the vicinity of the tapered region, and there is a technical problem that off-leakage current is generated to a degree that cannot be ignored.

  Accordingly, the present invention has been made in view of the above problems, and is a thin film semiconductor device such as a TFT having excellent voltage resistance and reduced off-leakage current, for example, a liquid crystal device and an organic EL device provided with the same. It is an object of the present invention to provide an electro-optical device and an electronic apparatus such as a thin film semiconductor device, a method for manufacturing such a thin film semiconductor device, and a thin film electronic device such as a capacitor having excellent voltage resistance.

  In order to solve the above problems, a thin film semiconductor device of the present invention has a semiconductor film having an island-like planar pattern including a channel region and a source region and a drain region doped with impurities, and a gate insulating film in the channel region. And the source region and the drain region are a peripheral region along the outer periphery of the semiconductor film and a second portion adjacent to the channel region along the channel region. And a central region surrounded by the peripheral region and the second portion, and in at least one of the source region and the drain region, at least a first of the peripheral regions adjacent to the channel region. The portion has a lower impurity concentration than the central region.

  According to the thin film semiconductor device of the present invention, the semiconductor film is made of, for example, a polysilicon film, an amorphous silicon film, or the like, and has an island-like planar pattern such as a rectangle. The gate electrode is made of, for example, a conductive polysilicon film, a conductive metal film, or the like, and is disposed to face the channel region of such a semiconductor film via a gate insulating film. The gate insulating film is made of, for example, a silicon oxide film, a thermal oxide film, a silicon nitride film, or the like. Here, in particular, the semiconductor film has a peripheral region of the island-like planar pattern, that is, an “outer edge portion” or “pattern edge portion” along the outer edge of the semiconductor film. In the peripheral region of such an island-like planar pattern, the coverage of the gate insulating film is large or small and is bad. In particular, among these peripheral regions, the three-layer structure composed of the semiconductor layer, the gate insulating film, and the gate electrode is liable to hinder the voltage resistance. It is a crossing point. That is, at this point, the film quality of the gate insulating film is basically poor due to the level difference of the semiconductor film, and the distance between the gate electrode and the source region or the drain region is close, and it is three-dimensionally viewed. In addition, since the edge portion of the semiconductor film in the peripheral region is angular toward the gate insulating film toward the gate electrode, electric field concentration is likely to occur.

  However, according to the present invention, in at least one of the source region and the drain region, at least the first portion adjacent to the channel region in the peripheral region has a lower impurity concentration than other portions of the semiconductor film. Specifically, the first portion has a lower impurity concentration than the central region of the semiconductor film. Here, the “central region” is a region of the semiconductor film excluding the peripheral region and excluding the second portion adjacent to the channel region along the channel region. That is, the central region typically corresponds to the main part of the source region occupying most of the source region near the center in plan view, or instead of or in addition to the main region of the source region. It corresponds to the main part of the drain region that occupies most. In the first portion, the semiconductor film has a low impurity concentration, and is preferably hardly doped with impurities as in the channel region and the LDD region described later. In this way, the structure in which the concentration of the impurity in the first portion is low can be obtained in the manufacturing process, for example, by doping the impurity into the central region while masking the first portion.

  As described above, the impurity concentration is lowered as the first portion of the portion where the withstand voltage is most likely to be disturbed in the peripheral region. That is, in the first portion, the semiconductor film functions as an insulating film in the edge portion of the source region and the drain region rather than the conductive film or the semiconductor film forming the source region or the drain region. In other words, it can be said that the insulating function by the gate insulating film is supplemented in the first portion having a low impurity concentration, that is, a high resistance, at a place where the breakdown voltage is most likely to be disturbed.

  Therefore, even if the coverage of the gate insulating film is locally poor near the first portion, the withstand voltage here is significantly increased. For this reason, off-leakage current is reduced. In addition, “electric field concentration” due to the angularity of the semiconductor film in the peripheral region is significantly reduced at least in the first part. Therefore, even if the coverage of the gate insulating film is not bad, it is possible to effectively avoid a situation in which the withstand voltage is lowered due to electric field concentration. That is, the withstand voltage can be improved extremely efficiently regardless of whether the coverage in the gate insulating film is good or bad.

  As a result, a thin film semiconductor device such as a thin film transistor having excellent voltage resistance and reduced off-leakage current can be realized. At this time, it is possible to avoid a situation in which impurities enter the semiconductor film in a V shape near the tapered shape of the semiconductor film as in the technique of Non-Patent Document 1. In addition, a situation in which the withstand voltage decreases near the tapered shape of the semiconductor film as in the technique of Patent Document 1 can be avoided.

  In the present invention, “at least the first portion of the peripheral region has a low impurity concentration” means that the impurity concentration of the first portion of the peripheral region that is most likely to interfere with the voltage resistance is low. This is because the effect of the present invention can be obtained. Therefore, the same effect can of course be obtained even if the semiconductor film is configured so that the concentration of impurities is low all over the peripheral region, that is, along the outer edge portion or the pattern edge portion. Which of the peripheral regions including the first portion should be determined in consideration of easiness in manufacturing or the like, for example, to reduce the impurity concentration.

  In one aspect of the thin film semiconductor device of the present invention, the impurity concentration of the peripheral region is lower than that of the central region.

  According to this aspect, the concentration of impurities in the peripheral region of the semiconductor film is low not only in the first portion, but also in the peripheral region away from the gate electrode, preferably over the entire periphery. Therefore, “electric field concentration” due to the angularity of the semiconductor film in the peripheral region away from the gate electrode is also significantly reduced due to the presence of the low impurity concentration in the angular part.

  In one aspect of the thin film semiconductor device of the present invention, the thin film semiconductor device is configured as an LDD (Lightly Doped Drain) type thin film transistor, and the second portion is an LDD region, which is compared with the central region. The impurity concentration is low.

  According to this aspect, in the LDD type thin film transistor, the voltage resistance can be improved, and the off-leak current can be reduced. Furthermore, even if the first portion and the second portion are doped at a concentration as low as that of the LDD region, the effects of the present invention can be obtained. Therefore, the first and second portions are formed on the same occasion as the formation of the LDD region. Forming at least one of the parts, more preferably both, is advantageous in the manufacturing process.

  In another aspect of the thin film semiconductor device of the present invention, the thin film semiconductor device is configured as a double-gate thin film transistor having two gate electrodes arranged in parallel as the gate electrode, and is planar in the semiconductor film. In the inter-gate region occupying the space between the two gate electrodes, at least a third portion of the peripheral region adjacent to the channel region has a lower impurity concentration than the central region.

  According to this aspect, the concentration of the impurity is lowered as the third part in the same manner as the first part in the part where the withstand voltage is most likely to be disturbed in the inter-gate region of the semiconductor film. Thus, in a double-gate thin film transistor, withstand voltage can be improved and off-leakage current can be reduced.

  In this aspect, the thin film semiconductor device is configured as a double gate type and LDD (Lightly Doped Drain) type thin film transistor, and a fourth portion adjacent to the channel region in the inter-gate region includes: The region may be an LDD region, and the impurity concentration may be lower than that of the central region.

  With this configuration, in the LDD-type and double-gate type thin film transistor, the voltage resistance can be improved, and the off-leak current can be reduced. Furthermore, in addition to the first and second portions, the effects of the present invention can be obtained even if the third and fourth portions are regions doped as low as the LDD region. Therefore, it is advantageous in the manufacturing process if at least one of the first to fourth portions, more preferably all of them are formed on the same occasion as forming the LDD region.

  Alternatively, in this aspect, the thin film semiconductor device is configured as a double gate type and LDD (Lightly Doped Drain) type thin film transistor, and the inter-gate region covers the entire area compared to the central region. The impurity concentration may be low.

  With this configuration, in the LDD-type and double-gate type thin film transistor, the voltage resistance can be improved, and the off-leak current can be reduced. Furthermore, in addition to the first and second portions, the effect of the present invention can be obtained even if the inter-gate region is a region doped as low as the LDD region. Therefore, if at least one of the first and second portions and the inter-gate region, more preferably all of them are formed on the same occasion as the formation of the LDD region, it is advantageous in the manufacturing process.

  In another aspect of the thin film semiconductor device of the present invention, the thin film semiconductor device includes a capacitor electrode formed by extending at least one of the source region and the drain region, and a dielectric on the capacitor electrode. And a storage capacitor having the other capacitor electrode arranged opposite to each other with a film interposed therebetween, and a fifth portion of the peripheral region located on the outer periphery of the one capacitor electrode is the one capacitor electrode. The concentration of the impurity is lower than the portion excluding the fifth portion in FIG.

  According to this aspect, the concentration of the impurity is lowered as the fifth portion in the semiconductor film constituting one of the capacitor electrodes, where the possibility that the breakdown voltage is most likely to be disturbed is the fifth portion. Therefore, one capacitor electrode is connected to the source region or drain region of the thin film transistor, and it is possible to construct a capacitor or a storage capacitor having excellent voltage resistance and off-leakage current characteristics.

  The other capacitor electrode may be configured so that its planar shape is slightly larger than that of the one capacitor electrode. With this configuration, since the semiconductor film constituting one capacitor electrode is angular toward the other capacitor electrode, the portion most likely to interfere with the withstand voltage is the fifth part. The withstand voltage can be improved without fail.

  In this aspect, the other capacitor electrode may be formed from the same layer as the gate electrode, and the dielectric film may be formed from the same layer as the gate insulating film.

  With this configuration, one capacitor electrode can be formed at the same opportunity as the source and drain regions in the semiconductor film, and the other capacitor electrode can be formed at the same opportunity as the gate electrode. Since the film can be formed on the same occasion as the gate insulating film, it is very advantageous in the manufacturing process.

  In order to solve the above problems, an electro-optical device of the present invention includes a plurality of pixels each including the above-described thin film semiconductor device according to the present invention (including various aspects thereof) and a display element controlled by the thin film semiconductor device. And a wiring electrically connected to the thin film semiconductor device for driving the plurality of pixel portions.

  According to the electro-optical device of the present invention, each thin film semiconductor device of the present invention, which has excellent voltage resistance and excellent off-leakage current characteristics, in each pixel portion, for example, a display element such as a liquid crystal element or an organic EL element. Thus, various types of driving such as active matrix control, switching control, drive control, and selection control can be performed, so that high-quality image display can be realized.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention, a video of a television, a mobile phone, an electronic notebook, a word processor, a viewfinder type or a monitor direct view type capable of displaying a high-quality image. Various electronic devices such as a tape recorder, a workstation, a videophone, a POS terminal, a touch panel, and an image forming apparatus such as a printer, a copy, and a facsimile using an electro-optical device as an exposure head can be realized. In addition, as an electronic apparatus according to the present invention, for example, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display) can be realized.

  In order to solve the above problems, a method of manufacturing a thin film semiconductor device of the present invention includes a step of forming a semiconductor film having an island-like planar pattern on a substrate, a step of forming a gate insulating film on the semiconductor film, An LDD (Lightly Doped Drain) region before and after the step of forming a gate electrode on the gate insulating film, the step of doping impurities at a low concentration via the gate electrode, and the step of doping impurities And a step of performing impurity doping at a high concentration while simultaneously masking both the region to be and the peripheral region of the island-like planar pattern at least the first portion adjacent to the channel region.

  According to the method for manufacturing a thin film semiconductor device of the present invention, first, for example, a substrate such as a semiconductor substrate, a quartz substrate, or a glass substrate is prepared. Thereafter, a semiconductor film having an island-like planar pattern is formed on the substrate from, for example, a polysilicon film or an amorphous silicon film. Thereafter, a gate insulating film is formed on the semiconductor film from, for example, a silicon oxide film, a thermal oxide film, a silicon nitride film, or the like. Thereafter, a gate electrode is formed on the gate insulating film from, for example, a conductive polysilicon film or a conductive metal film. Thereafter, a predetermined type of impurity depending on whether the thin film transistor to be constructed is N-type or P-type is doped at a low concentration through this gate electrode. That is, a channel region is formed in a region facing the gate electrode by self-alignment. Before or after the low-concentration impurity doping, a single mask is formed to mask, for example, a region to be an LDD region and the first portion. Then, a predetermined type of impurity is doped at a high concentration in a state where both the region to be the LDD region and the first portion are simultaneously masked. Thereby, a source region and a drain region are formed.

  Accordingly, the formation of the first portion that brings about an effect peculiar to the present invention and the formation of the LDD region for manufacturing the LDD type thin film transistor can be performed using a common mask. That is, as compared with the case of manufacturing a normal LDD type thin film transistor, it is not necessary to increase the manufacturing process, which is very convenient in practice.

  In order to solve the above problems, a thin film electronic device of the present invention includes a first film formed of a semiconductor film including an impurity region doped with an impurity and having an island-like planar pattern, and above or below the impurity region. A conductive second film having a predetermined plane pattern disposed opposite to each other with an insulating film interposed therebetween, and at least the second film in a peripheral region of the island-shaped plane pattern in the first film The peripheral facing portion disposed opposite to the first portion has a lower impurity concentration than portions other than the peripheral facing portion in the first film.

  According to the thin film electronic device of the present invention, the first film is made of, for example, a polysilicon film, an amorphous silicon film, or the like, and has an island-like planar pattern such as a rectangle. The second film is made of, for example, a conductive polysilicon film, a conductive metal film, or the like, and is disposed opposite to the first film via an insulating film. The insulating film is made of, for example, a silicon oxide film, a thermal oxide film, a silicon nitride film, or the like. Here, in particular, the first film has a peripheral region of an island-like planar pattern, that is, an “outer edge portion” or “pattern edge portion” along the outer edge of the first film. In the peripheral region of such an island-like planar pattern, the coverage of the insulating film is large or small and is bad. In particular, among these peripheral regions, the three-layer structure composed of the first film, the insulating film, and the second film is likely to interfere with the voltage resistance. It is a part to do. That is, at this point, the film quality of the insulating film is basically poor due to the step of the first film, and the edge portion of the first film is angular toward the insulating film side toward the second film. Concentration is also likely to occur.

  However, in the present invention, the concentration of impurities in the peripherally facing portion of the first film is lower than in other parts of the first film. As described above, the concentration of the impurity is lowered as a peripherally facing portion in a portion where the breakdown voltage is most likely to be disturbed in the peripheral region. That is, in the peripheral facing portion, the semiconductor film functions as a film close to an insulating film rather than a conductive film or a semiconductor film. In other words, it can be said that the insulating function by the insulating film is supplemented in the peripherally facing portion having a low impurity concentration, that is, a high resistance, at a place where the withstand voltage is most likely to be disturbed.

  Therefore, even if the coverage of the insulating film is locally poor in the vicinity of the peripheral facing portion, the withstand voltage here is significantly increased. In addition, “electric field concentration” due to the angularity of the first film in the peripheral facing portion is also significantly reduced. Therefore, even if the coverage of the insulating film is not bad, it is possible to effectively avoid a situation where the withstand voltage is lowered due to electric field concentration. That is, the withstand voltage can be improved extremely efficiently regardless of whether the coverage in the insulating film is good or bad.

  As a result of the above, various thin film electronic devices such as capacitors and storage capacitors that have excellent voltage resistance and have a basic structure that allows other wires and electrodes to pass through the insulating film on the electrodes and wires, for example, are realized. it can.

  In one aspect of the thin film electronic device of the present invention, the first film has one capacitor electrode in the impurity region, the second film has the one capacitor electrode, and the insulating film is a dielectric film. As the other capacitor electrode arranged opposite to each other.

  According to this aspect, it is possible to realize a capacitor or a storage capacity that is excellent in voltage resistance.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

(First Embodiment of Thin Film Semiconductor Device)
A first embodiment of a thin film semiconductor device of the present invention will be described with reference to FIGS. In this embodiment, the present invention is applied to a self-aligned and top-gate TFT.

  First, the structure of a TFT as a thin film semiconductor device of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a TFT according to the present embodiment, FIG. 2 is a B-B ′ cross-sectional view thereof, and FIG. 3 is a C-C ′ cross-sectional view thereof.

  1 to 3, the TFT includes a channel region 401C, an impurity-doped source region 401S and a drain region 401D on the element substrate 10, a semiconductor film 401 having an island-like planar pattern, and a channel region. 401C is provided with a gate electrode 403 arranged to face each other with a gate insulating film 402 interposed therebetween. The element substrate 10 is made of a glass substrate, a quartz substrate, a semiconductor substrate, a resin substrate, or the like. The semiconductor film 401 is made of a low temperature polysilicon film, a high temperature polysilicon film, an amorphous silicon film, a single crystal film, or the like. The source region 401S and the drain region 401D are doped with a predetermined concentration of impurities such as P (phosphorus) and B (boron) at a high concentration depending on whether the TFT is an N-channel type or a P-channel type. Thus, it is configured to have conductivity. Further, source and drain electrodes (not shown) or wirings are connected to the source region 401S and the drain region 401D, respectively. The gate insulating film 402 is composed of an insulating film having a single layer structure or a multilayer film structure such as a silicon oxide film, a silicon nitride film, or a thermal oxide film. The gate electrode 403 is composed of a conductive polysilicon film, a conductive metal film, or the like.

  In the present embodiment, in particular, the peripheral region 412 of the island-like planar pattern in each of the source region 401S and the drain region 401D includes the first portion 412e adjacent to the channel region 401C, and the impurity concentration compared to the central region 411. Is low. The central region 411 is configured to have conductivity that functions as a source and a drain in the source region 401S and the drain region 401D, respectively. The central region 411 excludes the peripheral region 412 in each of the source region 401S and the drain region 401D, and is adjacent to the channel region 401C along the channel region 401C (extending in the vertical direction in FIG. 1). It is an area excluding a part. In the present embodiment, the second portion has a high impurity concentration like the central region 411, and may be considered as a part of the central region 411.

  Next, with reference to FIG.4 and FIG.5, the effect | action of this embodiment comprised as mentioned above is demonstrated. 4A is a partial enlarged cross-sectional view of the vicinity of a portion corresponding to the peripheral region 412 (first portion 412e) of the semiconductor film 401 of FIG. 3 in one comparative example, and FIG. FIG. 4 is a partial enlarged cross-sectional view in the vicinity of a peripheral region 412 (first portion 412e) of the semiconductor film 401 of FIG. 3 in a specific example of the present embodiment. FIG. 5A is a partial enlarged cross-sectional view of the vicinity of a portion corresponding to the peripheral region 412 (first portion 412e) of the semiconductor film 401 of FIG. 3 in another comparative example, and FIG. It is a partial expanded sectional view of the peripheral region 412 (1st part 412e) vicinity of the semiconductor film 401 of FIG. 3 in the other specific example of a form.

  4A, in one comparative example, a semiconductor layer 401 ′, a gate insulating film 402 ′, and a gate electrode 403 are formed on the element substrate 10 in the same manner as the configuration of the present embodiment shown in FIGS. However, in the semiconductor film 401 ′, the peripheral region 412 or the first portion 412e in which the impurity concentration is lowered is not provided. That is, the peripheral region of the semiconductor film 401 ′ in the source region and the drain region is doped with a high concentration in the same manner as the central region. Accordingly, in one comparative example, the coverage of the gate insulating film 402 ′ is poor in the peripheral region along the outer edge of the semiconductor film 401 ′, that is, the “outer edge portion” or “pattern edge portion” (in FIG. 4A). , Part 501a). In this portion 501a, the film quality of the gate insulating film 402 ′ is basically poor due to the step of the semiconductor film 401 ′, and the distance between the gate electrode 403 and the semiconductor film 401 ′ is close, so that the withstand voltage property is improved. It is easy to get in trouble. In addition, since the edge portion of the semiconductor film 401 ′ is angular toward the gate insulating film 402 ′ toward the gate electrode 403, electric field concentration is likely to occur.

  As shown in FIG. 4B, also in one specific example of this embodiment, similarly, in the peripheral region 412, the coverage of the gate insulating film 402 is poor (see the portion 501b in FIG. 4B). Of the peripheral region 412 of the semiconductor film 401, the voltage resistance is likely to be hindered by the first portion 412e and the gate, which are portions of the semiconductor film 401 close to each other through the gate insulating film 402 in the portion 501b. This is a part of the electrode 403. However, in the present embodiment, the first portion 412 e has a lower impurity concentration as a part of the peripheral region 412 than other portions of the semiconductor film 401. Preferably, the peripheral region 412 including the first portion 412e is hardly doped with impurities as in the channel region 401C. Accordingly, the semiconductor film 401 functions as an insulating film in the peripheral region 412 including the first portion 412e. In other words, the insulating function of the gate insulating film 402 is supplemented by the high resistance first portion 412e for the portion most likely to interfere with the withstand voltage (see the portion 501b in FIG. 4B).

  Thus, according to the present embodiment, unlike the case of one comparative example, even if the coverage of the gate insulating film 402 is locally poor near the first portion 412e, as in the case of one comparative example, The withstand voltage here is significantly increased. For this reason, off-leakage current is reduced.

  In FIG. 5A, another comparative example is similar to the configuration of the present embodiment shown in FIGS. 1 to 3 on the element substrate 10, on the semiconductor layer 401 ″, the gate insulating film 402 ″, and the gate electrode 403. However, in the semiconductor film 401 ″, the peripheral region 412 or the first portion 412e in which the impurity concentration is lowered is not provided. However, in another comparative example, one comparison shown in FIG. Unlike the case of the example, in the peripheral region along the outer edge of the semiconductor film 401 ″ ′, the coverage of the gate insulating film 402 ″ is not bad. That is, the gate insulating film 402 ″ has no defect in the film thickness and shape. Absent. However, also in this case, the withstand voltage is reduced due to the electric field concentration in the portion 502a that is square on the gate insulating film 402 ″ side of the semiconductor film 401 ″. For this reason, dielectric breakdown as indicated by an arrow 503a is likely to occur compared to other portions of the semiconductor film 401 ″.

  As shown in FIG. 5B, similarly in other specific examples of this embodiment, electric field concentration is relatively likely to occur at a portion 502b that is square on the gate insulating film 402 side of the semiconductor film 401. However, the first portion 412e is a part of the peripheral region 412, and has a lower impurity concentration than other portions of the semiconductor film 401. The semiconductor film 401 includes an insulating film in the peripheral region 412 including the first portion 412e. Function as. Therefore, the dielectric breakdown as indicated by the arrow 503b due to the electric field concentration is much less likely to occur due to the gate insulating film 402 and the first portion 412e than in the case of FIG.

  As described above, according to the present embodiment, even if the coverage of the gate insulating film 402 is good in the vicinity of the first portion 412e as in the case of the other comparative examples, unlike the case of the other comparative examples, The withstand voltage increases significantly. For this reason, off-leakage current is reduced.

  In this embodiment, since the impurity concentration of the peripheral region 412 other than the first portion 412e is also low and the resistance is high, the semiconductor film 401 is angular in the peripheral region 412 away from the gate electrode 403. Also, the “electric field concentration” due to the presence (see FIG. 5) is remarkably reduced by the presence of the high resistance peripheral region 412 in the angular portion.

  As a result, according to the present embodiment, it is possible to realize a TFT having excellent voltage resistance and reduced off-leakage current.

(Method for Manufacturing First Embodiment of Thin Film Semiconductor Device)
Next, a manufacturing method of the TFT according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 6 is a process chart illustrating the manufacturing method of the TFT according to the first embodiment in order as a cross-sectional view at a location corresponding to FIG. 2, and FIG. 7A is a process chart of FIG. ) Is a perspective view showing the laminated structure on the substrate in the state of FIG. 7, and FIG. 7B is a perspective view showing the laminated structure on the substrate in the state of step (6) in FIG.

  In FIG. 6, first, in step (1), after a semiconductor film is formed on the element substrate 10 by CVD (Chemical Vapor Deposition), epitaxial growth, bonding, or the like, a predetermined plane is formed by patterning using photolithography and etching. A semiconductor film 401 having a pattern (see FIG. 1) is formed.

  Thereafter, in step (2), the gate insulating film 402 is formed on one surface of the element substrate 10 by thermal oxidation, CVD, or the like. However, the gate insulating film 402 can be removed at portions other than the portion covering the semiconductor film 401.

  Thereafter, in step (3), after forming a film to be the gate electrode 403 on one surface of the element substrate 10 by CVD, PVD, sputtering, or the like, the gate having a predetermined plane pattern is formed by patterning using photolithography and etching. An electrode 403 (see FIG. 1) is formed. As a result, a laminated structure before impurity doping is obtained on the element substrate 10 as shown in FIG.

  Thereafter, in step (4), a positive or negative photosensitive resist 601a is formed on the entire surface of the element substrate 10, and in step (5), exposure, development, baking, and the like using a mask are performed. A resist 601b having a pattern as illustrated in FIG. This pattern is formed so as to cover the peripheral region 412 including the first portion 412e. Note that the resist 601b may also be formed over the gate electrode 403.

  Thereafter, in the step (6), as shown in FIG. 7B, the high-concentration impurity 611 is doped using the resist 601b as a mask. Thus, the resistance of the central region 411 is reduced, so that the source region 401S and the drain region 401D each having conductivity are formed. At this time, the impurity 611 is hardly doped in the peripheral region 412 covered with the resist 601b and the channel region 401C covered with the gate electrode 403. That is, the peripheral region 412 and the channel region 401C remain as extremely high resistance semiconductor films that are almost the same as those formed in the step (1). Thereafter, the resist 601b is removed, and a subsequent process such as cleaning is performed.

  As a result, the TFT according to the first embodiment is manufactured relatively efficiently and easily.

(Second Embodiment of Thin Film Semiconductor Device)
A second embodiment of the thin film semiconductor device of the present invention will be described with reference to FIG. In the present embodiment, as in the case of the first embodiment, the present invention is applied to a self-aligned and top-gate TFT. However, unlike the first embodiment, the second embodiment is constructed as a double-gate TFT. FIG. 8 is a plan view of the TFT according to this embodiment. In FIG. 8, the same components as those in the first embodiment described with reference to FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 8, the TFT has two gate electrodes 403 a and 403 b arranged in parallel as gate electrodes on the element substrate 10. The peripheral region 412 including the third portion 413e in the inter-gate region occupying the space between the two gate electrodes 403a and 403b in the semiconductor film 401 in a plan view has an impurity concentration compared to the central region 411. Low. About another structure, it is the same as that of the case of 1st Embodiment.

  Therefore, according to the second embodiment, the impurity concentration of the third portion 413e, which is the most likely to disturb the withstand voltage in the region between the gates of the semiconductor film 401, is also reduced and the resistance is increased. Yes. Therefore, withstand voltage can be improved in a double-gate TFT, and off-leakage current can be reduced.

(Third Embodiment of Thin Film Semiconductor Device)
A third embodiment of the thin film semiconductor device of the present invention will be described with reference to FIG. In the present embodiment, as in the case of the first embodiment, the present invention is applied to a top gate type TFT. However, unlike the first embodiment, the second embodiment is constructed as an LDD type TFT. FIG. 9 is a plan view of the TFT according to this embodiment. In FIG. 9, the same components as those in the first embodiment described with reference to FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 9, the TFT includes LDD regions 451 and 452 along a channel region located immediately below the gate electrode 403 in the semiconductor film 401 and adjacent to the channel region. The LDD regions 451 and 452 correspond to an example of a “second portion” according to the present invention, that is, a region along the channel region 401C and adjacent to the channel region 401C. The concentration is low. About another structure, it is the same as that of the case of 1st Embodiment.

  Therefore, according to the third embodiment, the withstand voltage can be improved and the off-leak current can be reduced in the LDD type TFT.

(Method for Manufacturing Third Embodiment of Thin Film Semiconductor Device)
Next, a manufacturing method of the TFT according to the third embodiment configured as described above will be described with reference to FIG. FIG. 10 is a process chart sequentially illustrating the TFT manufacturing method according to the third embodiment as a cross-sectional view corresponding to FIG. 2, and FIG. 11 is a state of process (6) in FIG. It is a perspective view which shows the laminated structure on the board | substrate in. In FIGS. 10 and 11, the same components as those in the first embodiment described with reference to FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 10, steps (1) to (3) are performed in the same manner as in the manufacturing method according to the first embodiment shown in FIG.

  When the layered structure before impurity doping as shown in FIG. 7A is obtained on the element substrate 10 in step (3) of FIG. 10, subsequently, low-concentration impurities for forming the LDD regions 451 and 452 are formed. 612 is doped. As a result, in the semiconductor film 401, the region 401P other than the channel region 401C is a region doped with the impurity 612 at a low concentration.

  Thereafter, step (4) is performed in the same manner as in the manufacturing method according to the first embodiment shown in FIG.

  Thereafter, in step (5), a resist 601bb having a pattern as illustrated in FIG. 11 is formed by exposure using a mask, development, baking, and the like. This pattern is formed so as to cover the peripheral region 412 and the LDD regions 451 and 452. Note that a resist 601bb is also formed over the gate electrode 403.

  Thereafter, in step (6), as shown in FIG. 11, doping with a high-concentration impurity 611 is performed using the resist 601bb as a mask. Thus, the resistance of the central region 411 is reduced, so that the source region 401S and the drain region 401D each having conductivity are formed. At this time, the impurity 611 is hardly doped in the peripheral region 412 covered with the resist 601bb, the LDD regions 451 and 452, and the channel region 401C covered with the gate electrode 403. That is, the channel region 401C remains as an extremely high resistance semiconductor film that is almost the same as that formed in the step (1). On the other hand, the peripheral region 412 and the LDD regions 451 and 452 remain as high-resistance semiconductor films that are almost the same as those obtained when lightly doped in step (3). Thereafter, the resist 601b is removed, and a subsequent process such as cleaning is performed.

  As a result, the TFT according to the third embodiment is manufactured relatively efficiently and easily. In particular, the formation of the peripheral region 412 and the formation of the LDD regions 451 and 452 can be performed using the resist 601bb and the gate electrode 403 which are common masks. That is, as compared with the case of manufacturing a normal LDD type thin film transistor, it is not necessary to increase the manufacturing process, which is very convenient in practice. At this time, the peripheral region 412 including the first portion 412e exhibits an electrical property close to that of the insulating film even in a region doped as lightly as the LDD regions 451 and 452, and the effects of the present invention described above ( 4 and 5) are sufficiently obtained.

(Fourth Embodiment of Thin Film Semiconductor Device)
A fourth embodiment of the thin film semiconductor device of the present invention will be described with reference to FIG. In the present embodiment, as in the case of the first embodiment, the present invention is applied to a top gate type TFT. However, unlike the first embodiment, the second embodiment is constructed as an LDD type and double gate type TFT. FIG. 12 is a plan view of the TFT according to this embodiment. In FIG. 12, the same reference numerals are given to the same components as those in the first embodiment described with reference to FIGS. 1 to 7 or the second embodiment described with reference to FIG. Those descriptions will be omitted as appropriate.

  In FIG. 12, the TFT has two gate electrodes 403a and 403b arranged in parallel as gate electrodes on the element substrate. The inter-gate region 412C occupying the space between the two gate electrodes 403a and 403b in the semiconductor film 401 is configured as an LDD region having a lower impurity concentration than the central region 411. . About another structure, it is the same as that of the case of 1st Embodiment.

  Therefore, according to the fourth embodiment, the withstand voltage can be improved and the off-leak current can be reduced in the LDD type and double gate type TFT.

(Fifth Embodiment of Thin Film Semiconductor Device)
A fifth embodiment of the thin film semiconductor device of the present invention will be described with reference to FIG. In the present embodiment, as in the case of the first embodiment, the present invention is applied to a top gate type TFT. However, unlike the first embodiment, the fifth embodiment is constructed as an LDD type and double gate type TFT. FIG. 13 is a plan view of the TFT according to this embodiment. In FIG. 13, the same components as those in the first embodiment described with reference to FIGS. 1 to 7 or the second embodiment described with reference to FIG. Those descriptions will be omitted as appropriate.

  In FIG. 13, the TFT has two gate electrodes 403 a and 403 b arranged in parallel as gate electrodes on the element substrate 10. The LDD region 412L along the channel region and adjacent to the channel region excluding the central portion 411C of the inter-gate region occupying the space between the two gate electrodes 403a and 403b in the semiconductor film 401 in plan view has an impurity concentration. It is considered as a low resistance region with high resistance. That is, the LDD region 412L in the inter-gate region is configured as an example of the “fourth portion” according to the present invention. On the other hand, the central portion 411C of the inter-gate region is doped with a high concentration to be a low resistance region, like the central region 411. About another structure, it is the same as that of the case of 1st Embodiment.

  Therefore, according to the fourth embodiment, the withstand voltage can be improved and the off-leak current can be reduced in the LDD type and double gate type TFT.

(Embodiment of thin film electronic device)
An embodiment of the thin film electronic device of the present invention will be described with reference to FIGS. In the present embodiment, the present invention is applied to a storage capacitor (capacitor) in which one capacitor electrode is formed from a semiconductor film portion extending from the drain region in the embodiment of the thin film semiconductor device described above. . FIG. 14 is a plan view of the storage capacitor according to the present embodiment, and FIG. 15 is a DD ′ cross-sectional view thereof.

  14 and 15, the storage capacitor 70 is a dielectric made of a first capacitor electrode 701 extending from the drain region 1 e of the TFT 30 on the element substrate 10 and an insulating film 2 that is the same as the gate insulating film of the TFT 30. A film and a second capacitor electrode 3 b that is disposed opposite to the first capacitor electrode 701 and is made of the same film as the gate electrode 3 a of the TFT 30 with the dielectric film interposed therebetween. The second capacitor electrode 3 b is formed integrally with the capacitor line 300 and is electrically connected to a power source having a predetermined potential via the capacitor line 300. The TFT 30 is constructed as a double gate type and top gate type TFT having two gates 3a between the source region 1b and the drain region 1e, and the specific configuration thereof is, for example, the second embodiment described above. (See FIG. 8), the fourth embodiment (see FIG. 12) or the fifth embodiment (see FIG. 13). In the present embodiment, the first capacitor electrode 701 is an example of the “first film” according to the present invention, and the second capacitor electrode 3b is an example of the “second film” according to the present invention.

  Particularly in the present embodiment, the peripheral facing portion 701e of the first capacitor electrode 701 has a lower impurity concentration than the central portion 701C of the first capacitor electrode 701. In the present embodiment, the peripheral facing portion 701c is an example of the “peripheral facing portion” according to the present invention, and is also an example of the “fifth portion” according to the present invention. Therefore, according to the present embodiment, in the vicinity of the peripheral facing portion 701e where coverage is poor, voltage resistance is likely to be hindered, and electric field concentration is likely to occur, as in the case of the peripheral region 412 according to the above-described embodiment. In addition, the insulating film 2 acts to supplement the insulating function.

  As described above, according to the present embodiment, even if the coverage of the insulating film 2 is locally poor in the vicinity of the peripheral facing portion 701e, the withstand voltage here is significantly increased. Alternatively, even if the coverage of the insulating film 2 is good in the vicinity of the peripheral facing region 402, the withstand voltage here increases significantly.

  As a result, according to the present embodiment, the storage capacitor (capacitor) 70 having excellent voltage resistance can be realized.

  In addition, in this embodiment, the central portion 701C of the first capacitor electrode 701 can be formed on the same occasion as the source region 1b and the drain region 1e in the semiconductor film, and the second capacitor electrode 3b is the same as the gate electrode 3a. Since the dielectric film can be formed on the same occasion as the gate insulating film, the TFT 30 and the storage capacitor 70 connected to the drain 1e can be formed on the same element substrate 10. It is very advantageous in terms of manufacturing process. Further, the TFT 30 is an LDD type TFT as in the fourth embodiment (see FIG. 12) or the fifth embodiment (see FIG. 13), and the peripheral facing portion 701e is formed on the same occasion as the formation of the LDD region. This is more advantageous in the manufacturing process.

(Embodiment of electro-optical device)
An electro-optical device according to an embodiment of the invention will be described with reference to FIGS. In the present embodiment, the present invention is applied to an active matrix driving type liquid crystal device that includes the above-described embodiment of the thin film semiconductor device and the above-described embodiment of the storage capacitor in each pixel portion.

  First, an electrical configuration of the pixel portion in this embodiment will be described with reference to FIG. FIG. 16 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixel portions formed in a matrix that forms the image display area of the electro-optical device.

  In FIG. 16, a plurality of pixel portions 100 a are each formed with a pixel electrode 9 a and a TFT 30 for controlling the switching of the pixel electrode 9 a, and a data line 6 a to which an image signal is supplied is a source of the TFT 30. Is electrically connected. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Good.

  Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals S1, S2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9a are held for a certain period with the counter electrode 21 formed on the counter substrate 20. The The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel unit 100a. In the normally black mode, the voltage applied in units of each pixel unit 100a. Accordingly, the transmittance for incident light is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole.

  In order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the source voltage is applied. Thereby, the charge retention characteristic is improved, and an electro-optical device with a high contrast ratio can be realized.

  In the present embodiment, in particular, the TFT 30 has the same configuration as that of the various embodiments of the TFT described above (see FIGS. 1 to 13), and the storage capacitor 70 is the storage capacitor described above (see FIGS. 14 and 15). ), And has a high withstand voltage. In the present embodiment, an example of the “wiring” according to the present invention includes the scanning line 3 a, the data line 6 a, and the capacitor line 300.

  Next, a specific configuration of the pixel unit 100a as described above will be described with reference to FIGS. FIG. 17 is a plan view of the pixel portion 100a, and FIG. 18 is a cross-sectional view taken along the line AA ′ of FIG.

  In FIG. 17, on the element substrate 10, in addition to the above-described TFT 30, scanning line 3a, data line 6a, storage capacitor 70, etc., a transparent electrode 8, a reflective electrode 9, and the like are provided.

  The reflective electrodes 9 are formed in a matrix on the element substrate 10, and pixel switching TFTs 30 are electrically connected to the reflective electrodes 9 via the transparent electrodes 8. The reflective electrode 9 is formed with a transmissive window 14, and a region corresponding to the transmissive window 14 is covered with the transparent electrode 8. The reflective electrode 9 is made of a laminated film of aluminum, silver, or an alloy thereof, or titanium, titanium nitride, molybdenum, tantalum, or the like, and the transparent electrode 8 is made of ITO (indium tin oxide). ) Etc.

  On the other hand, as shown in FIG. 18, a concavo-convex forming layer 13 and an concavo-convex layer 7 (both not shown in FIG. 17) are formed under the reflective electrode 9 and the transparent electrode 8. Here, the concavo-convex forming layer 13 and the concavo-convex layer 7 are made of, for example, a photosensitive resin such as an organic resin, and in particular, the former is a layer formed in a form including block blocks scattered on the substrate surface. The latter is a layer formed so as to cover the entire surface of the substrate including such an unevenness forming layer 13. Therefore, the surface of the concavo-convex layer 7 is “swelled” in accordance with the scattered state of the block blocks constituting the concavo-convex formation layer 13, and as a result, the concavo-convex pattern 9 g is formed. In FIG. 17, the uneven pattern 9g is shown in a circular shape, and the circular portion has a shape protruding toward this side toward the paper surface of FIG. 17 as compared with the other portions. Is shown. That is, the uneven layer 7 and the block block are formed on the opposite side of the circular portion toward the paper surface of FIG. 17 (see FIG. 18).

  In the electro-optical device of the present embodiment having such a configuration, it is possible to perform image display in the transmission mode by using the transparent electrode 8 and the transmission window 14, and the reflective electrode 9, the unevenness forming layer 13, the unevenness By using the layer 7 and the uneven pattern 9g, it is possible to perform image display in the reflection mode. That is, the area defined by the former configuration is a transmission area that transmits light emitted from an internal light source (not shown) from the other side of the drawing to the near side in FIG. 17, and is defined by the latter configuration. Is a reflective region that reflects from the near side of the paper to the reflective electrode 9 and then reaches the reflective side of the paper again. In the latter case, in particular, since the light is scattered and reflected by the uneven pattern 9g, the viewing angle dependency of the image can be reduced.

  Now, returning to FIG. 17, the data lines 6 a, the scanning lines 3 a, and the capacitor lines 300 are formed along the vertical and horizontal boundaries of the region where the reflective electrode 9 is formed. The TFT 30 is connected to the data lines 6 a and the capacitor lines 300. Connected. That is, the data line 6a is electrically connected to the high concentration source region 1d of the TFT 30 through the contact hole, and the transparent electrode 8 is electrically connected to the high concentration drain region 1e of the TFT 30 through the contact hole 15 and the relay layer 6b. Connected. Further, the scanning line 3 a extends so as to face the channel region 1 a ′ of the TFT 30. The TFT 30 is of an LDD type and a double gate type as in the fifth embodiment (see FIG. 13) described above, and includes a low concentration LDD region 1b on both sides of the channel region 1a ′ in the semiconductor film 1, respectively. A high-concentration central portion 1c is provided between the two gates 3a.

  The storage capacitor 70 is a first capacitor electrode 701 formed by conducting the extended portion 1f of the semiconductor film 1 for forming the pixel switching TFT 30. The first capacitor electrode 701 includes the scanning line 3a and the storage capacitor 70. The second capacitor electrode 3b, which is the same layer and is formed integrally with the capacitor line 300, has a structure in which the second capacitor electrode 3b is disposed to face each other.

  In FIG. 18, in addition to the above, a base protective film 111 made of a silicon oxide film (insulating film) having a thickness of 100 to 500 nm is formed on the element substrate 10, and the thickness is formed on the base protective film 111 and the TFT 30. The first interlayer insulating film 4 made of a silicon oxide film having a thickness of 300 to 800 nm, and the second interlayer insulating film 5 made of a silicon nitride film having a thickness of 100 to 800 nm on the first interlayer insulating film 4 (surface protection) Film), the third interlayer insulating film 7 and the like are formed. However, in some cases, the second interlayer insulating film 5 may not be formed. An alignment film 16 is formed on the element substrate 10 side as the uppermost layer. In addition, in FIG. 18, a contact hole or the like for electrically connecting various components is provided. On the other hand, on the counter substrate 20 side, a light shielding film 23 extending so as to sew a so-called gap between the pixel portions 100a, a counter electrode 21 and an alignment film 22 formed on the entire surface of the substrate are formed to be laminated in this order. ing. A liquid crystal layer 50, which is an example of an electro-optical material, is sandwiched between the element substrate 10 and the counter substrate 20.

  According to the electro-optical device of the present invention configured as described above, the active matrix is provided in each pixel unit 100a by the TFT 30 having excellent voltage resistance and excellent off-leakage current characteristics and the storage capacitor 70 having excellent voltage resistance. Since it can be driven, high-quality image display can be realized.

(Electronics)
Next, a case where the above-described electro-optical device is applied to various electronic devices will be described with reference to FIGS.

  First, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 19 is a perspective view showing the configuration of this personal computer. In FIG. 19, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a display unit 1206 configured using an electro-optical device.

  Further, an example in which this electro-optical device is applied to a mobile phone will be described. FIG. 20 is a perspective view showing the configuration of this mobile phone. In FIG. 20, a mobile phone 1300 includes an electro-optical device together with a plurality of operation buttons 1302. In FIG. 20, the electro-optical device is indicated by reference numeral 1005.

  In addition, electro-optical devices include notebook personal computers, PDAs, televisions, viewfinders, monitor direct-view video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, POS terminals, The present invention can be applied to an apparatus provided with a touch panel, and further to an exposure head in an image forming apparatus such as a printer, a copy, and a facsimile.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and a thin film semiconductor device with such a change In addition, an electro-optical device, an electronic apparatus, a method for manufacturing a thin film semiconductor device, and a thin film electronic device are also included in the technical scope of the present invention.

It is a top view of TFT concerning a 1st embodiment of a thin film semiconductor device of the present invention. It is B-B 'sectional drawing of FIG. It is C-C 'sectional drawing of FIG. FIG. 4A is a partially enlarged cross-sectional view of the vicinity of the portion corresponding to the peripheral region of the semiconductor film of FIG. 3 in one comparative example and the vicinity of the peripheral region of the semiconductor film of FIG. 3 in one specific example of the first embodiment. It is a partial expanded sectional view (Drawing 4 (b)). FIG. 5A is a partially enlarged sectional view of the vicinity of a portion corresponding to the peripheral region of the semiconductor film of FIG. 3 in another comparative example and the vicinity of the peripheral region of the semiconductor film of FIG. 3 in another specific example of the first embodiment. FIG. 6 is a partially enlarged sectional view (FIG. 5B). FIG. 3 is a process chart sequentially illustrating a manufacturing method of the TFT according to the first embodiment as a cross-sectional view at a location corresponding to FIG. 2. 6 is a perspective view (FIG. 7A) showing the laminated structure on the substrate in the state of step (3) in FIG. 6 and a perspective view showing the laminated structure on the substrate in the state of step (6) in FIG. b)). It is a top view of TFT concerning a 2nd embodiment of a thin film semiconductor device of the present invention. It is a top view of TFT concerning a 3rd embodiment of a thin film semiconductor device of the present invention. FIG. 10 is a process chart sequentially illustrating a manufacturing method of a TFT according to a third embodiment as a cross-sectional view at a location corresponding to FIG. 2. It is a perspective view which shows the laminated structure on a board | substrate in the state of the process (6) of FIG. It is a top view of TFT concerning a 4th embodiment of a thin film semiconductor device of the present invention. It is a top view of TFT concerning a 5th embodiment of a thin film semiconductor device of the present invention. It is a top view of the storage capacity concerning the embodiment of the thin film electronic device of the present invention. It is D-D 'sectional drawing of FIG. FIG. 3 is a circuit diagram illustrating an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix-like pixels constituting an image display region in an electro-optical device according to an embodiment of the invention. It is a top view of the pixel part which mutually adjoins an element substrate. It is the sectional view on the AA 'line of FIG. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Element substrate, 30 ... TFT, 70 ... Storage capacitor, 100a ... Pixel part, 401 ... Semiconductor film, 401S ... Source region, 401D ... Drain region, 402 ... Gate insulating film, 403, 403a, 403b ... Gate electrode, 411 ... Central region, 412 ... Peripheral region, 412e ... First part, 601a, 601b, 601bb ... Resist, 412L, 451, 452 ... LDD region

Claims (13)

A semiconductor film having an island-like planar pattern including a channel region and an impurity-doped source region and drain region;
A gate electrode disposed opposite to the channel region via a gate insulating film,
The source region and the drain region are surrounded by a peripheral region along the outer periphery of the semiconductor film, a second portion adjacent to the channel region along the channel region, and the peripheral region and the second portion. Central area and
A thin film characterized in that at least one of the peripheral regions adjacent to the channel region in at least one of the source region and the drain region has a lower impurity concentration than the central region. Semiconductor device.   The thin film semiconductor device according to claim 1, wherein the peripheral region has a lower concentration of the impurity than the central region. The thin film semiconductor device is configured as an LDD (Lightly Doped Drain) type thin film transistor,
3. The thin film semiconductor device according to claim 1, wherein the second portion is an LDD region, and the concentration of the impurity is lower than that of the central region. The thin film semiconductor device is configured as a double gate type thin film transistor having two gate electrodes arranged in parallel as the gate electrode,
In the inter-gate region occupying between the two gate electrodes when viewed in plan in the semiconductor film, at least a third portion of the peripheral region adjacent to the channel region has a concentration of the impurity as compared with the central region. The thin film semiconductor device according to claim 1, wherein the thin film semiconductor device is low. The thin film semiconductor device is configured as a double gate type and LDD (Lightly Doped Drain) type thin film transistor,
5. The thin film semiconductor device according to claim 4, wherein a fourth portion adjacent to the channel region in the inter-gate region is the LDD region, and the impurity concentration is lower than that in the central region. The thin film semiconductor device is configured as a double gate type and LDD (Lightly Doped Drain) type thin film transistor,
5. The thin film semiconductor device according to claim 4, wherein the inter-gate region has a lower concentration of the impurity than the central region over the entire region. The thin film semiconductor device includes one capacitor electrode in which at least one of the source region and the drain region is extended, and the other capacitor electrode disposed to face the one capacitor electrode through a dielectric film. And a storage capacity having
Of the peripheral region, a fifth portion located on the outer periphery of the one capacitor electrode has a lower concentration of the impurity than a portion of the one capacitor electrode excluding the fifth portion. The thin film semiconductor device according to any one of claims 1 to 6. The other capacitor electrode is formed from the same layer as the gate electrode,
The thin film semiconductor device according to claim 7, wherein the dielectric film is formed of the same layer as the gate insulating film. A plurality of pixel units each including the thin film semiconductor device according to any one of claims 1 to 8 and a display element controlled by the thin film semiconductor device;
An electro-optical device comprising: a wiring electrically connected to the thin film semiconductor device for driving the plurality of pixel portions.   An electronic apparatus comprising the electro-optical device according to claim 9. Forming a semiconductor film having an island-like planar pattern on a substrate;
Forming a gate insulating film on the semiconductor film;
Forming a gate electrode on the gate insulating film;
Performing impurity doping at a low concentration via the gate electrode;
Concurrently with the step of doping with impurities, both a region to be an LDD (Lightly Doped Drain) region and at least a first portion adjacent to the channel region in the peripheral region of the island-like planar pattern are simultaneously masked. And a step of doping impurities at a high concentration. A method of manufacturing a thin film semiconductor device, comprising: A first film formed of a semiconductor film including an impurity region doped with impurities and having an island-like planar pattern;
A conductive second film having a predetermined plane pattern disposed oppositely via an insulating film above or below the impurity region, and
Of the peripheral region of the island-shaped planar pattern in the first film, at least a peripherally facing portion disposed to face the second film is more resistant to the impurities than portions other than the peripherally facing portion in the first film. A thin film electronic device characterized by a low concentration. The first film has one capacitance electrode in the impurity region,
13. The thin film electronic device according to claim 12, wherein the second film has the other capacitor electrode disposed opposite to the one capacitor electrode with the insulating film as a dielectric film.

Images