JP2006100352A - Method of analyzing fault of semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of analyzing the fault of semiconductor chip by which the fault distributing state of a plurality of semiconductor chips on a wafer can be analyzed without wasting nondefective chips. <P>SOLUTION: The method of analyzing fault of semiconductor chip includes a first step of dicing the wafer 1 on which nondefective chips 2 and defective chips 3 are identified, and removing the nondefective chips 2 from the diced wafer 1; a second step of discriminating the positions of the left defective chips 3 on the wafer 1, storing first positional information (a and b) indicating the positions of the defective chips 3 on the wafer 1, and, at the same time, transferring the defective chips 3 to an analyzing stage 10 by picking up the chips 3. The method also includes a third step of preparing second positional information indicating the position of the fault in each defective chip 3, by analyzing the fault of each defective chip 3 on the analyzing stage 10, and identifying and displaying the defective chips 3 and the positions of the faults in the chips 3 on a wafer map 4 based on the prepared second positional information and stored first positional information (a and b). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a failure analysis method for a semiconductor chip such as an LSI, and in particular, to analyze the distribution of failure locations on a wafer.

  According to a conventional failure analysis method for a semiconductor device, a step of generating a light emitting wafer map that collectively displays the light emission statuses of a plurality of semiconductor memory devices formed on a predetermined wafer on the predetermined wafer using an emission microscope. And a step of generating a plurality of defect wafer maps that collectively display defects for each manufacturing process on the wafer, and a fail bit map that collectively displays defective bits of the plurality of semiconductor memory devices on the predetermined wafer And a network to perform data management of the light emitting wafer map, the plurality of defective wafer maps and the fail bit map, and a matching process between two types of maps among the three types of maps, And a step of performing a failure analysis of the semiconductor memory device (for example, Patent Document 1). Irradiation).

Japanese Patent No. 3436456 (Claims, FIGS. 1-8)

  However, in the above-described conventional failure analysis method, a wafer on which a plurality of semiconductor memory devices including non-defective products are formed is used as a failure analysis sample as it is, and a location specified by failure analysis after failure analysis is determined by SEM (Scanning Electron Microscope) or TEM. Observations were made in detail with a (transmission electron microscope) or physical analysis for elemental analysis was performed. This physical analysis is an analysis to observe and analyze the specified failure location while performing various processing on the wafer, and to clarify the physical cause that caused the failure. Destructive analysis is performed by removing. Therefore, the conventional technology has a problem that a non-defective semiconductor memory device existing on the wafer is destroyed, and a non-defective semiconductor memory device (non-defective chip) is wasted.

  The present invention has been made in view of the above, and provides a failure analysis method for a semiconductor chip that can analyze a failure distribution situation on a wafer of a plurality of semiconductor chips without wasting non-defective chips. With the goal.

  In order to solve the above-described problems and achieve the object, the failure analysis method for a semiconductor chip according to the present invention performs dicing cutting on a wafer in which good chips and defective chips are identified, and converts the non-defective chips from the dicing cut wafer. A first step of extracting and determining a position of the remaining defective chip on the wafer; storing first position information indicating a position of the defective chip on the wafer; and picking up the defective chip A second step of transferring to the analysis stage, and a second position information indicating a failure position in each defective product chip by creating a failure analysis of each defective product chip on the analysis stage and creating the second And a third step for identifying and displaying the defective chip and the failure position in the defective chip on the wafer map on the basis of the position information and the stored first position information. It is characterized in that comprises a flop, a.

  The wafer is diced and the non-defective chips are extracted and returned to the product manufacturing line. Only the remaining defective chips are analyzed for failure, and the defective chip and the failure position in the defective chip are identified and displayed on the wafer map.

  A semiconductor chip failure analysis method that can analyze the failure distribution status of a plurality of semiconductor chips on a wafer without wasting non-defective chips is obtained.

  Embodiments of a semiconductor chip failure analysis method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing an outline of a semiconductor chip failure analysis method according to the present invention, FIG. 2 is a diagram showing a management method for defective chips that have been diced and separated from a wafer, and FIG. FIG. 4 is a diagram illustrating a schematic configuration of a failure analysis apparatus for a semiconductor chip, FIG. 4 is a flowchart illustrating a failure analysis method for a semiconductor chip, and FIG. 5A is a plan view of the alignment apparatus according to the first embodiment of the failure analysis apparatus. FIG. 5B is a longitudinal sectional view of the same.

  In the semiconductor chip failure analysis method of the first embodiment, as shown in the upper left diagram of FIG. 1, first, the electrical characteristics of a plurality of semiconductor chips formed on the wafer 1 are evaluated using an LSI tester or the like. The good chip 2 and the defective chip 3 are identified. Next, the wafer 1 is diced and cut in a matrix with the expanded sheet pasted on the back surface, each semiconductor chip is cut out, and the non-defective chip 2 is extracted from the wafer 1 and returned to the product manufacturing line. The upper left figure in FIG. 1 shows a state after the non-defective chip 2 (the white part in the figure) is extracted after the wafer 1 is diced.

  Thereafter, as shown in the lower diagram in FIG. 1, each remaining defective chip 3 (hereinafter simply referred to as “chip 3”) is placed on the analysis stage 10 and brought into contact with the probe 13, and the back surface of the chip. The failure analysis is performed by irradiating the near-infrared laser beam 31 to the failure position information in each chip 3 and the position information of each chip 3 on the wafer 1 is input and stored in a computer as a workstation. As shown in the upper right diagram of FIG. 1, after the failure location information obtained by analyzing the failure locations 3 a of all the chips 3 is input to the computer, the failure location information in each chip 3 is synthesized based on the location information on the wafer 1. Then, an identification display is made on the wafer map 4 of the monitor.

  Next, referring to FIG. 2 to FIG. 4, the pick-up of the chip 3 from the wafer 1 and the transfer to the chip tray 5, and the work station for the position information of the chip 3 on the wafer as the first position information An input method to the computer 20 will be described. First, as a first step, the dicing cutter 80 is controlled by the computer 20 of the failure analysis apparatus 100, and the wafer 1 with the non-defective chip 2 and the defective chip 3 identified and the expanded sheet pasted on the back surface is diced and cut. Each semiconductor chip is separated by pulling the expand sheet. Next, the non-defective chip 2 is extracted from the wafer 1 and returned to the product production line.

  Subsequently, as a step 2-1, the computer 20 controls the chip picking device 90 to determine the location of the defective chip 3 remaining on the wafer 1, picks up the chip 3 and picks up a predetermined chip tray 5 (#N) is transferred to a predetermined pocket (n, m). The chip picking device 90 includes an optical sensor 92 capable of recognizing the presence of a chip in the vicinity of a vacuum suction nozzle 91 that vacuum-sucks the chip 3, and sequentially identifies the chips 3 on the wafer 1. Is picked up, the empty pockets of the plurality of chip trays 5 are identified, and the chips 3 are arranged in order. Further, the chip picking device 90 inputs and stores the XY coordinate position information (a, b) on the wafer 1 as the first position information of the chip into the computer 20 when the chip 3 is picked up.

  Further, as a step 2-2, the chip picking device 90 determines the empty pocket of the chip tray 5, and when placing the chip 3 in the pocket, chip tray number information (# indicating the number of the chip tray 5) N) and pocket coordinate position information (n, m) indicating the position of the pocket are input to the computer 20 and stored in correspondence with the XY coordinate position information (a, b) on the wafer 1 as the first position information. Let In this way, all defective chips 3 on the wafer 1 are transferred to the chip trays 5 (# 1) to (#N) in which one wafer is one cassette, and XY coordinate position information on the wafer 1 ( a, b) and tray position information (#N (n, m)) are input to the computer 20 and stored.

  Next, as a 2-3 step, the chip 3 is picked up from the chip tray 5 by the chip picking device 90 and placed on the analysis stage 10. Next, as step 2-4, the alignment control unit 11 is controlled by the computer 20 to align the probe 13 held by the probe card 12 with the chip 3 and align the probe 13 with the chip 3. Contact the electrode. Details of the step 2-4 will be described later.

  Next, the emission analysis, OBIC analysis, and OBIRCH analysis method of the chip 3 by the well-known failure analysis apparatus 100 will be described with reference to FIG.

  Near-infrared laser light 31 is emitted from the light emitting source 30, reflected by the mirror 32, and irradiated to the back surface of the chip 3 through the half mirror 33. The computer 20 controls the scanning control unit 34 to scan and drive the scanning unit 36, and scans the back surface of the chip 3 with the near infrared laser beam 31.

  The reflected light 35 from the chip 3 is reflected by the half mirror 33, received by the photodiode 40, photoelectrically converted, amplified by the amplifier 41, and input to the image processor 50. On the other hand, the probe 13 is brought into contact with the electrode on the surface of the chip 3 and a bias voltage is applied to detect OBIC (light beam excitation current) and OBIRCH (light heating resistance change) generated by the irradiation of the laser beam 31, and an amplifier. Amplified at 60 and input to the image processor 50.

  The light emission source 30, the mirror 32, the half mirror 33, the scanning control unit 34, the scanning unit 36, the photodiode 40, the amplifier 41, the image processor 50, the amplifier 60, and the like constitute the back surface failure analysis apparatus 110.

  The reflected light detection signal, the OBIC detection signal and the OBIRCH detection signal input to the image processor 50 and the scanning signal output from the scanning control unit 34 are arithmetically processed by the arithmetic processing unit 51. Fault position information in the defective chip 3 as second position information obtained by processing the scanning signal and the reflected light detection signal, OBIC detection signal, and OBIRCH detection signal obtained in synchronization therewith. A certain optical image formation signal, OBIC image formation signal, and OBIRCH image formation signal are input to the computer 20 and stored therein. At this time, these image forming signals correspond to the XY coordinate position information (a, b) on the wafer 1 and the tray position information (#N (n, m)) as the first position information. Is input and stored.

  After the failure analysis, the chip 3 is returned to the original pocket of the chip tray 5 by the chip picking device 90. The chip 3 performs detailed analysis by acquiring an enlarged analysis image of a specific failure location after the failure analysis, and details the location specified by the failure analysis using a SEM (scanning electron microscope) or TEM (transmission electron microscope). It is stored and managed by the chip tray 5 in preparation for physical analysis for observation or elemental analysis. The above is the 3-1 step.

  As a step 3-2, in the computer 20 that performs failure analysis, a stored optical image that is failure position information in the defective chip 3 as second position information is operated by operating the keyboard 21 or the like. The OBIC image, the OBIRCH image, and the optical image corresponding to the OBIC image, the OBIRCH image, and the corresponding optical image are displayed on the wafer map of the monitor 22 based on the signal, the OBIC image formation signal, the OBIRCH image formation signal, and the XY coordinate position information (a, b) on the wafer 1. To display.

  Next, with reference to FIGS. 5A and 5B, a method for aligning the defective chip 3 and the probe card 12 (probe 13) according to the first embodiment as the step 2-4 will be described. To do. Although not shown, the analysis stage 10 shown in FIGS. 5A and 5B includes the failure analysis apparatus 100 shown in FIG. When the wafer 1 is fixed to the analysis stage 10, it can be fixed by vacuum suction. However, when the chip 3 is fixed, the fixing method to the analysis stage 10 becomes a problem.

  A circular quartz glass 14 as a transparent portion is attached to the center of the circular analysis stage 10, and a hook-shaped fixed guide 15 for positioning one corner of the chip 3 is provided on the quartz glass 14. Opposite to the fixed guide 15, a Y-shaped movable guide 16 that presses the other corner of the chip 3 toward the fixed guide 15 is provided. The chip 3 is positioned and fixed on the quartz glass 14 by positioning one corner of the chip 3 with the fixed guide 15 and pressing the other corner toward the fixed guide 15 with the movable guide 16. Thereafter, the probe card 12 is lowered onto the chip 3, and the rough positioning is performed with the tip of the probe 13 slightly separated from the upper surface of the chip 3.

  Next, the back surface failure analysis apparatus 110 is operated, the near infrared laser beam 31 is emitted from the light emission source 30 to irradiate the back surface of the chip 3, and the scanning control unit 34 is controlled by the computer 20 to scan the scanning unit 36. Driven, the back surface of the chip 3 is scanned with the near-infrared laser beam 31. The reflected light 35 from the chip 3 and the probe 13 is received and these optical images are acquired. While observing the optical image on the monitor 22, the alignment control unit 11 is controlled so that the alignment of the chip 3 and the probe 13 is matched, and the analysis stage 10 is moved and rotated with respect to the probe 13 to perform alignment.

  After alignment, the probe card 12 is lowered and the probe 13 is brought into contact with the electrode of the chip 3. Finally, the movable guide 16 is separated from the chip 3. The above is the alignment method of the chip 3 and the probe card 12 (probe 13) according to the first embodiment as the 2-4 step. In this way, alignment can be performed using the back surface failure analysis apparatus 110.

  According to the semiconductor chip failure analysis method of the first embodiment described above, the failure of the semiconductor chip that can analyze the failure distribution status of the plurality of semiconductor chips on the wafer 1 without wasting non-defective chips 2. An analysis method is obtained.

Embodiment 2. FIG.
Next, with reference to FIG. 6, a method of aligning the chip 3 and the probe card 12 (probe 13) according to the second embodiment as the step 2-4 will be described. FIG. 6 is a longitudinal sectional view of the analysis stage 10 showing the alignment method of the second embodiment. Although not shown, the analysis stage 10 in FIG. 6 includes the failure analysis apparatus 100 shown in FIG.

  A circular quartz glass 14 as a transparent portion is attached to the center of the circular analysis stage 10. The chip 3 is positioned on the quartz glass 14 while being sucked by the vacuum suction nozzle 91 of the chip picking device 90. Thereafter, the probe card 12 is lowered onto the chip 3, and the rough positioning is performed with the tip of the probe 13 slightly separated from the upper surface of the chip 3.

  Next, the back surface failure analysis apparatus 110 is operated, the near infrared laser beam 31 is emitted from the light emission source 30 to irradiate the back surface of the chip 3, and the scanning control unit 34 is controlled by the computer 20 to scan the scanning unit 36. Driven, the back surface of the chip 3 is scanned with the near-infrared laser beam 31. The reflected light 35 from the chip 3 and the probe 13 is received and these optical images are acquired.

  The chip picking device 90 is controlled to move and rotate the vacuum suction nozzle 91 so that the alignment of the chip 3 and the probe 13 is matched while viewing the optical image on the monitor 22. After alignment, the probe card 12 is lowered and the probe 13 is brought into contact with the electrode of the chip 3. Thus, alignment can be performed using the chip picking device 90 and the back surface failure analysis device 110.

Embodiment 3 FIG.
Next, with reference to FIGS. 7-1 and 7-2, a method for aligning the chip 3 and the probe card 12 (probe 13) according to the third embodiment as the step 2-4 will be described. 7A and 7B are longitudinal sectional views of the analysis stage 10a showing the alignment method of the third embodiment. Although not shown, the analysis stage 10a of FIGS. 7-1 and 7-2 includes the failure analysis apparatus 100 shown in FIG.

  A suction port 10b is provided at the center of the analysis stage 10a for wafer failure analysis, and a quartz glass 14 as a transparent part is attached to the outer periphery. The chip 3 is placed on the suction port 10b of the analysis stage 10a by the chip picking device 90, and is sucked and fixed.

  A CCD camera 17 as an imaging device connected to the computer 20 and capable of imaging the upper and lower surfaces is inserted between the probe card 12 and the chip 3 to acquire optical images of the probe 13 and the chip 3. Two optical images are superimposed on the monitor 22, and the alignment control unit 11 is controlled so that the alignment of the probe 13 and the chip 3 is aligned, and the analysis stage 10 a is moved and rotated with respect to the probe 13.

  After the alignment, the CCD camera 17 is moved, the chip 3 is sucked and fixed by the vacuum suction nozzle 91 of the chip picking device 90, and the suction of the suction port 10b of the analysis stage 10a is stopped. Next, as shown in FIG. 7B, the analysis stage 10 a is slid to move the chip 3 and the probe card 12 onto the quartz glass 14. Thereafter, the chip 3 is lowered onto the quartz glass 14, the probe card 12 is subsequently lowered onto the chip 3, and the probe 13 is brought into contact with the electrode of the chip 3. As described above, the alignment may be performed by using the analysis stage 10a for wafer failure analysis and the CCD camera 17.

  In the above embodiment, the defective chip 3 is once transferred to the chip tray 5 and then transferred to the analysis stage 10 in the second step. However, the defective chip 3 is directly transferred from the wafer 1 to the analysis stage 10. When the rear surface failure analysis is completed, the wafer 1 is returned to the original position, and the defective chip 3 may be held and stored by the adhesive force of the expanded sheet.

  As described above, the semiconductor chip failure analysis method according to the present invention is useful as a failure analysis method that does not waste non-defective chips.

It is a figure which shows the outline of the failure analysis method of the semiconductor chip concerning this invention. It is a figure which shows the management method of the defective chip isolate | separated from the wafer. It is a figure which shows schematic structure of the failure analysis apparatus of a semiconductor chip. It is a flowchart which shows the failure analysis method of a semiconductor chip. It is a top view of the alignment apparatus of Embodiment 1 of a failure analysis apparatus. It is the longitudinal cross-sectional view. FIG. 10 is a longitudinal sectional view of an analysis stage showing the alignment method of the second embodiment. FIG. 10 is a longitudinal sectional view of an analysis stage showing the alignment method of Embodiment 3. FIG. 10 is a longitudinal sectional view of an analysis stage showing the alignment method of Embodiment 3.

Explanation of symbols

1 Wafer 2 Good chip 3 Defective chip (chip)
4 Wafer map 10, 10a Analysis stage 13 Probe 20 Workstation 100 Failure analysis device 110 Back surface failure analysis device

Claims (5)

A first step of dicing cutting a wafer in which good chips and defective chips are identified, and extracting the non-defective chips from the diced wafer;
The position of the remaining defective chip on the wafer is determined, first position information indicating the position of the defective chip on the wafer is stored, and the defective chip is picked up and transferred to the analysis stage. Two steps,
By analyzing failure of each defective product chip on the analysis stage, second position information indicating a failure position in each defective product chip is generated, and the generated second position information and the stored first position A third step of identifying and displaying the defective chip and the failure position in the defective chip on the wafer map based on the information;
A failure analysis method for a semiconductor chip, comprising:   In the second step, the defective chip is picked up from the wafer and transferred to a predetermined pocket of the chip tray, the first position information, chip tray number information indicating the number of the chip tray, and the pocket 2. The failure analysis method for a semiconductor chip according to claim 1, further comprising a step of storing in correspondence with pocket position information indicating the position of the semiconductor chip.   Between the second step and the third step, one corner of the defective chip is positioned by a fixed guide provided on the analysis stage, and the other corner is pressed by the movable guide toward the fixed guide. A step of fixing the defective chip on the analysis stage, a step of roughly positioning the probe on the defective chip, and an optical image of the defective chip and the probe obtained by a back surface failure analysis device. The failure analysis method for a semiconductor chip according to claim 1, further comprising a step of aligning the defective chip and the probe by moving the analysis stage while viewing an image.   Between the second step and the third step, a step of positioning the defective chip on the analysis stage by a chip picking device, a step of roughly positioning the probe on the defective chip, and the back surface Obtaining an optical image of the defective chip and the probe by a failure analysis device, moving the defective chip by the chip picking device while viewing the optical image, and aligning the defective chip and the probe; The failure analysis method for a semiconductor chip according to claim 1, wherein:   Between the second step and the third step, a step of placing the defective chip on the suction port of the analysis stage by a chip picking device, and a step of roughly positioning the probe above the defective chip Then, an imaging device capable of imaging both the upper and lower surfaces is inserted between the defective chip and the probe, an optical image of the defective chip and the probe is acquired, and the analysis stage is moved while viewing the optical image to A step of aligning the non-defective chip and the probe; and the chip picking device causes the defective chip to float from the analysis stage, and the analysis stage is slid to position the defective chip and the probe in the transparent portion of the analysis stage. And a step of bringing the defective chip and the probe into contact with each other. The semiconductor chip failure analysis method of according to claim 1 or 2 that.

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