JP2006099598A - Interface extension circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface extension circuit that can control a plurality of cards or modules compliant with PCMCIA standards or CFA standards with minimum CPU resources. <P>SOLUTION: The interface extension circuit has a data latch circuit 101 for holding an address signal from a CPU 200, an access determination circuit 102 for determining an accessed slot from the data latch circuit 101, an address conversion circuit 103 for generating an effective address of register access compliant with PCMCIA standards or CFA standards from the data latch circuit 101, means for outputting the effective address generated by the address conversion circuit 103 to each slot as an address, a control signal output circuit 106 for outputting a control signal from the CPU 200 to the slot determined by the access determination circuit 102, and a status signal output circuit 107 for outputting a status signal from the slot determined by the access determination circuit 102 to the CPU 200. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PC card that is detachably attached to an information processing terminal such as a personal computer or a portable information terminal or is used by being embedded in an information processing terminal, a module having a PC card interface, and the like. The present invention relates to an interface expansion circuit that can be used when a plurality of terminals are used.

  An auxiliary storage device provided with a hard disk device such as a memory card or magnetic disk used as a storage medium, for example, as a PC card that is detachably mounted on an information processing terminal such as a personal computer or a portable information terminal There are a modem card and a LAN card used for wired communication, a wireless LAN card used for wireless communication, and the like. By using these PC cards, personal computers and portable information terminals can flexibly cope with the situation and environment in which they are used. For example, a LAN card can be used in an environment where a wired LAN can be used, and communication using a wireless LAN card can be performed in a wireless LAN environment.

  The PC card is used by inserting a connector into the PC card slot of the PC card interface provided in the information processing terminal based on the PCMCIA (Personal Computer Memory Card International Association) standard (PC Card Standard), which is a US standardization organization. When not in use, it can be pulled out from the PC card slot. Hereinafter, the above unified standard is referred to as a PCMCIA standard.

  A compact flash (registered trademark) (hereinafter abbreviated as a CF card) proposed by CFA (Compact Flash Association) is small and excellent in portability, so that it can be used for small information processing such as digital cameras and portable information terminals. Used on the terminal. Hereinafter, a standard relating to a CF card defined by the CFA is referred to as a CFA standard.

  The PC card employs a two-piece connector having 68 pins, and the CF card employs a 50-pin two-piece connector.

  However, with the recent miniaturization of portable information terminals, the size of the card connector mounting area has become a problem. Therefore, in recent years, module parts conforming to PC card or CF card standards have become widespread, and it has become possible to provide a smaller information processing terminal by incorporating this module part into the information processing terminal.

  With the spread of PC cards, CF cards, and module parts as described above, central processing units (hereinafter abbreviated as CPU) mounted on information processing terminals also conform to the PCMCIA standard or CFA standard. The ones with the interface controllers that have been developed have appeared. As a result, the CPU can control the card directly inserted into the PC card slot or the CF card slot or the built-in module component without using the PC card or CF card interface controller.

  However, in recent years, information processing terminals have become multimedia with functions such as communication and AV, and there is a demand for smaller and more functions. For example, there is a demand for an information processing terminal that has a wireless LAN communication function and a storage function capable of storing a larger amount of information. This can be achieved by combining a wireless LAN card or module with a memory card or hard disk device.

  In order to satisfy the above-described configuration, conventionally, an interface control LSI between the CPU and each card or module, that is, a controller that can control a plurality of PC cards, CF cards, or modules is required.

Further, as a technique for connecting a plurality of cards to one slot, a technique has been devised in which a plurality of PC cards are connected, a desired function is selected and switched by a switch so that it can be executed ( Patent Document 1).
JP-A-8-180148 "Thorough research on PC / memory cards", CQ Publishing, 2002

  However, when a control LSI that can control a plurality of PC cards or CF cards or modules is used, the problem is the allocation of the address space of the CPU that controls the control LSI. When controlling a plurality of cards and modules, the CPU needs to allocate an address space to each card or module. In some cases, a switching signal for controlling each card or module from the CPU may be required. For example, in the case of a CF card, the address signal is 10 bits. However, since these 10 bits use a register for accessing the CF card for addressing, an address space is allocated for the 10-bit address signal (address is assigned). Cannot be decoded). Therefore, the control LSI can only receive an address signal of 10 bits or more, or can input a switching signal from the CPU. When the address signal of 10 bits or more is input, the number of bits of the address signal of each CPU differs depending on the CPU, and the allocation of the address space is also different, so the versatility of the control LSI is lost. Therefore, control can be performed by using a switching signal for controlling each card or module from the CPU described later. By outputting a switching signal corresponding to an address space allocated in advance from the CPU to the control LSI, the control LSI can control each card or module using the switching signal regardless of the connected CPU. It becomes. However, with today's portable information processing terminals becoming multimedia and downsizing, it may be difficult to secure this switching signal. Even if the CPU has a PC card or CF card controller built-in, the number of PC cards or CF cards that can be controlled by the controller built in the CPU is determined, most of which are 1 or 2 slots. . In order to control a larger number of cards or modules, the above controller LSI is required. Even in this case, it is necessary to assign an address space.

  At this time, there is no room for allocating an address space for controlling a plurality of PC cards or CF cards or modules to the CPU. For example, if an address space is used for other functions of the CPU and there is no newly allocated address space, only the number of slots that can be controlled by the controller built in the CPU can be used, and a control LSI for expanding the slots can be used. There is a problem that it cannot be used.

  In addition, in a PC card (see Patent Document 1) in which a plurality of PC cards are connected, and a desired function is selected and switched by a switch so that it can be executed, only one of the functions connected to the plurality of PC cards is used. Is selected and executed, there is a problem that it is not possible to perform real-time processing for continuously processing functions across a plurality of PC cards. In addition, in the configuration in which a plurality of PC cards are connected, the mounting area is large. There was a problem of getting bigger.

  The present invention solves the above-described problems of the prior art, and efficiently processes a plurality of PC cards or CF cards or modules with minimum CPU resources in an information processing terminal such as a personal computer or a portable information device. An object of the present invention is to provide an interface expansion circuit capable of performing the above.

  In order to achieve the above object, the present invention basically employs the technical configuration described below.

  A first invention according to the present invention is an interface expansion circuit that is connected to a CPU including a controller that controls a card or module conforming to the PCMCIA standard or CFA standard, and controls a plurality of slots with a control signal for one slot. Holding means for holding an address signal from the CPU, determination means for determining a slot to be accessed based on the state of the holding means, and address generation means for generating an effective address of a register address conforming to a predetermined standard from the holding means Address output means for outputting the effective address as the address of each slot, control signal output means for outputting a control signal from the CPU to the slot determined by the determination means, and output from the slot determined by the determination means A status signal output signal for outputting a status signal to the CPU; It is as it has.

  The second invention is an interface expansion circuit which is connected to a CPU and which controls a card or module conforming to the PCMCIA standard or CFA standard with a peripheral circuit access control signal, and controls a card or module mounted in a plurality of slots. A holding unit for holding an address signal from the CPU; a determination unit for determining a slot to be accessed based on a state of the holding unit; and an address generation for generating an effective address of a register address conforming to a predetermined standard from the holding unit Means, an address output means for outputting the effective address as an address of each slot, a control signal generating means for generating a control signal for controlling a card or a module from a control signal for peripheral circuit access, and a slot determined by the determining means Output the control signal from the control signal generator A control signal output means is a status signal outputted from the determined slot discriminating means intended and a status signal output signal to be outputted to the CPU.

  According to the present invention, since a plurality of cards or modules can be controlled by a control signal for one slot or one peripheral circuit, an interface for the card or module is expanded by effectively using resources of the CPU. Can be used.

  A first invention according to the present invention is an interface expansion circuit that is connected to a CPU including a controller that controls a card or module conforming to the PCMCIA standard or CFA standard, and controls a plurality of slots with a control signal for one slot. Generating a valid address of a register address conforming to a predetermined standard from the holding means for holding an address signal from the CPU, a determining means for determining a slot to be accessed based on the state of the holding means Discriminated by the discriminating means, address generating means for outputting the effective address as an address of each slot, control signal output means for outputting a control signal from the CPU to the slot discriminated by the discriminating means, and discriminating means Status signal output from the designated slot to the CPU In which and a status signal output signal power.

  According to the PC card interface expansion circuit according to the first aspect of the present invention, when the CPU mounted on the information processing terminal has a card or a controller that can control a module conforming to the PCMCIA standard or the CFA standard, it corresponds to one slot. Multiple control cards (up to 4 slots) or modules can be controlled by the control signal, so PC cards or CF cards or modules compliant with PCMCIA or CFA standards can be used without allocating CPU address space. CPU resources can be used effectively.

  In addition, the second invention is an interface extension for controlling a card or module connected to a CPU and controlling a card or module compliant with the PCMCIA standard or CFA standard with a peripheral circuit access control signal. A holding means for holding an address signal from the CPU; a determination means for determining a slot to be accessed based on a state of the holding means; and an effective address of a register address conforming to a predetermined standard from the holding means Address generation means for generating the effective address as the address of each slot, control signal generation means for generating a control signal for controlling the card or module from the peripheral circuit access control signal, , In the slot determined by the determining means A control signal output means for outputting a control signal from the control signal generating means, and the status signal output signal for outputting a status signal outputted from the determination slot in said discriminating means to said CPU, in which comprises a.

  According to the PC card interface expansion circuit according to the second aspect of the present invention, even when the CPU mounted on the information processing terminal does not have a card that complies with the PCMCIA standard or the CFA standard or a controller that can control the module, Multiple peripherals (up to 4 slots) of cards or modules can be controlled by the control signal of one peripheral circuit, so a PC card or CF card, or a module conforming to the PCMCIA standard or CFA standard can be used without assigning CPU I / O. It can be used in an expanded manner, and CPU resources can be used effectively.

  According to a third invention, in the first or second invention, the address generation means accesses the information table of the card or module and a configuration register for setting and monitoring the state of the card or module. A first address control unit for accessing, a second address control unit for accessing an ATA register for reading / writing data from / to the card or module, and any of the first or second address control unit And a selection unit for selecting whether to generate the effective address.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment)
An interface expansion circuit according to the present invention includes a circuit that holds an address signal output from a CPU and a bus interface circuit that connects a CPU or a card or module compliant with the PCMCIA standard or CFA standard in a microcomputer system. A circuit for generating an effective address for register access conforming to the PCMCIA standard or the CFA standard, a circuit for determining a corresponding slot from the held value, a circuit for outputting a control signal from the CPU to the determined slot, and a CPU If the output control signal is a control signal that does not conform to the PCMCIA standard or the CFA standard, a circuit that generates a control signal that conforms to the PCMCIA standard or the CFA standard is provided.

  FIG. 1 is a block diagram showing a configuration of an interface extension circuit according to an embodiment of the present invention.

  In FIG. 1, a PC card expansion circuit 100 as an interface expansion circuit of the present invention is mounted between a CPU 200 and a plurality of slots (slot 1 to slot 4).

  As shown in FIG. 1, the PC card expansion circuit 100 is connected to the CPU 200 from an address bus 111 output from the CPU 200, a control signal 112 output from the CPU 200, and a control signal 113 output to the CPU 200. Become. From the CPU 200, a data bus 210 is connected to each of the slots 300 to 600. The PC card expansion circuit 100 includes a data latch circuit 101 serving as a holding circuit for an address signal from the address bus 111, an access determination circuit 102 for determining which slot is accessed, and a PCMCIA standard or a value based on the value of the data latch circuit 101. An address conversion circuit 103 that generates an effective address for register access compliant with the CFA standard, and a control signal 112 output from the CPU 200 are assigned to the slot control signals 115, 116, 117, and the slot determined by the access determination circuit 102. The control signal output circuit 106 that outputs as 118, the status signal 1 (119) and the status signal 2 (output from the slot 1 (300), slot 2 (400), slot 3 (500), and slot 4 (600), respectively) 120), status signal 3 (121), from the status signal 4 (122), to select only the status signal of the determined slot in the access judging circuit 102, and configured by a status signal output circuit 107 for outputting to the CPU 200.

  By the way, a card and a module compliant with the PCMCIA standard and the CFA standard can be controlled by accessing the internal registers. Accessing this register requires the control signals shown in Table 1, an 11-bit address signal, and a 16-bit data signal. Further, the register control of PC cards and module parts compliant with the PCMCIA standard and the CFA standard is characterized in that the register address values are standardized and unified.

  However, cards and modules compliant with the PCMCIA standard input a 26-bit address signal, but the PC card ATA register specification uses only a 10-bit address signal. The same applies to PC cards conforming to the CF standard. That is, if the PC card conforms to the PCMCIA standard and the CF standard, the same control is performed and there is no problem.

  Next, for a card and a module compliant with the PCMCIA standard or the CFA standard, an information table (CIS: Card Information Structure) in which information of the card and the module is stored, and various settings are performed for the card and the module. A memory address space consisting of an attribute memory area in which registers (CCR: Card Configuration Register) are stored, a common memory area in which task file registers can be stored, and an I / O address space in which task file registers can be stored as in the common memory area There is.

  Whether the task file register is stored in the common memory area or the I / O address space depends on the card mode of the PC card. When the PC card operates in the memory card mode, the task file register is stored in the common memory area, and when the PC card operates in the I / O card mode, it is stored in the I / O address space. When using cards and modules compliant with the PCMCIA standard or CFA standard, first access the attribute memory area information table (CIS: Card Information Structure), obtain card and module information, and then make various settings. After performing necessary settings in a register (CCR: Card Configuration Register), the task file register is accessed to actually exchange data with the card or module. This PC card expansion circuit 100 utilizes the above-described features.

  Specific examples of the PC card expansion circuit and its control method according to the present invention will be described below in detail with reference to the drawings.

(First specific example)
FIG. 2 is a block diagram showing the configuration of the first specific example of the PC card expansion circuit according to the present invention. In this figure, when the CPU 200 has a built-in controller that can control a card or module compliant with the PCMCIA standard or CFA standard, the CPU controls a plurality of slots (maximum 4 slots) with one control signal. In the PC card expansion circuit 100 used for this purpose, the data latch circuit 101 that holds the address signal output from the CPU 200, the access determination circuit 102 that determines the slot to be accessed from the data latch circuit 101, and the data latch circuit 101 An address conversion circuit 103 that generates an effective address for register access conforming to the PCMCIA standard or the CFA standard, an address output circuit 104 that outputs an effective address generated from the address conversion circuit 103 as an address of each slot, and a CPU It is determined whether the control signal 112 from 00 conforms to the PCMCIA standard or the CFA standard, and if it conforms to the PCMCIA standard or the CFA standard, it is output as it is, and the control signal does not conform to the PCMCIA standard or the CFA standard. For example, the control signal generation circuit 105 that generates and outputs a control signal based on the PCMCIA standard or the CFA standard from the control signal, and the control signal generation circuit 105 outputs the control signal generation circuit 105 to the slot to be accessed determined by the access determination circuit 102. A control signal output circuit 106 that outputs a control signal; a status signal output circuit 107 that receives a status signal output from each slot, and determines and outputs the status signal of the slot determined by the access determination circuit 102 to the CPU 200; Features that consisted of PC card expansion circuit 100 is shown.

  In addition, the address conversion circuit 103 is configured to set and monitor a card or module information table (CIS: Card Information Structure) conforming to the PCMCIA standard or the CFA standard, and a card or module state conforming to the PCMCIA standard or the CFA standard. The data latch circuit 101 performs control for accessing the configuration register to be performed, control for accessing the ATA register for actually reading and writing data with a card or module conforming to the PCMCIA standard or CFA standard, and the like. The PC card expansion circuit is characterized in that it is configured to select which control is performed by the address signal from the CPU 200 held in the above.

  Hereinafter, the PC card expansion circuit shown in FIG. 2 will be described in more detail.

  FIG. 2 shows a PC card extension for controlling the card or module connected in four slots with a control signal for one slot in a CPU incorporating a controller that can control a card or module compliant with the PCMCIA standard or CFA standard. A circuit is shown.

  The address bus 111 in FIG. 2 is assigned the lower 10 bits of the address bus possessed by the CPU 200. In the PC card expansion circuit 100 of the present invention, this address bus 111 is given a certain rule. This constant rule (format) is shown in FIG.

From FIG. 4, the lower 2 bits are bits (ID number) indicating which slot is accessed, and the assignment of these bits is as follows.
Address (1), Address (0) Corresponding slot 0 0 Slot 1 (300)
0 1 Slot 2 (400)
1 0 Slot 3 (500)
1 1 Slot 4 (600)
Next, the lower third bit from FIG. 4 indicates whether the CPU 200 accesses the attribute memory area or the common memory area of the card or module connected to each slot. That is, when the bit is “0”, the common memory area is accessed, and when the bit is “1”, the attribute memory area is accessed.

  Here, when the third bit is “0”, the upper 8 bits of FIG. 4 are all “0”.

  This is because the attribute area of the card and module conforming to the PCMCIA standard and the CFA standard requires 000h to 3FFh, that is, a 9-bit address is required, and a valid address cannot be designated by the above-described bit assignment. Therefore, when accessing the attribute area, the address bus 111 must first output only information indicating which slot is accessed and information indicating access to the attribute area, and then outputs a valid address value. . Therefore, when accessing the attribute area, the CPU 200 actually has to access twice, but this attribute area is accessed only during the initial setting of the card or module connected to the slot, Since there is no constant access, there is almost no significant impact such as a reduction in processing speed.

  Next, when the third bit is “1”, the upper 8 bits of FIG. 4 indicate the indexed table number of the PC card ATA register.

  Table 2 shows the indexed table of the PC card ATA register and the effective address assigned to the table.

  The data latch circuit 101 in FIG. 2 delivers the lower 2 bits and lower 3 bits of FIG. Further, the remaining 8 bits are transferred to the address conversion circuit 103. However, when the CPU 200 performs attribute memory access, the lower 2 bits and lower 3 bits of the signal in FIG. 4, a total of 3 bits, are transferred to the access determination circuit 102, but the remaining 8 bits are not transferred to the address conversion. In the second access, all 11-bit signals are transferred to the address output circuit 104.

  The access determination circuit 102 in FIG. 2 outputs a 3-bit signal output from the data latch circuit 101, that is, a 2-bit signal indicating which slot is accessed, and the CPU 200 performs attribute memory access or common memory access. A 1-bit signal indicating the above is input, an output enable signal for permitting output to the address output circuit 104, the control signal output circuit 105, and the status signal output circuit 106, the control signal output circuit 105, and the status signal output circuit Information on which slot to output is delivered to 106.

  When the CPU 200 performs attribute memory access, the address determination circuit 102 holds only information about which slot is accessed in the first access, and the address output circuit 104, the control signal output circuit 105, and the status signal output circuit 106 Output enable signal is not output.

  Next, in the second access, an output enable signal is output to the held information and address output circuit 104, control signal output circuit 105, and status signal output circuit 106.

  Next, in the address conversion circuit 103 of FIG. 3, when the CPU 200 performs a common memory access, the indexed information of the PC card ATA register output from the data latch circuit 101 is converted into a valid address, and the address Delivered to the output circuit 104. The indexed table of the PC card ATA register and the effective address assigned to the table are as shown in (Table 2).

  On the other hand, when the CPU 200 performs attribute memory access, nothing is performed in the first access, and the effective address output in the second access is output to the address output circuit 104 as it is.

  2 outputs the effective address output from the address conversion circuit 103 in each slot, slot 1 (300), slot 2 based on the output enable signal output from the access determination circuit 102. (400), slot 3 (500), and slot 4 (600). When the output enable signal output from the access determination circuit 102 is “0”, the address output circuit 104 does not output, and when the output enable signal is “1”, the effective address output from the address conversion circuit 103 is changed. Output.

  Next, when the CPU 200 outputs a control signal conforming to the PCMCIA standard or the CFA standard, the control signal generation circuit 105 in FIG. 2 sets the setting pin of the control signal generation circuit 105 to directly control the control signal from the CPU 200. The control signal is output to the control signal output circuit 106. That is, when the CPU 200 outputs a control signal compliant with the PCMCIA standard or CFA standard, that is, when the CPU 200 incorporates a controller that can control a card or module compliant with the PCMCIA standard or CFA standard, By setting the setting pin to “0”, the control signal from the CPU 200 is output to the control signal output circuit 106 as it is.

  Next, the control signal output circuit 106 of FIG. 2 outputs an output enable signal output from the access determination circuit 102 to the control signal 112 output from the CPU 200 shown in (Table 1) output from the control signal generation circuit 105, and One of control signal 1 (115), control signal 2 (116), control signal 3 (117), and control signal 4 (118), which is a control signal of each slot, based on information on which slot is accessed In addition, a control signal output from the CPU 200 is output. Similar to the address output circuit 104, when the output enable signal output from the access determination circuit 102 is “0”, the control signal output circuit 105 does not output, and when the output enable signal is “1”, the control signal output The circuit 106 outputs a control signal to the corresponding slot.

  2 outputs the status signal 1 (119), status signal 2 (120), status signal 3 (121), and status signal 4 (122) output from each slot to the access determination circuit. Based on the output enable signal output from 102 and information on which slot to access, the status signal of the corresponding slot is output to the status signal of the CPU 200. Similar to the address output circuit 104 and the control signal output circuit 105, when the output enable signal output from the access determination circuit 102 is “0”, the status output circuit 107 does not input the status signal from each slot, and the output enable signal When the signal is “1”, the status signal from each slot is input and output to the status signal of the CPU 200.

  In this way, the PC card expansion circuit 100 according to the present invention performs a process as described above so that the CPU 200 mounted on the information processing terminal can control a controller or card that conforms to the PCMCIA standard or the CFA standard. If it has, a plurality of cards (up to 4 slots) or a module can be controlled by a control signal for one slot, so that it is compliant with PC card or CF card, PCMCIA standard or CFA standard without assigning address space of CPU 200 The module can be extended and used, and the resources of the CPU 200 can be used effectively.

(Second specific example)
FIG. 3 is a block diagram showing the configuration of the second specific example of the PC card expansion circuit according to the present invention.

  FIG. 3 shows the control of the card or module connected in four slots by a control signal 112 of one peripheral circuit in a CPU 200 that does not have a controller that can control a card or module compliant with the PCMCIA standard or CFA standard. A PC card expansion circuit 100 is shown.

  The PC card expansion circuit 100 of the present invention includes an address bus 111 output from the CPU 200, a control signal 112 output from the CPU 200, a control signal 113 output to the CPU 200, and a data latch circuit serving as an address signal holding circuit. 101, an access determination circuit 102 that determines which slot is accessed, an address conversion circuit 103 that generates an effective address for performing register access based on the PCMCIA standard or the CFA standard from the value of the data latch circuit 101, Determine whether the address output circuit 104 that outputs the effective address generated by the address conversion circuit 103 and the control signal 112 output from the CPU 200 conforms to the PCMCIA standard or the CFA standard, and conforms to the PCMCIA standard or the CFA standard What If there is a control signal that is output as it is and does not comply with the PCMCIA standard or CFA standard, a control signal generation circuit 105 that generates and outputs a control signal compliant with the PCMCIA standard or CFA standard from the control signal, and access determination The control signal output circuit 106 that outputs the slot control signal 1 (115), the control signal 2 (116), the control signal 3 (117), and the control signal 4 (118) to the slot determined by the circuit 102, and the slot 1 (300 ), Status signal 1 (119), status signal 2 (120), status signal 3 (121), status signal 4 (output from slot 2 (400), slot 3 (500), and slot 4 (600), respectively. 122), select only the control signal of the slot determined by the access determination circuit 102, Having a status signal output circuit 107 for outputting to PU200.

  In the address bus 111 in FIG. 3, the lower 10 bits of the address bus of the CPU 200 are assigned. In the PC card expansion circuit 100 of the present invention, this address bus 111 is given a certain rule. This fixed rule (format) is as shown in FIG.

As shown in FIG. 4, the lower 2 bits are bits indicating which slot is accessed, and the allocation of these bits is as follows.
Address (1), Address (0) Corresponding slot 0 0 Slot 1 (300)
0 1 Slot 2 (400)
1 0 Slot 3 (500)
1 1 Slot 4 (600)
Next, the lower third bit from FIG. 4 indicates whether the CPU 200 accesses the attribute memory area or the common memory area of the card or module connected to each slot. That is, when the bit is “0”, the common memory area is accessed, and when the bit is “1”, the attribute memory area is accessed.

  Here, when the third bit is “0”, the upper 8 bits in FIG. 3 are all “0”.

  This is because the attribute area of the card and module conforming to the PCMCIA standard and the CFA standard requires 000h to 3FFh, that is, a 9-bit address is required, and a valid address cannot be designated by the above-described bit assignment. Therefore, when accessing the attribute area, the address bus (111) first outputs only information about which slot to access and information to access the attribute attribute area, and then outputs a valid address value. There must be. Therefore, when accessing the attribute area, the CPU 200 actually has to access twice, but this attribute area is accessed only during the initial setting of the card or module connected to the slot, Since there is no constant access, there is almost no significant impact such as a reduction in processing speed.

  Next, when the third bit is “1”, the upper 8 bits of FIG. 4 indicate the indexed table number of the PC card ATA register. Table 2 shows the indexed table of the PC card ATA register and the effective address assigned to the table.

  The data latch circuit 101 in FIG. 3 delivers the lower 2 bits and lower 3 bits of FIG. 4, a total of 3 bits, to the access determination circuit 102. Further, the remaining 8 bits are transferred to the address conversion circuit 103. However, when the CPU 200 performs attribute memory access, the lower 2 bits and lower 3 bits of the signal in FIG. 4, a total of 3 bits, are transferred to the access determination circuit 102, but the remaining 8 bits are not transferred to the address conversion. In the second access, all 11-bit signals are transferred to the address output circuit 104.

  The access determination circuit 102 in FIG. 3 performs a 3-bit signal output from the data latch circuit 101, that is, a 2-bit signal indicating which slot is accessed, and whether the CPU 200 performs attribute memory access or common memory access. A 1-bit signal indicating the above is input, an output enable signal for permitting output to the address output circuit 104, the control signal output circuit 106, and the status signal output circuit 107, the control signal output circuit 106, and the status signal output circuit Information on which slot to output is delivered to 107.

  When the CPU 200 performs attribute memory access, the address determination circuit 102 holds only information about which slot is accessed in the first access, and the address output circuit 104, the control signal output circuit 106, and the status signal output circuit 107 Output enable signal is not output.

  Next, in the second access, an output enable signal is output to the stored information and address output circuit 104, control signal output circuit 106, and status signal output circuit 107.

  Next, in the address conversion circuit 103 of FIG. 3, when the CPU 200 performs a common memory access, the indexed information of the PC card ATA register output from the data latch circuit 101 is converted into a valid address, and the address Delivered to the output circuit 104. The indexed table of the PC card ATA register and the effective address assigned to the table are as described above (Table 2).

  On the other hand, when the CPU 200 performs attribute memory access, nothing is performed in the first access, and the effective address output in the second access is output to the address output circuit 104 as it is.

  Next, the address output circuit 104 in FIG. 3 uses the effective address output from the address conversion circuit 103 based on the output enable signal output from the access determination circuit 102 in each slot, slot 1 (300), slot 2 and so on. (400), slot 3 (500), and slot 4 (600). When the output enable signal output from the access determination circuit 102 is “0”, the address output circuit 104 does not output, and when the output enable signal is “1”, the effective address output from the address conversion circuit 103 is changed. Output.

  Next, the control signal generation circuit 105 in FIG. 3 generates a control signal based on the PCMCIA standard or the CFA standard from the control signal output from the CPU 200. By setting the control signal generation setting pin to “1”, a control signal based on the PCMCIA standard and the CFA standard is generated from the control signal from the CPU 200, and is output to the control signal output circuit 106.

  Next, the control signal output circuit 106 in FIG. 3 uses the control signal generated by the control signal generation circuit 105 based on the output enable signal output from the access determination circuit 102 and information on which slot is accessed. The control signal 1 (115), the control signal 2 (116), the control signal 3 (117), or the control signal 4 (118), which is a control signal of each slot, is output. Similar to the address output circuit 104, when the output enable signal output from the access determination circuit 102 is "0", the control signal output circuit 106 does not output, and when the output enable signal is "1", the control signal output The circuit 106 outputs a control signal to the corresponding slot.

  3 outputs the status signal 1 (119), status signal 2 (120), status signal 3 (121), and status signal 4 (122) output from each slot to the access determination circuit. Based on the output enable signal output from 102 and information on which slot to access, the status signal of the corresponding slot is output to the status signal of the CPU 200. Similar to the address output circuit 104 and the control signal output circuit 106, when the output enable signal output from the access determination circuit 102 is “0”, the status output circuit 107 does not input the status signal from each slot, and the output enable signal When the signal is “1”, the status signal from each slot is input and output to the status signal of the CPU 200.

  In this way, the PC card expansion circuit 100 according to the present invention performs a process as described above so that the CPU 200 mounted on the information processing terminal can control a controller or card that conforms to the PCMCIA standard or the CFA standard. Even if not, a plurality of (up to 4 slots) cards or modules can be controlled by a control signal of one peripheral circuit, so that the PC card or CF card or PCMCIA standard or CFA standard without assigning the I / O of the CPU 200 Can be expanded and used, and the resources of the CPU 200 can be used effectively.

  In the first specific example and the second specific example described above, it is assumed that four PCMCIA standard or CFA standard cards and modules are connected to the PC card expansion circuit of the present invention. Even if two or three cards and modules are used, control can be performed without any problem. The PC card expansion circuit of the present invention is also applicable to a system in which the CPU to be connected does not include a controller that can control a card or module compliant with the PCMCIA standard and the CFA standard and only one card and module are connected. It is possible to flexibly cope with future slot expansion without the need to newly use or allocate CPU resources.

  The interface expansion circuit according to the present invention can be used not only in portable terminal devices that are required to be further reduced in size and performance in the future, but also in a plurality of simultaneous use of PC cards (or modules) having different purposes of use. It can be applied to usages that you want to use.

The block diagram which shows the structure of the PC card expansion circuit by embodiment of this invention Block diagram showing a first specific example of the PC card expansion circuit Block diagram showing a second specific example of the PC card expansion circuit The figure which shows the format of the address input signal of the PC card expansion circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 PC card expansion circuit 101 Data latch circuit 102 Access determination circuit 103 Address conversion circuit 104 Address output circuit 105 Control signal generation circuit 106 Control signal output circuit 107 Status signal output circuit 111 Address bus 112, 113 Control signal 115-118 Slot control signal 119 to 122 Status signal 200 CPU
210 Data bus 300, 400, 500, 6000 PC card slot

Claims (3)

An interface expansion circuit connected to a CPU including a controller for controlling a card or module compliant with the PCMCIA standard or CFA standard, and controlling a plurality of slots with a control signal for one slot,
Holding means for holding an address signal from the CPU;
Discriminating means for discriminating a slot to be accessed based on the state of the holding means;
Address generating means for generating an effective address of a register address conforming to a predetermined standard from the holding means;
Address output means for outputting the effective address as an address of each slot;
Control signal output means for outputting a control signal from the CPU to the slot determined by the determination means;
An interface expansion circuit comprising: a status signal output signal that outputs a status signal output from the slot determined by the determination means to the CPU. An interface expansion circuit that is connected to a CPU and controls a card or module that conforms to the PCMCIA standard or CFA standard with a peripheral circuit access control signal, and controls the card or module mounted in a plurality of slots,
Holding means for holding an address signal from the CPU;
Discriminating means for discriminating a slot to be accessed based on the state of the holding means;
Address generating means for generating an effective address of a register address conforming to a predetermined standard from the holding means;
Address output means for outputting the effective address as an address of each slot;
Control signal generating means for generating a control signal for controlling the card or module from the control signal for peripheral circuit access;
Control signal output means for outputting a control signal from the control signal generation means to the slot determined by the determination means;
An interface expansion circuit comprising: a status signal output signal that outputs a status signal output from the slot determined by the determination means to the CPU. The address generation means includes an information table for the card or module, a first address control unit for accessing a configuration register for setting and monitoring the state of the card or module, the card or module and data A second address control unit for accessing an ATA register for reading and writing; and a selection unit for selecting whether the first or second address control unit generates the effective address. The interface expansion circuit according to claim 1 or 2.

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