JP2006099288A - Bus sharing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus sharing system capable of grasping the use condition of a bus by means of a simple circuit configuration. <P>SOLUTION: The bus sharing system comprises a module 101 and a module 102, which are two bus masters exclusively sharing a serial cable 103. The module 101 includes an N-ch open drain 12 connected via a resistance element R2 to a signal line 104 connected to the module 102 and to which a predetermined voltage is applied; an A/D converter 13 for measuring a potential difference Vad on the signal line 104 side of the resistance element R2; and a transmission/reception control part 14 for determining the use condition of the bus according to the potential difference Vad measured by the A/D converter 13. In this way it is possible to grasp using a simple configuration the use condition of the bus. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus sharing system including a plurality of bus masters that exclusively share a bus.

  Conventionally, in a bus sharing system consisting of a plurality of bus masters that exclusively share the bus, each bus master uses the bus after making a request to use the bus, but in this case, there is a conflict with other bus masters If this is the case, arbitration of the right to use the bus (hereinafter referred to as the bus right) is required.

  As a bus right arbitration method, there are a method often used in bus arbitration between a plurality of CPUs (hereinafter referred to as a CPU method), a method used in I2C (hereinafter referred to as an I2C method), and the like.

  For example, in the CPU system, each bus master requests a bus right from the super master, and the super master arbitrates to give the bus right.

  In the I2C method, priorities are assigned at the time of slave address assignment of each slave, and the bus right is given to a bus master that accesses a slave having a higher priority.

  However, in the CPU system, it is necessary to provide a super master for arbitrating the bus right in addition to each bus master, which causes a problem that the circuit configuration becomes very complicated.

  Further, in the I2C method, it is necessary to assign a slave address to each bus master, which causes a problem that the communication protocol at that time becomes very complicated.

  Therefore, in Patent Document 1, bus masters having open collectors in a circuit that outputs a connection request are connected by a single signal line, the bus use state is monitored by a signal flowing through the signal line, and arbitration of the bus right is performed. Techniques for performing are disclosed.

In this way, if arbitration of the bus right is performed by a signal flowing through one signal line, it is not necessary to provide a super master for arbitrating the bus right in addition to each bus master as in the CPU system. Therefore, the circuit configuration is simplified. Further, unlike the I2C method, it is not necessary to assign a slave address to each bus master, so that no complicated communication protocol is required.
JP 2-165362 (released on June 26, 1990)

  However, the technique disclosed in Patent Document 1 requires a complicated circuit (arbitration circuit as shown in FIG. 2) in order to grasp the usage state of the bus.

  Therefore, the bus sharing system must have a complicated circuit configuration.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a bus sharing system capable of grasping the bus use state with a simple circuit configuration.

  In order to solve the above problems, a bus sharing system according to the present invention is a bus sharing system including a plurality of bus masters that exclusively share a bus. The bus master is connected to another bus master and a predetermined voltage is applied. An output circuit that outputs a high level or a low level indicating whether or not a bus is requested to be applied to the applied signal line via a resistance element; a potential difference measurement circuit that measures a potential difference on the signal line side of the resistance element; and And a bus usage state determination circuit that determines a bus usage state based on the potential difference measured by the potential difference measurement circuit.

  The voltage applied to the signal line varies depending on the level output from the output circuit of each bus master. That is, the potential of the signal line varies depending on whether the output from the output circuit of each bus master is at a high level or a low level. By utilizing this characteristic and measuring the potential difference of the signal lines with each bus master, it becomes possible to determine whether or not each bus master has a bus use request.

  Therefore, as in the above configuration, each bus master measures the potential difference between the signal lines connecting the bus masters by the potential difference measurement circuit provided to each bus master, and based on the potential difference measured by the bus use state determination circuit. The use state of the bus can be determined.

  In this way, since the bus master itself can grasp the bus usage status with a simple circuit configuration that only measures the potential difference between the signal lines connecting the bus masters, a super master for bus arbitration is separately provided. There is no need to provide it. For this reason, it is not necessary to provide a plurality of wires as in the case of performing bus arbitration by providing a super master, and bus arbitration can be performed with a simple circuit configuration of only one signal line.

  From the above, the present invention is particularly suitable for a circuit in which the number of signal lines cannot be increased more than necessary.

  Furthermore, the structure which made the resistance value of one resistance element differ from the resistance value of another resistance element among each said resistance element may be sufficient.

  In this case, if the resistance values of the resistance elements are different, the potential difference of the signal lines is different even if each bus master is in the same bus use state. Therefore, the priority order for acquiring the bus right of the bus master can be set according to this different potential difference. it can. As a result, since it is not necessary to assign a slave address to each bus master in order to set the priority order to the bus master as in the prior art, a complicated protocol for communication is not required.

  Further, the output circuit may be configured as an open drain, a pull-up resistor element may be provided on the signal line, and the potential difference measuring circuit may be configured as an analog / digital converter (A / D converter). Good.

  In this case, the arbitration of the bus right can be performed only by providing one signal line for connecting the open drains, so that the circuit configuration can be simplified. In addition, since the A / D converter only detects the potential difference between the signal lines, it does not require a high-accuracy one, and an inexpensive A / D converter with low power consumption and relatively low accuracy can be used. .

  Of the above resistance elements, the resistance value of one resistance element may be different from the resistance value of another resistance element.

  As described above, the priority order of each bus master can be easily assigned only by changing the resistance values of the resistance elements.

  In the bus sharing system according to the present invention, as described above, the bus master is connected to other bus masters, and a high voltage indicating whether or not there is a bus use request via a resistance element is applied to a signal line to which a predetermined voltage is applied. Output circuit that outputs a level or low level, a potential difference measurement circuit that measures a potential difference on the signal line side of the resistance element, and a bus use that determines a bus use state based on a potential difference measured by the potential difference measurement circuit By providing the state determination circuit, the bus master itself can grasp the bus use state with a simple circuit configuration in which only the potential difference between the signal lines connecting the bus masters is measured.

  The embodiment of the present invention will be described as follows.

  In the bus sharing system according to the present embodiment, as shown in FIG. 1, the modules 101 and 102 as two bus masters are connected by a serial cable 103 as a bus, and the use state of the bus is grasped. The signal line 104 is used for connection.

  The module 101 includes a data transmission / reception unit 11 that transmits and receives clocks and data to and from the module 102, an N-ch open drain 12 (output circuit), an A / D converter 13 (potential difference measurement circuit), and these circuits. And a transmission / reception control unit 14 (bus use state determination circuit) for controlling transmission / reception of signals.

  The data transmitter / receiver 11 transmits and receives a clock signal and a data signal via the serial cable 103.

  The N-ch open drain 12 has an output terminal in a high-impedance state or a low level depending on whether or not there is a bus use request, and this output terminal is connected to the signal line 104 of the potential difference Vad via the resistor element R2. Yes.

  The signal line 104 is connected to a power supply voltage Vdd and connected to a pull-up resistor element R1 for holding a potential when the N-ch open drain 12 is in a high impedance state.

  Thereby, at the output terminal of the N-ch open drain 12, in addition to the low level, the high level by the pull-up is maintained in the high impedance state. That is, the N-ch open drain 12 functions as an output circuit that performs low-level or high-level output.

  The A / D converter 13 is connected to the side of the resistance element R2 opposite to the connection side of the N-ch open drain 12, and functions as a potential difference measuring circuit that measures the potential difference Vad on the signal line 104. Have.

  The transmission / reception control unit 14 has a function as a bus right arbitration unit that determines the bus use state based on the potential difference measured by the A / D converter 13 and arbitrates the bus right.

  Specifically, in the bus sharing system shown in FIG. 1, the power supply voltage Vdd is connected to the signal line 104 via the resistance element R <b> 1, and the potential difference Vad at this connection point is measured by the A / D converter 13. Then, the transmission / reception control unit 14 executes a bus right determination process based on the measured potential difference Vad.

  Since the module 102 has the same configuration as the module 101, the description thereof is omitted. However, the resistor R3 is connected to the N-ch open drain 12 of the module 102.

  In the bus sharing system shown in FIG. 1, the module 101 and the module 102 have different resistance values between the module 101 side resistance element R2 and the module 102 side resistance element R3. (Priority order) can be given. On the other hand, if the resistance values of the resistance elements R2 and R3 are the same, there is no priority between the module 101 and the module 102.

  The flow of the bus right determination process by the bus sharing system configured as described above will be described below.

  First, the bus right determination process when there is no priority between the modules 101 and 102 will be described. Here, the power supply potential Vdd = 3.0V, the resistance value of the resistance element R1 = 50 kΩ, the resistance value of the resistance element R2 = the resistance value of the resistance element R3 = 100 kΩ. Under this condition, the potential difference Vad changes as shown in Table 1 below depending on the terminal states of the N-ch open drain 12 of the module 101 and the module 102. In other words, this potential difference Vad indicates the state of each other's modules, and it can also be understood where the bus right is.

  In Table 1, mod 1 indicates the terminal state of the N-ch open drain 12 of the module 101, and mod 2 indicates the terminal state of the N-ch open drain 12 of the module 102.

  For example, if the potential difference Vad detected by the A / D converter 13 is 3.0 V, it can be seen that the terminals of the N-ch open drain 12 are in a high impedance state (Hi-Z) in both the module 101 and the module 102. Show no state, bus claim to each other.

  If the potential difference Vad detected by the A / D converter 13 is 2.0 V, it can be seen that the terminal of the N-ch open drain 12 of either the module 101 or the module 102 is at a low level (Low). In this case, the module having the low-level terminal of the N-ch open drain 12 has the bus right.

  Furthermore, if the potential difference Vad detected by the A / D converter 13 is 1.5 V, it can be seen that both the module 101 and the module 102 are in a state of claiming the bus right. In this case, since the bus is in contention, the module from which will give up the bus right.

  In consideration of the above, the flow of the bus right determination process when there is no priority will be described below with reference to the flowchart shown in FIG. Here, the operation on the module 101 side will be described.

  First, it is determined whether or not the potential difference Vad detected by the A / D converter 13 is 3.0 V (step S1). Here, when it is determined that Vad = 3.0 V, both the terminal of the N-ch open drain 12 of itself and the terminal of the N-ch open drain 12 of the module 102 which is the communication partner are in a high impedance state (Hi− Z). Therefore, the process proceeds to step S2 to determine whether or not there is a data transmission request from the transmission / reception control unit 14.

  On the other hand, if it is determined in step S1 that Vad = 3.0 V, the terminal of the N-ch open drain 12 of the counterpart module 102 is Low, that is, the bus right is claimed. Therefore, the process proceeds to step S3, and a reception process for receiving data from the module 102 is performed.

  In step S2, if there is a transmission request from the transmission / reception control unit 14, the terminal of the N-ch open drain 12, that is, the open drain buffer is set to low (step S4). On the other hand, if there is no transmission request from the transmission / reception control unit 14 in step S2, the process proceeds to step S1 to determine again whether the potential difference Vad detected by the A / D converter 13 is 3.0V.

  Then, it is determined whether or not the potential difference Vad is 2.0 V (step S5). Here, if it is determined that Vad = 2.0V, it means that the bus right is secured, and data transmission processing is performed (step S6).

  Next, when the transmission process is completed, the terminal of the N-ch open drain 12 is set to Hi-Z again, and the process proceeds to step S1.

  On the other hand, if it is determined in step S5 that Vad = 2.0V, since the bus right is not secured, the process waits for a predetermined time (step S8), and again whether Vad = 2.0. It is determined whether or not (step S9). Here, if it is determined that Vad = 2.0, the bus right has been secured, so the process proceeds to step S6 to perform data transmission processing.

  On the other hand, if it is determined in step S9 that Vad = 2.0V, the process proceeds to step S10, and the open drain buffer that is the terminal of the N-ch open drain 12 is set to Hi-Z.

  Then, it waits again for a predetermined time (step S11).

  Subsequently, it is determined whether or not the potential difference Vad is 3.0 V (step S12). Here, if Vad = 3.0 V, the process proceeds to step S4, and the terminal of the N-ch open drain 12 is set to Low.

  On the other hand, if it is determined in step S12 that Vad = 3.0 V, the module 102 on the other side claims the bus right, and the process proceeds to step S3 to perform data reception processing.

  As described above, in the bus sharing system configured as described above, the modules 101 and 102 as the bus masters measure the potential difference Vad of the signal line 104 connecting the modules by the A / D converter 13 provided in each. Thus, it is possible to grasp the use state of the serial cable 103 serving as a bus from the measured potential difference Vad.

  In this way, the use state of the serial cable 103 in which the module itself is a bus can be grasped with a simple circuit configuration in which only the potential difference Vad between the signal lines 104 connecting the modules is measured.

  In addition, a resistor element R2 (R3) is provided between the signal output terminal of the N-ch open drain 12 and the signal line 104, and the A / D converter 13 receives the signal from the resistor element R2 (R3). Since the potential difference Vad at the terminal portion on the line 104 side is measured, the change in the potential difference Vad of the signal line 104 can be increased.

  Thereby, as the A / D converter 13, an inexpensive A / D converter having low power consumption of about several bits and not so high can be used, so that a bus sharing system can be created at low cost. it can.

  Further, the priority order of bus right acquisition is set by making the resistance value of at least one resistance element of the resistance element R2 (R3) connected to each module different from the resistance value of other resistance elements. be able to. That is, if the resistance value of the resistance element is different, the potential difference Vad of the signal line 104 in the bus use state is different, and therefore, the priority order of the bus use of the module can be assigned according to the different potential difference Vad.

  Next, bus right determination processing when there is a priority between the modules 101 and 102 will be described. Here, the power supply potential Vdd = 3.0V, the resistance value of the resistance element R1 = the resistance value of the resistance element R2 = 50 kΩ, and the resistance value of the resistance element R3 = 100 kΩ. Under this condition, the module 101 has a higher priority than the module 102.

  Also in this case, the potential difference Vad changes as shown in the following Table 2 depending on the terminal state of the N-ch open drain 12 of the module 101 and the module 102. You can see where is.

  In Table 2, mod 1 indicates the terminal state of the N-ch open drain 12 of the module 101, and mod 2 indicates the terminal state of the N-ch open drain 12 of the module 102.

  For example, if the potential difference Vad detected by the A / D converter 13 is 3.0 V, it can be seen that the terminals of the N-ch open drain 12 are in a high impedance state (Hi-Z) in both the module 101 and the module 102. Show no state, bus claim to each other.

  If the potential difference Vad detected by the A / D converter 13 is 1.5 V, it can be seen that the terminal of the N-ch open drain 12 of the module 101 is at a low level (Low). In this case, the module 101 having the N-ch open drain 12 terminal at the low level has the bus right.

  If the potential difference Vad detected by the A / D converter 13 is 2.0 V, it can be seen that the terminal of the N-ch open drain 12 of the module 102 is at a low level (Low). In this case, the module 102 having the low-level terminal of the N-ch open drain 12 has the bus right.

  Further, if the potential difference Vad detected by the A / D converter 13 is 1.2 V, it can be seen that both the module 101 and the module 102 are in a state of claiming the bus right. In this case, since the buses are in contention, the bus master with the higher priority waits for the other party to give up the bus right, and the bus master with the lower priority gives up the bus right.

  In consideration of the above, the flow of bus right determination processing in the case of priority is described below with reference to the flowcharts shown in FIGS. Here, description will be made assuming that the priority order for acquiring the bus right of the module 101 is higher than that of the module 102. 3 shows the flow of processing as the operation on the module 101 side, and FIG. 4 shows the flow of processing as the operation on the module 102 side.

  First, the processing flow on the higher priority side (module 101 side) will be described below with reference to FIG.

  First, it is determined whether or not the potential difference Vad detected by the A / D converter 13 is 3.0 V (step S21). Here, when it is determined that Vad = 3.0 V, both the terminal of the N-ch open drain 12 of itself and the terminal of the N-ch open drain 12 of the module 102 which is the communication partner are in a high impedance state (Hi− Z). Therefore, the process proceeds to step S2 to determine whether or not there is a data transmission request from the transmission / reception control unit 14.

  On the other hand, if it is determined in step S21 that Vad = 3.0V, the terminal of the N-ch open drain 12 of the counterpart module 102 is Low, that is, the bus right is claimed. Therefore, the process proceeds to step S23, and a reception process for receiving data from the module 102 is performed.

  In step S22, if there is a transmission request from the transmission / reception control unit 14, the terminal of the N-ch open drain 12, that is, the open drain buffer is set to low (step S24). On the other hand, if there is no transmission request from the transmission / reception control unit 14 in step S22, the process proceeds to step S21 to determine again whether or not the potential difference Vad detected by the A / D converter 13 is 3.0V.

  Then, it is determined whether or not the potential difference Vad is 1.5 V (step S25). If it is determined that Vad = 1.5V, the bus right is secured and data transmission processing is performed (step S26).

  Next, when the transmission process is completed, the open drain buffer that is the terminal of the N-ch open drain 12 is set to Hi-Z (step S27), and the process proceeds to step S21.

  Next, the flow of processing on the lower priority side (module 102 side) will be described below with reference to FIG.

  First, it is determined whether or not the potential difference Vad detected by the A / D converter 13 is 3.0 V (step S31). Here, when it is determined that Vad = 3.0 V, both the terminal of the N-ch open drain 12 of the own device and the terminal of the N-ch open drain 12 of the module 101 which is the communication counterpart are both in a high impedance state (Hi− Z). Accordingly, the process proceeds to step S32, and it is determined whether or not there is a data transmission request from the transmission / reception control unit 14.

  On the other hand, if it is determined in step S31 that Vad = 3.0 V, the terminal of the N-ch open drain 12 of the counterpart module 101 is Low, that is, the bus right is claimed. Therefore, the process proceeds to step S33, and a reception process for receiving data from the module 101 is performed.

  In step S32, if there is a transmission request from the transmission / reception control unit 14, the terminal of the N-ch open drain 12, that is, the open drain buffer is set to low (step S34). On the other hand, if there is no transmission request from the transmission / reception control unit 14 in step S32, the process proceeds to step S31, and it is determined again whether or not the potential difference Vad detected by the A / D converter 13 is 3.0V.

  Then, it is determined whether or not the potential difference Vad is 2.0 V (step S35). Here, if it is determined that Vad = 2.0 V, the bus right is secured, and data transmission processing is performed (step S36).

  Next, when the transmission process is completed, the open drain buffer which is the terminal of the N-ch open drain 12 is set to Hi-Z (step S37). Control goes to step S31.

  On the other hand, if it is determined in step S35 that Vad is not 2.0, it is assumed that the counterpart module 101 is requesting the bus right, so the open drain buffer is set to Hi-Z (step S38). In step S33, data is received from the module 101 side.

  As described above, the priority order for acquiring the bus right can be assigned simply by changing the resistance value of the resistance element connected to the module, so it is necessary to provide a special arbitration circuit for the bus right arbitration. There is no. As a result, even when priority is assigned to each module, the bus right determination process can be performed without using a complicated communication protocol as in the I2C method.

  Further, in this embodiment, since one signal line is added, the present invention can be effectively applied particularly to a field where the number of signal lines cannot be increased, such as a mobile phone.

  In this embodiment, the case where two bus masters (modules 101 and 102) share one bus (serial cable 103) has been described. However, the present invention is not limited to this. The present invention can be applied even when one bus is shared.

  An example in which there are three bus masters sharing one bus will be described below with reference to FIGS.

  The bus sharing system shown in FIG. 5 is obtained by adding a module 201 to the bus sharing system shown in FIG.

  Here, the three modules are connected to the serial cable 103 and the signal line 104 so as to have a corresponding relationship. That is, in the module 201, the signal line 104 is connected to the N-ch open drain 12 via the resistance element R4.

  The A / D converter 13 is connected to the side of the resistance element R4 opposite to the connection side of the N-ch open drain 12, and functions as a potential difference measurement circuit that measures the potential difference Vad on the signal line 104. have.

  That is, the module 201 includes each unit having the same function as the module 102 described above, and thus description of the function of each unit is omitted.

  The flow of the bus right determination process by the bus sharing system configured as described above will be described below.

  Here, a bus right determination process when there is no priority among the modules 101, 102, and 201 will be described. Here, the power supply potential Vdd = 3.0 V, the resistance value of the resistance element R1 = 30 kΩ, the resistance value of the resistance element R2 = the resistance value of the resistance element R3 = the resistance value of the resistance element R4 = 30 kΩ. Under this condition, the potential difference Vad changes as shown in Table 3 below depending on the terminal states of the N-ch open drain 12 of the module 101, the module 102, and the module 201. That is, the potential difference Vad indicates the state of each module, and it can also be understood which module has the bus right.

  In Table 3, mod 1 indicates the terminal state of the N-ch open drain 12 of the module 101, mod 2 indicates the terminal state of the N-ch open drain 12 of the module 102, and mod 3 indicates the N-ch open drain 12 of the module 201. The pin state is shown.

  For example, if the potential difference Vad detected by the A / D converter 13 is 3.0 V, all of the module 101, the module 102, and the module 201 have the N-ch open drain 12 terminal in the high impedance state (Hi-Z). It turns out that there is, and shows the state that does not claim the bus right to each other.

  If the potential difference Vad detected by the A / D converter 13 is 1.5 V, it can be seen that the terminal of the N-ch open drain 12 of the module 101, the module 102, or the module 201 is at a low level (Low). . In this case, the module having the low-level terminal of the N-ch open drain 12 has the bus right.

  Furthermore, if the potential difference Vad detected by the A / D converter 13 is 1.0 V, it can be seen that two of the modules 101, 102, and 201 claim the bus right. In this case, since the bus is in contention, the module from which will give up the bus right.

  If the potential difference Vad detected by the A / D converter 13 is 0.75 V, it can be seen that all of the module 101, the module 102, and the module 201 are in a state of claiming the bus right. In this case, since the buses are in conflict, any two modules will give up the bus right.

  In consideration of the above, the flow of the bus right determination process when there is no priority will be described below with reference to the flowchart shown in FIG. Here, the operation on the module 101 side will be described.

  First, it is determined whether or not the potential difference Vad detected by the A / D converter 13 is 3.0 V (step S41). Here, when it is determined that Vad = 3.0 V, both the terminal of the N-ch open drain 12 of itself and the terminals of the N-ch open drain 12 of the modules 102 and 201 which are communication partners are in a high impedance state ( Hi-Z). Accordingly, the process proceeds to step S42, and it is determined whether or not there is a data transmission request from the transmission / reception control unit 14.

  On the other hand, when it is determined in step S41 that Vad = 3.0V, the terminal of the N-ch open drain 12 of at least one of the module 102 and the module 201 on the other side is Low, that is, the bus right Therefore, the process proceeds to step S43, and a reception process for receiving data from at least one of the module 102 and the module 201 is performed.

  In step S42, if there is a transmission request from the transmission / reception control unit 14, the terminal of the N-ch open drain 12, that is, the open drain buffer is set to low (step S44). On the other hand, if there is no transmission request from the transmission / reception control unit 14 in step S42, the process proceeds to step S1 to determine again whether or not the potential difference Vad detected by the A / D converter 13 is 3.0V.

  Then, it is determined whether or not the potential difference Vad is 1.5 V (step S45). Here, if it is determined that Vad = 1.5 V, it means that the bus right has been secured, and data transmission processing is performed (step S46).

  Next, when the transmission process is completed, the terminal of the N-ch open drain 12 is set to Hi-Z again, and the process proceeds to step S41.

  On the other hand, if it is determined in step S45 that Vad is not 1.5V, the bus right is not secured, so the system waits for a predetermined time (step S48). Then, is Vad = 1.5V again? It is determined whether or not (step S49). Here, if it is determined that Vad = 1.5V, the bus right has been secured, so the process proceeds to step S46 to perform data transmission processing.

  On the other hand, if it is determined in step S49 that Vad = 1.5V, the process proceeds to step S50, and the open drain buffer that is the terminal of the N-ch open drain 12 is set to Hi-Z.

  Then, it waits again for a predetermined time (step S51).

  Subsequently, it is determined whether or not the potential difference Vad is 3.0 V (step S52). Here, if Vad = 3.0V, the process proceeds to step S44, and the terminal of the N-ch open drain 12 is set to Low.

  On the other hand, if it is determined in step S52 that Vad is not 3.0 V, at least one of the partner module 102 and module 201 claims the bus right, and the process proceeds to step S43 to receive data. I do.

  In this way, even in the case of three modules, that is, in the case of three bus masters, almost the same processing can be performed as in the case of two bus masters, and thus the same effect is produced. Therefore, even when there are four or more bus masters, almost the same processing as in the case of two bus masters can be performed.

  In the description of the processing in FIG. 6, the case where the resistance values of the resistance elements R2, R3, and R4 connected to the respective bus masters are the same is described. You may make it give a priority. The processing in this case is almost the same as the processing shown in FIGS. 3 and 4, and is omitted here.

  In this embodiment, an example in which the N-ch open drain 12 is used as the output circuit provided in each module has been described. However, the present invention is not limited to this. For example, an open collector may be used. Good. It can also be realized by using a P-ch open drain and pulling down the signal line 104. In this case, the potential is opposite to that in the case of the N-ch open drain, but the bus right can be arbitrated by the same control.

  Furthermore, the present invention can be applied even if a tri-state buffer is used instead of the N-ch open drain 12.

  Furthermore, in the present embodiment, an example in which the A / D converter 13 is used as the potential difference measuring circuit provided in each module has been described. However, the present invention is not limited to this, and if the potential difference number level is determined. For example, a comparator or a detector may be used.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  That is, the present invention is not limited to the case where the serial cable 103 is used as the bus shown in the embodiment, and can be applied to various buses such as a parallel bus system.

  In addition, each module and each processing step of the bus sharing system of the above embodiment is such that a calculation unit such as a CPU executes a program stored in a storage unit such as a ROM or a RAM, and an input unit such as a keyboard, a display, or the like. It can be realized by controlling output means or communication means such as an interface circuit. Therefore, various functions and various processes of the bus sharing system of the present embodiment can be realized simply by a computer having these means reading the recording medium storing the program and executing the program.

  As the recording medium, a memory (not shown) such as a ROM may be used as a program medium for processing by the microcomputer, and a program reader is provided as an external storage device (not shown). It may be a program medium that can be read by inserting a recording medium therein.

  In any case, the stored program is preferably configured to be accessed and executed by the microprocessor. Furthermore, it is preferable that the program is read out, and the read program is downloaded to the program storage area of the microcomputer and the program is executed. It is assumed that the download program is stored in the main device in advance.

  The program medium is a recording medium configured to be separable from the main body, such as a tape system such as a magnetic tape or a cassette tape, a magnetic disk such as a flexible disk or a hard disk, or a disk such as a CD / MO / MD / DVD. Fixed disk system, card system such as IC card (including memory card), or semiconductor memory such as mask ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash ROM, etc. In particular, there are recording media that carry programs.

  In addition, if the system configuration is capable of connecting to a communication network including the Internet, the recording medium is preferably a recording medium that fluidly carries the program so as to download the program from the communication network.

  Further, when the program is downloaded from the communication network as described above, it is preferable that the download program is stored in the main device in advance or installed from another recording medium.

  The bus sharing system according to the present invention can be applied to any system as long as it is a bus master device that exclusively shares the bus, and is particularly effective in the field of devices in which signal lines cannot be increased, such as mobile phones. it can.

1, showing an embodiment of the present invention, is a block diagram showing a main configuration of a bus sharing system. FIG. 2 is a flowchart showing a flow of processing for grasping a bus usage state when priority is not set between bus masters in the bus sharing system shown in FIG. 1. In the bus sharing system shown in FIG. 1, it is a flowchart which shows the flow of a process for grasping | ascertaining the bus use state in the bus master of a high priority side, when the priority is set between bus masters. In the bus sharing system shown in FIG. 1, it is a flowchart which shows the flow of a process for grasping | ascertaining the bus use state in the bus master of a low priority order, when priority is set between bus masters. FIG. 10 is a block diagram showing another embodiment of the present invention and showing a configuration of main parts of a bus sharing system. FIG. 6 is a flowchart showing a flow of processing for grasping a bus use state when priority is not set between bus masters in the bus sharing system shown in FIG. 5.

Explanation of symbols

11 Data transceiver 12 N-ch open drain (output circuit)
13 A / D converter (potential difference measurement circuit)
14 Transmission / reception control unit (bus usage status determination circuit)
101 module (bus master)
102 modules (bus master)
103 Serial cable (bus)
104 signal line 201 module (bus master)
R1 Resistance element R2 Resistance element R3 Resistance element R4 Resistance element Vdd Power supply potential

Claims (5)

In a bus sharing system consisting of multiple bus masters that exclusively share a bus,
The bus master is
An output circuit for outputting a high level or a low level indicating whether or not a bus is requested to be transmitted to a signal line connected to another bus master and to which a predetermined voltage is applied;
A potential difference measuring circuit for measuring a potential difference on the signal line side of the resistance element;
A bus sharing system comprising: a bus usage state determination circuit that determines a bus usage state based on the potential difference measured by the potential difference measurement circuit.   2. The bus sharing system according to claim 1, wherein among the respective resistance elements, a resistance value of one resistance element is different from a resistance value of another resistance element. The output circuit is composed of an open drain, and the potential difference measuring circuit is composed of an analog / digital converter.
2. The bus sharing system according to claim 1, wherein a pull-up resistance element is connected to the signal line. In a bus sharing system consisting of multiple bus masters that share a bus exclusively,
The bus master is
An open drain connected via a resistive element to a signal line connected to another bus master and connected to the pull-up resistive element;
An analog / digital converter connected to the signal line side of the resistance element and measuring a potential difference of the signal line;
A bus sharing system comprising: a bus use state determination circuit that determines a bus use state based on a potential difference measured by the analog / digital converter.   6. The bus sharing system according to claim 5, wherein a resistance value of one resistance element among the resistance elements is different from a resistance value of another resistance element.

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