JP2006099211A - Memory controller and nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To much more quickly provide the relocation processing technology of address management information in a nonvolatile storage device based on a relocation type address management method. <P>SOLUTION: The physical address of address management information AT is updated and recorded in a nonvolatile ROM 101. Thus, it is possible to more quickly update and record the address management information AT in a flash memory 104 than a conventional method for updating and recording the physical address of the address management information AT on the flash memory in terms of address management. The guaranteed frequency of the rewriting of the nonvolatile ROM is set so as to be sufficiently larger than the flash memory, (that is, about 10 billion times) so that the rewriting of the physical address of the address management AT on the nonvolatile RAM 101 can be prevented from being problematic in the guaranteed frequency of rewriting. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile memory device such as a semiconductor memory card, stores address management information for the flash memory in the flash memory, and reads a necessary part of the address management information to the volatile memory. The present invention relates to a memory controller and a nonvolatile storage device to be used. The present invention further includes a nonvolatile storage system having an external access device as a component and a memory control method describing the operation of the memory controller.

  A nonvolatile storage device having a flash memory writes and reads data by converting a logical address given to access the flash memory into a physical address. The nonvolatile storage device has address management information for address conversion. As described above, there is a non-volatile storage device that stores address management information in a flash memory and reads and uses only a necessary portion of the address management information in a volatile memory such as a random access memory (RAM). As such a non-volatile memory device, for example, a device described in Patent Document 1 is known.

  FIG. 7 shows an address map in the flash memory in the nonvolatile memory device described in Patent Document 1. The flash memory includes a management area 701 and a data area 702. The data area 702 is an area for storing so-called content information such as data read and written from an external access device, that is, music data and image data. The data area 702 is divided into four areas, for example, a data area # 0 to a data area # 3 every 1024 blocks. The management area 701 is an area for storing management information such as an address conversion table for determining a physical block address corresponding to a logical block address of data. The management area 701 includes an address conversion table LTPb 704 and an address conversion table index LTPa 703. LTPb 704 consists of # 0 to # 3 of LTPb 704 in order to manage # 0 to # 3 of data area 702, respectively.

  The number of entries managed by LTPb 704 # 0 to LTPb 704 # 3 matches the number of blocks. In each data area 702, basically, in order to convert a logical block address (0 to 1023 blocks) into a physical block address (0 to 1023 blocks), for each logical block number corresponding to each logical block address, that is, 1 A physical block number and an allocation flag are prepared for each word. The allocation flag is a flag for identifying whether valid data has already been allocated to the stored physical block number.

  The LTPa 703 has a physical block number in which LTPb 704 # 0 to LTPb 704 # 3 are stored and an allocation flag. LTPa 703 and LTPb 704 # 0 to LTPb 704 # 3 exist in an arbitrary block which is an erasing unit. For example, if the block is divided from page 1 to page N, page 1 (for example, 2 kbytes) is used. One address conversion table is configured. For example, LTPa 703 is associated with page 1 of the first block of management area 701, LTPb 704 # 0 is associated with page 1 of the next block, and pages other than page 1 of each block may be unused.

  A writing operation of the nonvolatile memory device configured as described above will be described. A data write destination area is determined in accordance with a logical address given from an external access device. For example, when a logical address 0 is designated from the external host, LTPb 704 # 0 corresponding to the data area 702 # 0 in the flash memory is read from the flash memory to a volatile memory such as a RAM based on the LTPa 703. Then, the allocation flag in one word corresponding to the logical block number in the read LTPb 704 # 0 is checked. If not allocated, the physical block in the data area 702 # 0 corresponding to the physical block number in one word is erased, and then data is written. Next, after allocating the allocation flag in this one word in the RAM to the allocated state, that is, the value 0, LTPb 704 # 0 is written back to the flash memory.

  On the other hand, the allocation flag in one word corresponding to the logical block number is checked. If the allocation flag has already been allocated, the physical block numbers corresponding to all areas of the logical block numbers 0 to 1023 are checked, and the physical block numbers that have not been allocated. Search (for example, physical block number 10). Then, data is written to the physical block of the data area 702 # 0 corresponding to the physical block number 10 after the erase process.

  Further, the physical block number 10 is written in the physical block number portion of one word of the logical block number 0 in the RAM. Further, the physical block number portion in one word in the logical block number in which the physical block number 10 was previously recorded is changed to the physical block number value previously stored in the physical block number portion in the logical block number 0. At the same time, the allocation flag is set to an unallocated state, that is, a value of 1. Then, LTPb 704 # 1 is written back to the flash memory.

  However, in the address management method of Patent Document 1 described above, LTPb 704 is allocated to a fixed area. Therefore, for example, when only one block in data area 702 # 0 is rewritten, LTP 704 # 0 is always allocated. It was necessary to rewrite the block. In other words, when 1024 blocks in the data area 702 # 0 are rewritten once each, the block to which the LTP 704 # 0 is allocated is rewritten 1024 times. Therefore, the average rewrite count is 1024 times in the management area 701 than in the data area 702. In other words, since rewriting concentrates on the management area 701, there is a problem that the life of the flash memory is shortened.

  As a method for solving this problem, as shown in Patent Document 2, a technique for allowing management information to be rearranged has been proposed. According to this technology, instead of assigning the management area to the fixed area, it is possible to reduce the number of rewrites of the management area to the same extent as the data area by sequentially changing the arrangement position of the management area, It is said that the lifetime of flash memory can be increased.

  Hereinafter, as disclosed in Patent Document 2, an address management method (hereinafter referred to as a rearrangement type address management method) in which the arrangement position of the management area is sequentially changed will be described with reference to FIGS. FIG. 4 is a conceptual diagram showing the configuration of an address management table (AT) and address translation table index information (ATI) in a conventional nonvolatile storage device based on the relocation address management method. FIG. 5 is an explanatory diagram showing a configuration of a conventional nonvolatile memory device and an address map of a flash memory in the nonvolatile memory device based on the relocation address management method. FIG. 6 is a flowchart showing an address management information update method based on the relocation address management method.

  Incidentally, the entry area and the management area in Patent Document 2 correspond to the ATI group and AT groups α and β in FIG. 4, respectively. In FIG. 4, an ATI group 401 and AT groups 402 and 403 are shown. For convenience, regarding the AT group, there are an AT group α 402 and an AT group β 403, and there are other AT groups other than those shown in the figure. The ATI group 401, the AT group α402, the AT group β403,... Are each composed of four physical blocks 404.

  In FIG. 5, the nonvolatile storage device includes a flash memory 508 and a memory controller 509. The memory controller 509 includes a host interface (host I / F) 501, a control unit 502, and a random access memory (RAM) 503. The host I / F 501 is an I / F for transmitting and receiving signals such as data and commands between the nonvolatile storage device and the access device. The control unit 502 controls the operation of the flash memory 508 and the nonvolatile storage device by a command from the access device. A RAM 503 is a volatile memory that temporarily stores data, address management information, and the like.

  The flash memory 508 has an ATI group area 504 and a data area 505. The ATI group area 504 is an area for storing the ATI group. The data area 505 is an area for storing data. Each data area includes a plurality of AT groups 506 and a plurality of data entries 507 corresponding thereto. The data entry 507 is a data entry managed by the current AT. In the flash memory 508, the physical block that is an erasure unit consists of two pages, and each page size is 2 kB.

  The ATI group area 504 is an area for storing an ATI group for managing the AT group in the data area 505 (# 0 to # 3). The ATI has a physical block number of each AT group, that is, an address indicating the physical block. If 64 AT groups are managed in each data area with one ATI, about 1 word (physical block number 10 bits) × 4 (number of data areas) × 64 (number of AT groups) = 512B, which is shown in FIG. As shown, eight ATIs can be recorded per block. ATIs are arranged four physical blocks from the top physical block of the flash memory 508, and form an ATI group 401.

  The data area 505 stores data read / written from / to an external access device, that is, so-called content information such as music data and image data, and also stores an AT group. The data area 505 is divided into four areas, that is, a data area # 0 to a data area # 3. Further, each area is divided into 1024 blocks. The AT group is stored in each data area in order to manage each data area. The unit managed by the AT, that is, the data entry 507 is one block. In each data area, in order to convert a logical block address (0 to 1023 block) into a physical block address (0 to 1023 block), a physical block is assigned to each logical block number (10 bits) corresponding to each logical block address. It has a number (10 bits) and an allocation flag (1 bit). Accordingly, the data capacity of one AT is 11 bits (physical block number 10 bits and allocation flag 1 bit) × 1024 blocks = about 2048 B, and one AT has one AT. The allocation flag is a flag for identifying whether valid data has already been allocated to each physical block.

  Next, the write operation will be described with reference to FIGS. The AT group α402 and AT group β403 in FIG. 4 are AT groups that manage the same data area. In the example shown in FIG. 4, the AT group α402 is managed by ATI # 4, and the AT group β403 is ATI. This area is managed by # 5. The AT and ATI updates are stored in the flash memory 508 so that the next AT and ATI flash memory 508 is not written to the same block as the current AT and current ATI. Further, the order of writing is determined in advance and stored in the flash memory 508 so that the ATI rewrite update does not occur every time the AT is updated, that is, in order to realize high-speed processing.

  Further, the process of detecting the latest ATI from the ATI group (S601 in FIG. 6) is performed at the time of initialization, for example, and is not performed for each data write command from the external access device to the nonvolatile memory device. A series of controls shown in FIG. 6 is executed by the control unit 502 shown in FIG. The control unit 502 may include a central processing unit (CPU).

  First, updating within an AT group managed by one ATI will be described. The memory controller 509 determines a data write destination area in accordance with a logical address given from an external access device. For example, when the logical address 0 is designated from the external access device, the memory controller 509 determines the current AT group corresponding to the data area # 0 in the flash memory 508. That is, in FIG. 4, it is determined from the current ATI which of the AT group α 402 and the AT group β 403 is the current AT group (S602 in FIG. 6).

  For example, AT # 2 is obtained from the current ATI in the read current AT group, read from the flash memory 508 to the RAM 503, and the physical block number in one word corresponding to the logical block number is checked (S603). If the physical block number is not registered in one word corresponding to the logical block number, that is, if it is not allocated, the unallocated physical block number is detected. Then, the physical block of the corresponding data area # 0 is erased, and the data is written to the flash memory 508. Next, the allocation flag corresponding to the physical block number in which the data is written is updated to the allocated state, that is, the value 0 (S604).

  Thereafter, AT # 3 is written in the flash memory in accordance with a predetermined writing order shown in FIG. 4 (S605, S607). On the other hand, the physical block number in one word corresponding to the logical block number is checked, and if it has already been allocated, a physical block number that has not been allocated is detected in the RAM 503. Then, the physical block of the corresponding data area # 0 in the flash memory 508 is erased and the data is written. In addition, the physical block number in which the data is written is written in the area corresponding to the physical block number in one word of the logical block number 0 in the RAM 503. Furthermore, the allocation flag corresponding to the physical block number is updated to the allocated state, that is, the value 0, and the allocation flag corresponding to the physical block number used in the previous logical block number 0 is set to the unallocated state, that is, the value 1. (S604). Thereafter, AT # 3 is written in the flash memory in accordance with a predetermined writing order shown in FIG. 4 (S605, S607).

  Next, a case where an ATI update occurs will be described. In FIG. 4, when the current AT is the final AT # 7 of the AT group α402 managed by ATI # 4, it is determined in S605 that the current AT is the final AT managed by the current ATI, and in S606, An empty block for writing the AT group is secured. An unallocated physical block number is detected from the allocation flag of AT # 7 of the AT group α402 which is the current AT in the RAM 503. Then, the physical block in the data area # 0 corresponding to the detected physical block number is erased to secure the area of the AT group β403.

  In the AT, in addition to the information created in the data write process S604, the allocation flag corresponding to the physical block number used to secure the area of the AT group α402 in the RAM 503 is updated to an unallocated state, and further, the AT group The allocation flag corresponding to the physical block number used for securing the area of β403 is updated to allocate. In S608, the latest AT is written to the AT # 0 area of AT group β403 in data area # 0. In step S609, the physical block address of each AT in the AT group β 403 is written in the ATI # 5 area.

  When the ATI group 401 is updated, it is necessary to secure a physical block for recording the ATI group in addition to the process for updating the ATI group. An unallocated physical block number is detected from the allocation flag of AT # 7 in the RAM 503, and the target physical block detected by the flash memory 508 is erased to secure an area for the next ATI group. In addition to the AT information at the time of ATI update, the allocation flag corresponding to the physical block number used to secure the area of the current ATI group in the RAM 508 is not allocated. Further, the allocation flag corresponding to the physical block number used for securing the area of the next ATI group 401 is updated to the allocated state. Thereafter, the AT and ATI are written into the flash memory 508 in the same manner as when updating the ATI.

As described above, ATs can be rearranged by ATI, that is, they are not assigned to fixed areas, so that ATs with high rewrite frequency do not concentrate on a specific physical block. Although ATI is allocated to a fixed area, it is an area having an address indicating AT, so that the rewriting frequency is relatively low.
JP 2001-142774 A JP-A-10-260908

  However, as described above, when all the AT group and ATI group are used, a process for securing a new AT group or ATI group area, that is, an erase process occurs. For this reason, although it is infrequent, processing speed will fall remarkably. When this is applied to an access device that records stream data such as a moving image, real-time recording may not be possible. Further, when the decrease in processing speed is relatively small, there is no problem until real-time recording cannot be performed. However, the access device is forced to mount a buffer RAM for compensating for a decrease in processing speed. In this case, the access device is forced to increase the cost.

  The present invention solves the above-mentioned conventional problems, and provides a non-volatile storage device that does not require area management of address management information in a relocation address management method, that is, does not cause a decrease in processing speed in area reservation. With the goal.

  In order to achieve this object, the nonvolatile memory device of the present invention comprises a nonvolatile memory, for example, a nonvolatile RAM, which has a sufficiently higher number of rewrites than the flash memory, and stores information indicating the storage location of the ATI, that is, the address management information AT. The data is stored and held in a non-volatile RAM having a sufficient number of guaranteed rewrites than the flash memory.

  Particularly, the invention according to claims 1 to 7 is a memory controller for writing and reading data to and from the nonvolatile main memory in accordance with a command and a logical address given from an external access device. The memory controller includes an address management table for managing data storage addresses and control means for performing data read / write control on the nonvolatile main memory, and address management for managing data storage addresses based on the address management table. And a nonvolatile auxiliary storage memory for storing the storage address of the address management table. The non-volatile auxiliary storage memory is a non-volatile memory that has a higher number of guaranteed rewrites than the non-volatile main memory, and the storage address of the address management table is not fixed by appropriately updating the storage address of the address management table. It is characterized by. With this configuration, by appropriately rewriting the storage address of the address management table in the nonvolatile auxiliary storage memory, the address management table on the nonvolatile main storage memory such as a flash memory is always rewritten on the same physical address. Can be avoided. Since the nonvolatile auxiliary storage memory is a nonvolatile memory having a larger number of guaranteed rewrites than the nonvolatile main storage memory, for the frequent rewrite of the storage address in the address management table in the nonvolatile auxiliary storage memory, There is no particular problem.

  The inventions according to claims 8 to 14 of the present invention include a nonvolatile main memory and a memory controller, and the nonvolatile main memory according to a command and a logical address given from an external access device. This is a non-volatile storage device that writes data to and reads data from the storage device. The nonvolatile main storage memory is composed of a plurality of physical blocks each including at least one sector, and the memory controller stores an address management table for managing the data storage address and the data storage for the nonvolatile main storage memory. Control means for performing read / write control, address management means for managing the storage address of the data based on the address management table, and a nonvolatile auxiliary storage memory for storing the storage address of the address management table. The non-volatile auxiliary storage memory is a non-volatile memory that has a higher number of guaranteed rewrites than the non-volatile main storage memory, and the storage address of the address management table is not fixed by appropriately updating the storage address of the address management table. It is characterized by doing so. With this configuration, by appropriately rewriting the storage address of the address management table in the nonvolatile auxiliary storage memory, the address management table on the nonvolatile main storage memory such as a flash memory is always rewritten on the same physical address. Can be avoided. Since the nonvolatile auxiliary storage memory is a nonvolatile memory having a larger number of guaranteed rewrites than the nonvolatile main storage memory, for the frequent rewrite of the storage address in the address management table in the nonvolatile auxiliary storage memory, There is no particular problem.

  The inventions according to claims 15 to 21 of the present invention include an access device, a nonvolatile main memory, and a memory controller, and the nonvolatile main memory according to a command and a logical address given from the access device. A non-volatile storage system that writes data to and reads data from a storage memory. The nonvolatile main storage memory is composed of a plurality of physical blocks each including at least one sector, and the memory controller stores an address management table for managing the data storage address and the data storage for the nonvolatile main storage memory. Control means for performing read / write control, address management means for managing the storage address of the data based on the address management table, and a nonvolatile auxiliary storage memory for storing the storage address of the address management table. The non-volatile auxiliary storage memory is a non-volatile memory that has a higher guaranteed number of rewrites than the non-volatile main storage memory, and the storage address of the address management table is not fixed by appropriately updating the storage address of the address management table. It is characterized by doing so. With this configuration, by appropriately rewriting the storage address of the address management table in the nonvolatile auxiliary storage memory, the address management table on the nonvolatile main storage memory such as a flash memory is always rewritten on the same physical address. Can be avoided. The non-volatile auxiliary memory is a non-volatile memory that has a higher guaranteed number of rewrites than the non-volatile main memory, so the rewrite of the storage address of the address management table in the non-volatile auxiliary memory is frequently performed. No particular problem arises.

  Further, the invention according to claims 22 to 28 of the present invention is a memory control method for writing and reading data to and from a nonvolatile main memory according to a command and a logical address given from the outside. This memory control method performs an address management table for managing a data storage address and a data read / write control with respect to a nonvolatile main storage memory, manages a data storage address based on the address management table, and manages an address. The storage address of the table is stored in the nonvolatile auxiliary storage means. The non-volatile auxiliary storage memory is a non-volatile memory that has a higher number of guaranteed rewrites than the non-volatile main storage means, and the storage address of the address management table is fixed by appropriately updating the storage address of the address management table. It is characterized by not being done. By this processing, the address management table on the nonvolatile main memory such as a flash memory is always rewritten on the same physical address by appropriately rewriting the storage address of the address management table in the nonvolatile auxiliary storage memory. Can be avoided. The non-volatile auxiliary storage memory is a non-volatile storage means having a higher guaranteed number of rewrites than the non-volatile main storage memory. Therefore, the rewrite of the storage address of the address management table in the non-volatile auxiliary storage memory is frequently performed. There is no particular problem.

  As a result, the address management information AT can be rearranged by sequentially updating the ATI on the non-volatile RAM, so that it is possible to avoid a decrease in the processing speed for securing the AT group and the area of the ATI group. The number of rewrites of the ATI is larger than the number of rewrites of the address management information AT and data. However, since the nonvolatile RAM has a sufficiently large number of rewrite guarantees of the flash memory, it does not affect the life of the nonvolatile storage device.

  A nonvolatile memory device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing the configuration of the nonvolatile memory device according to this embodiment and its address map. The nonvolatile storage device includes a flash memory 104 and a memory controller 108. The memory controller 108 includes a host I / F 501, a control unit 102, a nonvolatile RAM 101, and a RAM 103. The flash memory 104 is divided into a plurality of data areas.

  A nonvolatile RAM 101 in the memory controller 108 is a nonvolatile RAM that stores an AT pointer that is a physical address of the address management information AT. The control unit 102 controls the operation of the nonvolatile storage device including the flash memory 104 by a command from the access device. A RAM 103 is a volatile memory that temporarily stores data, address management information, and the like, and includes a random access memory. The control unit 102 and the RAM 103 have a function of an address management unit that manages a data storage address based on an address management table described later.

  The data area of the flash memory 104 is divided into a number of physical blocks. In this example, the physical block 105 stores the old AT. The physical block 106 stores the current AT, which is the current AT. The physical block 107 is a data entry managed by the current AT. In the flash memory 104, a physical block as an erasure unit is composed of two pages, and each page size is 2 kB. Other blocks are the same as those of the conventional nonvolatile memory device shown in FIG.

  FIG. 2 is a memory map showing the storage format of the nonvolatile RAM 101. In FIG. 2, the upper bytes, that is, 4 bytes from Byte 0 are areas that hold the physical addresses of ATs that manage the data area # 0 shown in FIG. The following Byte is an area for holding the physical address of the AT that manages the data areas # 1 to # 3. For example, the area that holds the physical address of the AT that manages the data area # 0 is composed of two areas of the AT pointer # 0_0 and the AT pointer # 0_1, and the current AT is stored in either area. Information indicating the current AT, that is, the current AT identification flag is stored in the bits indicated by the thick frame in FIG. For each pointer in which the AT pointer to which the value 1 is assigned holds the physical address of the current AT, an area for 10 bits holding the AT physical address value is provided. For example, in the case of AT pointer # 0_0, the physical address of the AT is stored with b1 on the Byte1 side as MSB and b0 on the Byte0 side as LSB.

  FIG. 3 is a flowchart showing the address management information update method according to this embodiment. The operation of the nonvolatile memory device according to this embodiment will be described with reference to FIGS. The basic operation is the same as that of the conventional nonvolatile memory device shown in FIG. The difference is a method of rearranging the address management information AT, that is, a method of determining a physical address of the address management information AT. The present embodiment is characterized in that the address management information AT is rearranged by updating the AT pointer on the nonvolatile RAM 101.

不揮発性ＲＡＭ１０１は、表１に示すように、フラッシュメモリと比較すると、書き換え保証回数が１００億回と非常に多い。このため不揮発性ＲＡＭ１０１上でのＡＴポインタの更新、即ち書き換えによる寿命は特に考慮する必要が無くなる。またバイトあたりの書き込みサイクルも１００ｎｓと比較的高速に行えるので、図２に示したＡＴポインタの２バイトは２００ｎｓで実行できる。従来のようなフラッシュメモリ上でのＡＴＩの更新と比較して、より高速にアドレス管理情報ＡＴの再配置処理が行える。さて、図３を用いて、アクセス装置から書き込み要求があった場合の処理について説明する。

As shown in Table 1, the non-volatile RAM 101 has a very large number of guaranteed rewrites of 10 billion compared with the flash memory. For this reason, it is not necessary to particularly consider the lifetime due to the update of the AT pointer on the nonvolatile RAM 101, that is, the rewriting. Further, since the write cycle per byte can be performed at a relatively high speed of 100 ns, two bytes of the AT pointer shown in FIG. 2 can be executed in 200 ns. Compared with the conventional ATI update on the flash memory, the address management information AT can be relocated at a higher speed. Now, the processing when there is a write request from the access device will be described with reference to FIG.

  First, when data is written to the flash memory 104 for the first time, the nonvolatile RAM 101 stores 0th of AT pointers corresponding to each data area, that is, AT pointer # 0_0, AT pointer # 1_0, AT pointer # 2_0. It is assumed that the value 1 is set as the current AT identification flag (thick framed bit) in the AT pointer # 3_0 and the physical block number 0 is set as the pointer value. However, the physical block with physical block number 0 is not a bad block. After this state, the data write destination area is determined according to the logical address given from the access device (S301 in FIG. 3).

  For example, when the logical address 0 is designated from the external access device, the physical block number 0 of the data area # 0 in the flash memory 104 is designated as the current AT, and the current AT is read from the flash memory 104 to the RAM 103 (S302). ). Also, the physical block number in one word corresponding to the logical block number is checked. If the physical block number is not registered in one word corresponding to the logical block number, that is, if it is not allocated, the unallocated physical block number is detected, the physical block is erased, and the data is flash memory 104 is written. Next, the allocation flag corresponding to the physical block number in which the data is written is updated to the allocated state, that is, the value 0 (S303).

  Thereafter, based on the AT on the RAM 103, the unallocated physical block number is detected (for example, physical block number 5), the physical block is erased, and the physical block is updated to the allocated state, that is, the value 0. The AT of the RAM 103 is written back to the flash memory 104 (S304). Since the physical block number 5 is the current AT, the physical block number 5 is written as a pointer value to the AT pointer # 0_1 of the nonvolatile RAM 101, and the value 1 is written to the current AT identification flag (thick framed bit). Further, since the AT pointer # 0_0 becomes the old AT, the value 0 is written in the current AT identification flag (thick framed bit). The storage state of the nonvolatile RAM 101 when the above processing is completed is as shown in FIG.

  Next, when there is a write request from the access device, based on the current AT stored at the address of the physical block number 5 as shown in FIG. 1, the shaded physical block, that is, the physical block of the physical block number 4092 Write data to.

  Although a method of storing the AT itself in the nonvolatile RAM is also conceivable, since the AT has a relatively large capacity of 2 kB as in the present embodiment, a nonvolatile RAM having a larger capacity than the nonvolatile RAM 101 is provided. There is a need, which is a cost disadvantage. Since the capacity of the address management information AT increases as the capacity of the flash memory increases, the above demerits become more remarkable.

  Further, in order to rationalize the size of the address management information AT as in this embodiment, the address space of the entire flash memory is divided into data areas # 0 to # 3 and each has the address management information AT independently. When the logical address accessed from the access device is frequently accessed across the data areas # 0 to # 3, it is necessary to load the address management information AT from the flash memory to the nonvolatile RAM for each access. There is.

  In the conventional nonvolatile memory device as shown in FIG. 4, the address management information AT is loaded from the flash memory to the volatile RAM, and the volatile RAM has a write cycle on the order of 10 nSec. It was able to load relatively fast. Since the nonvolatile RAM has a write cycle on the order of 100 nSec, for example, 200 μSec (2 kB × 100 nSec) is required to load the address management information AT for 2 kB. This is a time close to the write cycle time of the flash memory, and it is an order that cannot be ignored as a reduction in processing speed.

  The flash memory 104 may not be divided into the data area # 0 to the data area # 3. Further, the nonvolatile RAM 101 may not be built in the memory controller 108 but may be outside the memory controller 108. Further, the nonvolatile RAM 101 may be a ferroelectric memory (FeRAM), a magnetic recording type arbitrary writing / reading memory (MRAM), an ovonic unified memory (OUM), or a resistance RAM (RRAM).

  The nonvolatile storage device of the present invention is a device that stores address management information for the flash memory in the flash memory itself, and reads and uses a necessary part of the address management information in the volatile memory. Wear leveling can be realized without impairing processability. INDUSTRIAL APPLICABILITY The present invention is particularly useful as a storage device for devices that require real-time properties, such as a system that records and reproduces stream data such as moving images.

It is explanatory drawing which shows the structure and address map of a non-volatile memory device by embodiment of this invention. 4 is a memory map of a nonvolatile RAM according to the present embodiment. It is a flowchart which shows operation | movement of the address management method by this Embodiment. It is a conceptual diagram which shows the conventional address management method. It is explanatory drawing which shows the structure and address map of the conventional non-volatile memory device. It is a flowchart which shows operation | movement of the conventional address management method. It is explanatory drawing which shows the address map of the conventional non-volatile memory device.

Explanation of symbols

101 Nonvolatile RAM
102, 502 Control unit 103, 503 RAM
104, 508 Flash memory 105, 106, 404 Physical block 107 Data entry 401 ATI group 402 AT group α
403 AT group β
501 Host interface (Host I / F)
504 ATI group area 505 Data area

Claims (28)

A memory controller that writes data to and reads data from a nonvolatile main memory in accordance with a command and a logical address given from an external access device,
An address management table for managing data storage addresses and control means for performing data read / write control with respect to the nonvolatile main memory;
Address management means for managing data storage addresses based on the address management table;
A non-volatile auxiliary storage memory for storing a storage address of the address management table;
The non-volatile auxiliary storage memory is a non-volatile memory having a higher number of rewrite guarantees than the non-volatile main storage memory, and the storage address of the address management table is updated by appropriately updating the storage address of the address management table. A memory controller characterized in that the memory controller is not fixed.   2. The memory controller according to claim 1, wherein the nonvolatile auxiliary storage memory has a writing speed in units of at least one bit to several bytes faster than the main storage nonvolatile memory.   3. The memory controller according to claim 1, wherein the nonvolatile auxiliary storage memory is a nonvolatile RAM.   4. The memory controller according to claim 3, wherein the nonvolatile auxiliary memory is a ferroelectric memory (FeRAM).   4. The memory controller according to claim 3, wherein the non-volatile auxiliary storage memory is a magnetic recording type arbitrary write / read memory (MRAM).   4. The memory controller according to claim 3, wherein the non-volatile auxiliary storage memory is an ovonic unified memory (OUM).   4. The memory controller according to claim 3, wherein the nonvolatile auxiliary storage memory is a resistance RAM (RRAM). A non-volatile storage device having a non-volatile main memory and a memory controller, and writing and reading data to and from the non-volatile main memory according to a command and a logical address given from an external access device ,
The nonvolatile main memory is
A plurality of physical blocks including at least one sector;
The memory controller is
An address management table that manages data storage addresses and control means for performing data read / write control for the nonvolatile main memory, and address management means for managing data storage addresses based on the address management table; A non-volatile auxiliary storage memory for storing a storage address of the address management table,
The non-volatile auxiliary storage memory is a non-volatile memory having a larger number of guaranteed rewrites than the non-volatile main storage memory, and the storage address of the address management table is updated by appropriately updating the storage address of the address management table. A non-volatile storage device characterized in that it is not fixed.   9. The nonvolatile storage device according to claim 8, wherein the nonvolatile auxiliary storage memory has a writing speed in units of at least 1 bit to several bytes faster than the main storage nonvolatile memory.   10. The nonvolatile storage device according to claim 8, wherein the nonvolatile auxiliary storage memory is a nonvolatile RAM.   The nonvolatile storage device according to claim 10, wherein the nonvolatile auxiliary storage memory is a ferroelectric memory (FeRAM).   11. The nonvolatile storage device according to claim 10, wherein the nonvolatile auxiliary storage memory is a magnetic recording type arbitrary write / read memory (MRAM).   The nonvolatile storage device according to claim 10, wherein the nonvolatile auxiliary storage memory is an ovonic unified memory (OUM).   The nonvolatile storage device according to claim 10, wherein the nonvolatile auxiliary storage memory is a resistance RAM (RRAM). Non-volatile memory having an access device, a non-volatile main memory, and a memory controller, and writing and reading data to and from the non-volatile main memory according to a command and a logical address given from the access device A system,
The nonvolatile main memory is
A plurality of physical blocks including at least one sector;
The memory controller is
An address management table that manages data storage addresses and control means for performing data read / write control for the nonvolatile main memory, and address management means for managing data storage addresses based on the address management table; A non-volatile auxiliary storage memory for storing a storage address of the address management table,
The non-volatile auxiliary storage memory is a non-volatile memory having a larger number of guaranteed rewrites than the non-volatile main storage memory, and the storage address of the address management table is updated by appropriately updating the storage address of the address management table. A non-volatile storage system characterized in that the memory is not fixed.   16. The nonvolatile storage system according to claim 15, wherein the nonvolatile auxiliary storage memory has a writing speed in units of at least 1 bit to several bytes faster than the nonvolatile memory for main storage.   17. The nonvolatile storage system according to claim 15 or 16, wherein the nonvolatile auxiliary storage memory is a nonvolatile RAM.   17. The nonvolatile memory system according to claim 16, wherein the nonvolatile auxiliary memory is a ferroelectric memory (FeRAM).   17. The nonvolatile storage system according to claim 16, wherein the nonvolatile auxiliary storage memory is a magnetic recording type arbitrary write / read memory (MRAM).   The non-volatile storage system according to claim 16, wherein the non-volatile auxiliary storage memory is an ovonic unified memory (OUM).   The nonvolatile storage system according to claim 16, wherein the nonvolatile auxiliary storage memory is a resistance RAM (RRAM). A memory control method for writing data to and reading data from a nonvolatile main memory according to a command and a logical address given from the outside,
An address management table for managing data storage addresses and data read / write control with respect to the nonvolatile main storage memory, management of data storage addresses based on the address management table, and storage of the address management table Store the address in non-volatile auxiliary storage memory,
The non-volatile auxiliary storage memory is a non-volatile memory having a larger number of guaranteed rewrites than the non-volatile main storage memory, and the storage address of the address management table is updated by appropriately updating the storage address of the address management table. A memory control method characterized in that the memory is not fixed.   23. The memory control method according to claim 22, wherein a writing speed in units of at least one bit to several bytes in the non-volatile auxiliary memory is faster than that of the main memory non-volatile memory.   24. The memory control method according to claim 22, wherein a nonvolatile RAM is used as the nonvolatile auxiliary storage memory.   The memory control method according to claim 24, wherein a ferroelectric memory (FeRAM) is used as the nonvolatile auxiliary storage memory.   25. The memory control method according to claim 24, wherein a magnetic recording type arbitrary write / read memory (MRAM) is used as the nonvolatile auxiliary storage memory.   The memory control method according to claim 24, wherein an ovonic unified memory (OUM) is used as the nonvolatile auxiliary storage memory.   25. The memory control method according to claim 24, wherein a resistance RAM (RRAM) is used as the nonvolatile auxiliary storage memory.

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