JP2006094242A - Variable delay type oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable delay type oscillator with stable operation while an influence of noises at the start of oscillation is restricted. <P>SOLUTION: The variable delay type oscillator is composed of an oscillation loop, which includes an SAW element and a variable phase circuit for changing the phase based on an input signal, and an output driving circuit for driving an outer circuit by using one contact of the oscillation loop as an output. A hysteresis comparator is used as the output driving circuit, or a power-supply voltage is monitored by an operation control circuit and a voltage, which enables the operation, is fed to the output driving circuit if the power-supply voltage becomes a previously set level or more. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a variable delay oscillator using, for example, a surface acoustic wave (SAW) element as a delay element.

  Optical communication is being rapidly developed because it can transmit data in a wide band, and an optical communication apparatus used for this is generally configured as shown in FIG. That is, in the optical communication apparatus 1, parallel data from a signal processing circuit (not shown) is converted into serial data by the parallel / serial conversion unit 11, and this data is sent to the optical diode 13 via the drive circuit 12, where the optical signal is transmitted. And transmitted through the transmission line 14. The transmission speed of optical data is about to be increased in the future, for example, 10 Gbps. In this case, the clock signal supplied to the parallel / serial conversion unit 11 is required to have a considerably high frequency, for example, about 600 MHz. On the other hand, if the clock signal contains jitter (fluctuation), depending on the degree, the waveform of the optical pulse may collapse and read errors may occur. Therefore, the allowable amount of jitter contained in the clock signal is specified. Yes.

  For this reason, a jitter filter 15 composed of a PLL (phase locked loop) circuit is provided in the clock signal path. A variable delay type oscillator that is a voltage controlled oscillator is incorporated in the PLL circuit, but when the frequency of the clock signal to be processed becomes high, for example, about 600 MHz, the thickness of the crystal element when the delay element is used becomes the thickness. It is advantageous to use a surface acoustic wave (SAW) element because it is very thin and difficult to process. Since the SAW element relies on a surface wave, the Q value is inferior to that of a quartz crystal resonator. However, since the resonance frequency can be adjusted by adjusting the arrangement of the electrode patterns on the surface, it is considered to be suitable for such a use. FIG. 9 shows a variable delay oscillator using a SAW element widely used in high-speed communication apparatuses such as an optical communication apparatus. The output drive circuit 18 is connected to one point of an oscillation loop including the SAW element 16 and the variable phase circuit 17. The output which becomes a clock pulse is taken out at 1 and a load (not shown) is driven. A DC voltage signal is input from the input terminal, and the phase of the frequency signal that circulates the oscillation loop according to the voltage level is shifted by the variable phase circuit 17 to oscillate at a predetermined frequency, and a rectangular wave signal having the oscillation frequency is output. It is output from the drive circuit 18.

  On the other hand, in order to convert the sine wave pulse input from the oscillation loop into a rectangular wave pulse, the output drive circuit 18 is composed of a wideband high gain amplifier circuit, for example, when a 600 MHz sine wave pulse is rotating in the oscillation loop. For example, it is required to have a high gain up to about 2 GHz. The reason is that since a harmonic wave is included in the sine wave pulse, it must be processed at a high speed in order to obtain a rectangular wave pulse. Further, in order for the clock pulse from the variable delay oscillator to be transmitted by the optical communication apparatus as described above, the output drive circuit 18 is required to drive a low impedance, for example, ECL (emitter coupled logic circuit), PECL. In the case of (pseud emitter coupled logic circuit), it is necessary to obtain an output current of about 140 mA in order to drive a load of 50Ω.

  At the time of starting the oscillation immediately after the power supply of the variable delay oscillator is turned on, before the frequency signal that goes around the oscillation loop in the middle of the rise of the power supply voltage is stabilized, the output drive circuit 18 passes through the parasitic capacitance or the power supply GND line. The wraparound noise is input to the output side 10 of the SAW element 16, and when such noise is generated, it is input to the output drive circuit 18. The output drive circuit 18 is, for example, about 2 GHz as described above. Since a gain as high as 40 dB can be obtained, noise is greatly amplified here.

  By the way, when the variable delay oscillator is made into one chip, its chip size is increasingly reduced, and it is going to be mounted in a very small package of about 5 mm × 7 mm or less, for example. For this reason, each component circuit of the variable delay type oscillator is placed close to each other. However, as described above, when the oscillation frequency becomes considerably high, noise due to the noise is caused through the parasitic capacitance or the power line or ground. As a result, the output drive circuit 18 has a large gain through the line, and the output drive circuit 18 has a large gain. As a result, the oscillation loop is different from the original oscillation loop (the regular loop 100 shown in FIG. 9). (Attached loop 200 shown in FIG. 9) is formed, abnormal oscillation may occur, and a predetermined clock signal may not be supplied to the load.

  Patent Document 1 exists as a prior art document suggesting that a SAW element is used as a delay element of a variable delay type oscillator. However, the above-mentioned problems are not noted here.

JP 2000-196358 A

  The present invention has been made under such circumstances, and an object of the present invention is to provide a variable delay type oscillator capable of suppressing the influence of noise at the time of oscillation start and obtaining stable operation.

  The present invention includes an oscillation loop that includes a delay element and a variable phase circuit that changes a phase based on an input signal, and an output drive circuit that drives an external circuit by extracting a frequency signal from one contact of the oscillation loop. One example of the variable delay oscillator includes a noise suppression unit that suppresses generation of noise from the output drive circuit when oscillation starts. In another aspect, the output drive circuit may be constituted by a hysteresis comparator. As yet another aspect, the power supply voltage of the variable delay oscillator is monitored, and when the power supply voltage is lower than a preset setting voltage, the output drive circuit is disabled, and the power supply voltage is set in advance. In the above case, a configuration including an operation control circuit for enabling the output drive circuit can be given.

  According to the present invention, since the noise suppression means for suppressing the generation of noise from the output drive circuit at the time of oscillation start-up is provided, noise from the output side of the output drive circuit is It is possible to suppress the sneaking to the input side or entering the oscillation loop, and thus a stable operation can be obtained for the variable delay oscillator.

  According to another invention, since the output drive circuit is configured by a hysteresis comparator, even if noise generated at the time of oscillation start is input to the output drive circuit, the degree of disturbance of the signal, which is the input noise, is determined by the hysteresis comparator. Since it is mitigated by the action, it is possible to suppress the entry into the input side of the output drive circuit and the entry into the oscillation loop. According to still another aspect of the invention, when the power supply voltage of the variable delay oscillator is lower than a preset set voltage, the output drive circuit is disabled so that generation of noise from the output side of the output drive circuit is suppressed. It is done. Therefore, in these inventions, a stable operation can be obtained for the variable delay oscillator. As a result, for example, if this variable delay oscillator is used for a jitter filter of an optical communication apparatus, the communication operation is stabilized.

  FIG. 1 is a circuit diagram showing a variable delay oscillator according to a first embodiment of the present invention. A SAW element 2 is a delay element, and a pair of comb-like electrodes are provided on the surface of the piezoelectric body on the input side and the output side, respectively. 21 and 22 are input-side electrodes, and 23 and 24 are output-side electrodes. When a voltage is applied between the input-side electrode pairs 21 and 22, the surface of the piezoelectric body is distorted corresponding to the voltage. The distorted wave propagates to the output electrode pair 23 and 24 to generate a voltage between the electrode pair 23 and 24, and the frequency signal corresponding to the input frequency signal is delayed and output. Become.

  The electrodes 23 and 24 on the output side of the SAW element 2 are connected to the input side of the amplifier 31 at the front stage, and the variable phase circuit 32 and the amplifier 33 at the rear stage are connected to the output side of the amplifier 31 in this order. . The output side of the amplifier 33 at the subsequent stage is connected to the electrodes 21 and 22 on the input side of the SAW element 2, and an oscillation loop is formed by the SAW element 2, the amplifier 31, the variable phase circuit 32, and the amplifier 33.

  The variable phase circuit 32 includes a frequency control terminal 30 and has a function of shifting and outputting the phase of the frequency signal on the input side according to the magnitude of the DC voltage supplied to the frequency control terminal 30. As will be described later, the variable delay oscillator of this example is incorporated in, for example, a PLL circuit. In this case, a DC voltage that is an output signal from a low-frequency pass filter of the PLL circuit is supplied from the frequency control terminal 30 to the variable phase circuit 32. Will be.

  Reference numeral 4 denotes an output driving circuit for taking out a frequency signal from one contact of the oscillation loop and driving an external circuit. In this example, the output driving circuit 4 is provided between the amplifier 31 and the variable phase circuit 32 in the previous stage. And a hysteresis comparator having its input terminal connected to the signal path. The hysteresis comparator has the input / output characteristics shown in FIG. 2. The operating voltage at the time of rising of the output is V2, and the operating voltage at the time of falling of the output is V1. Therefore, the output is at the “low” level until the input voltage reaches V2, and even if the output drops from V2, the “high” level is maintained until V1. In order to facilitate understanding of the operation of this embodiment, the operating point when a normal comparator is used is indicated as V0, and the operation is indicated by a dotted line. This hysteresis comparator has a gain of 40 dB or more up to 2 GHz for an oscillation loop frequency of 600 MHz, for example.

  Next, the operation of this embodiment will be described. Now, assuming that a device incorporating a variable delay oscillator is turned on, the frequency signal does not rise immediately and stably at the start of oscillation in the oscillation loop, and there is a probability that random noise will occur before the rise. high. FIG. 3 schematically shows the noise, and the vertical axis indicates the input voltage of the output drive circuit 4 corresponding to the noise level. In FIG. 3, V1 and V2 are the aforementioned threshold voltages in the hysteresis comparator that constitutes the output drive circuit 4, respectively. If the noise level is smaller than the threshold value, or if the threshold value is designed to be larger than the noise level, the output of the hysteresis comparator is fixed at the “H” or “L” level. Even if the noise level exceeds the threshold value, as shown in FIG. 4A, the degree of disturbance of the signal, which is the input noise, is mitigated by the action of the hysteresis comparator. On the other hand, when a normal comparator is used as the output drive circuit 4, since the rising and falling operating points are both V0, the frequency corresponding to noise is high and disturbed as shown in FIG. A pulse will be generated.

  As described above, since a pulse with a small degree of disturbance is output from the output driving circuit 4 at the time of oscillation start-up, even if the variable delay type oscillator is made into one chip and the chip size is small, the output driving circuit 4 It is possible to suppress the pulse from entering the input side or the oscillation loop, and there is no possibility of abnormal oscillation, and the oscillation operation starts. In both normal oscillation and abnormal oscillation, it is necessary to satisfy predetermined gain and phase conditions in the oscillation loop. These conditions are not established immediately after the power is turned on, and the power supply voltage increases with a certain time constant. At the same time, oscillation grows when the circuit starts operating and approaches the oscillation condition. For this reason, even if the power supply of each part including the hysteresis comparator is common, the response of the hysteresis comparator is faster before the oscillation condition is satisfied by the normal design.

  If this variable delay oscillator is incorporated in, for example, a PLL circuit, a DC voltage is supplied to the variable phase circuit 32 via a frequency control terminal 40 from a low-frequency pass filter (not shown) in the previous stage, and the DC voltage The phase of the frequency signal input to the variable phase circuit 32 is shifted according to the level, thereby adjusting the frequency of the frequency signal that goes around the oscillation loop, and oscillates at a frequency of 600 MHz, for example. This frequency signal is a sine wave, but is converted into a rectangular wave pulse signal by a hysteresis comparator (output drive circuit 4) and output to a load which is an external circuit. Since the hysteresis comparator has a large gain and outputs a pulse with a large amplitude, the pulse can be transmitted to a load connected to a subsequent stage, for example, an optical communication cable, that is, the load can be driven.

  As described above, according to the first embodiment, since the hysteresis comparator is used as the output drive circuit 4, even if noise is generated in the oscillation loop at the time of oscillation start, the pulse output from the output drive circuit 4 The degree of disturbance is small. Since this output drive circuit 4 has a high gain up to a high frequency, and if the output is random noise, it is easy to turn to the input side. Therefore, this embodiment is extremely effective as a technique for suppressing noise wraparound. is there. As a result, abnormal oscillation is suppressed, that is, a situation where the oscillation condition of the associated loop 200 shown in FIG. 5 is satisfied first and the oscillation of the regular loop 100 is prevented can be avoided, and the operation of the variable delay oscillator is stable. To do.

  Next, a second embodiment of the variable delay oscillator according to the present invention will be described with reference to FIGS. Reference numeral 5 in FIG. 6 denotes an operation control circuit provided on the power supply line 50 for supplying a power supply voltage to the power supply terminal of the output drive circuit 4 made of, for example, a comparator. The operation control circuit 5 includes a voltage dividing resistors 51 and 52 that divide a power supply voltage from a power source, and a positive input terminal connected to a connection point between the voltage dividing resistors 51 and 52 and a negative input terminal, for example. And a comparator 53 grounded via a power supply for the set voltage. The comparator 53 has a function of outputting a high level voltage to the power supply terminal of the output drive circuit 4 when the input voltage exceeds the preset voltage VR until the input voltage exceeds the preset voltage VR. Have

  The low level of the output voltage of the comparator 53 is a voltage at which the output drive circuit 4 becomes inoperable (may be zero), and the high level voltage is a voltage at which the output drive circuit 4 can operate, for example, Power supply voltage. The role of the operation control circuit 5 is to monitor the power supply voltage and to operate the output drive circuit 4 after the power supply voltage rises to a certain level, that is, after the oscillation loop rises to a voltage level that stabilizes the oscillation loop to some extent. A voltage, for example, a power supply voltage is to be supplied, and the set voltage is determined from this viewpoint.

  In the second embodiment, as shown in FIG. 7A, when the power supply of the variable delay oscillator is turned on, the power supply voltage rises. However, until the power supply voltage reaches the set voltage VS, the comparator 53 is positive. Since the input voltage on the side is smaller than the input voltage on the negative side, the output voltage is at a low level as shown in FIG. At this time, even if noise is generated in the oscillation loop, the output drive circuit 4 is in an inoperable state, so that the noise is not amplified and output, so that abnormal oscillation does not occur.

  When the power supply voltage rises and exceeds the set voltage VS, the positive input voltage of the comparator 53 becomes larger than the negative input voltage, so that the output voltage becomes a high level, for example, the level of the power supply voltage. 4 is supplied to the power supply terminal 4, and the output drive circuit 4 becomes operable. At this stage, the oscillation of the oscillation loop has settled to some extent and there is almost no noise, so that no abnormal oscillation occurs even if the output drive circuit 4 is operating. Therefore, abnormal oscillation can be suppressed also in the second embodiment, and a stable operation can be obtained for the variable delay oscillator.

  As described above, the embodiment of the present invention has been described. However, in the present invention, noise generated in an oscillation loop at the time of oscillation start-up is input to the output drive circuit 4, and as a result, the noise generated from the output drive circuit 4 is caused. Thus, the operation does not become unstable. In short, it may be configured to include a noise suppression means for suppressing generation of noise from the output drive circuit at the time of starting oscillation. In the above example, the noise suppressing means corresponds to the hysteresis comparator, the operation control circuit 5 and the like.

1 is a circuit diagram showing an embodiment of a variable delay oscillator according to the present invention. It is a characteristic view which shows the input-output characteristic of the hysteresis comparator used for said embodiment. It is a voltage waveform diagram which shows the noise at the time of the oscillation starting input into the output drive circuit used for said embodiment. It is a voltage waveform diagram showing an output signal at the time of oscillation start in the output drive circuit. It is a circuit diagram which shows the regular oscillation loop and incidental oscillation loop in the circuit of said embodiment. It is a circuit diagram which shows other embodiment of the variable delay type | mold oscillator based on this invention. It is a characteristic view which shows the operation | movement of the operation control circuit used for said other embodiment. It is a block diagram which shows the general structural example of an optical communication apparatus. It is a circuit diagram which shows the prior art example of a variable delay type | mold oscillator.

Explanation of symbols

2 SAW elements 21 to 24 Electrodes 31 and 33 Amplifier 32 Variable phase circuit 4 Output drive circuit composed of hysteresis comparator 40 Output drive circuit 5 Operation control circuit 53 Comparator 6 Optical communication device 7 Jitter filter 73 composed of PLL circuit Variable delay of the present invention Type oscillator

Claims (3)

A variable delay type including an oscillation loop including a delay element and a variable phase circuit that changes a phase based on an input signal, and an output driving circuit for driving an external circuit by extracting a frequency signal from one contact of the oscillation loop In the oscillator,
A variable delay oscillator comprising noise suppression means for suppressing generation of noise from the output drive circuit when oscillation starts. A variable delay type including an oscillation loop including a delay element and a variable phase circuit that changes a phase based on an input signal, and an output driving circuit for driving an external circuit by extracting a frequency signal from one contact of the oscillation loop In the oscillator,
A variable delay oscillator characterized in that the output drive circuit comprises a hysteresis comparator. A variable delay type including an oscillation loop including a delay element and a variable phase circuit that changes a phase based on an input signal, and an output driving circuit for driving an external circuit by extracting a frequency signal from one contact of the oscillation loop In the oscillator,
The power supply voltage of the variable delay oscillator is monitored, and when the power supply voltage is lower than a preset set voltage, the output drive circuit is disabled, and when the power supply voltage is equal to or higher than the preset set voltage, the output drive circuit A variable delay type oscillator comprising an operation control circuit for enabling the operation of the oscillator.

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